CN115190575A

CN115190575A - Synchronization signal block receiving method and electronic equipment

Info

Publication number: CN115190575A
Application number: CN202110368335.9A
Authority: CN
Inventors: 周化雨; 沈兴亚; 潘振岗
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2021-04-06
Filing date: 2021-04-06
Publication date: 2022-10-14
Also published as: WO2022213942A1

Abstract

The embodiment of the application provides a method for receiving a synchronization signal block and electronic equipment. The method comprises the following steps: the time domain position of the synchronization signal block SSB is determined. According to the method of the embodiment of the application, the receiving of the SSB configured as the short control signaling can be realized.

Description

Synchronization signal block receiving method and electronic equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a synchronization signal block receiving method and an electronic device.

Background

In the high-frequency unlicensed spectrum, short control signaling (short control signaling) may be used according to regulations. The short control signaling may also be referred to as contention-free short control signaling (contention extension short control signaling) and may also be referred to as listen-before-talk-free operation (LBT extension operation).

Specifically, in the Rel-15 NR protocol of the 5G New Radio (NR), when the total duration of the short control signaling does not exceed 10 ms within the observation time of 100 ms, the short control signaling can be transmitted without listening Before speaking (LBT). Therefore, the use of short control signaling can ensure that some important control signaling can be sent out as soon as possible or on time, thereby improving the system reliability and causing less interference (smaller duty cycle). However, how to configure the control signaling as the short control signaling is an urgent problem to be solved.

Disclosure of Invention

In view of the prior art, the present application provides a method and an electronic device for receiving an SSB after the SSB is configured as a short control signaling.

The embodiment of the application adopts the following technical scheme:

in a first aspect, the present application provides a synchronization signal block receiving method, including:

the time domain position of the synchronization signal block SSB is determined.

In an implementation manner of the first aspect, the determining the time-domain location of the SSB includes:

the time domain location of the SSB within the SSB period is determined.

In an implementation manner of the first aspect, the determining a time-domain location of an SSB within an SSB period includes:

and determining the time domain position of the SSB in the SSB period according to the index or the number of the SSB period.

In an implementation manner of the first aspect, the determining a time-domain location of an SSB within the SSB period includes:

and determining the time domain position of the SSB in the ith SSB period to be the time domain positions of the n & ltth & gt i & lt/th & gt (i + 1) -1 SSB in a 5 millisecond window, wherein i is the number of the SSB period, i is an integer from 0 to m-1, m is a positive integer, n is a positive integer, and the 5 millisecond window is a half frame where the SSB is located.

In one implementation of the first aspect, N is N/m, where N is the total number of SSB time domain positions within the 5 millisecond window.

In one implementation of the first aspect, the N =64.

In one implementation of the first aspect, m =4.

In one implementation of the first aspect, the n =16.

In an implementation manner of the first aspect, the determining a time-domain location of the SSB within the SSB period includes:

determining the time domain position of the SSB in the 0 th SSB period as the time domain positions of the 0 th to 15 th SSBs in the 5 millisecond window;

determining the time domain positions of the SSBs in the 1 st SSB period as the time domain positions of the 16 th to 31 th SSBs in the 5 millisecond window;

determining the time domain position of the SSB in the 2 nd SSB period as the time domain positions of the 32 nd to 47 th SSBs in the 5 millisecond window;

the time domain location of the SSB in the 3 rd SSB period is determined to be the time domain location of the 48 th to 63 rd SSB within the 5 millisecond window.

In an implementation manner of the first aspect, the determining the time domain location of the SSB includes:

and determining the index or number of the SSB period according to the system frame number corresponding to the SSB.

In an implementation manner of the first aspect, the determining an index or a number of the SSB period includes:

and determining the index or number of the SSB period as F/s, wherein F is the system frame number corresponding to the SSB, and s is the frame number corresponding to one SSB period.

when the system frame number corresponding to the SSB is 0, determining that the index or number of the SSB period is 0;

when the system frame number corresponding to the SSB is 2, determining that the index or number of the SSB period is 1;

when the system frame number corresponding to the SSB is 4, determining that the index or number of the SSB period is 2;

and when the system frame number corresponding to the SSB is 6, determining that the index or number of the SSB period is 3.

In a second aspect, the present application provides a synchronization signal block receiving method, including:

the synchronization signal block SSB is determined to be short control signaling.

In an implementation manner of the second aspect, the determining that the SSB is short control signaling includes:

and determining the SSB as the short control signaling according to the master information block or the system information block.

and when the discovery burst sending window is not configured, determining the SSB as short control signaling.

In one implementation form of the second aspect, the method further comprises:

and determining a short control signaling window, and determining the SSB in the short control signaling window as the short control signaling.

In one implementation manner of the second aspect, the determining the short control signaling window includes: the period and duration of the short control signaling window is determined.

In one implementation manner of the second aspect, the determining the short control signaling window includes:

a set of short control signaling windows within a time interval is determined.

In an implementation manner of the second aspect, the determining a set of short control signaling windows within a time interval includes:

the transmission occasions and the duration of the group of short control signaling windows over the time interval on each transmission occasion are determined.

In a third aspect, the present application proposes an electronic device comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the electronic device to perform the method steps according to the first and/or second aspect.

In a fourth aspect, the present application proposes a communication chip characterized in that the communication chip comprises a memory for storing computer program instructions and a processor for executing the computer program instructions stored on the memory, wherein the computer program instructions, when executed by the processor, trigger the communication chip to perform the method steps of the first aspect and/or the second aspect.

In a fifth aspect, the present application proposes a computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program, which, when run on a computer, causes the computer to perform the method according to the first aspect and/or the second aspect.

According to the technical scheme provided by the embodiment of the application, at least the following technical effects can be realized:

according to the method of the embodiment of the application, the receiving of the SSB configured as the short control signaling can be realized.

Drawings

FIG. 1 is a simplified block diagram of a communication system according to an embodiment of the present application;

fig. 2 is a schematic diagram of SSB transmission timing according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

Fig. 1 is a diagram illustrating a communication system according to an embodiment of the present application. As shown in fig. 1, the base station 110 and the user equipment 120 communicate based on the NR protocol.

In Rel-15 NR, the ue 120 obtains time-frequency Synchronization of a cell and obtains a physical layer cell ID of the cell through a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS), which is generally called cell search.

The PSS, SSS and Physical Broadcast Channel (PBCH) constitute a synchronization signal block (SS/PBCH block, SSB).

Each synchronization signal block has a predetermined time domain position. This time domain location may also be referred to as a candidate synchronization signal block. Multiple blocks of synchronization signals constitute one SS-burst. A plurality of synchronization signal blocks form a synchronization signal burst. The plurality of synchronization signal bursts constitute an SS-burst-set (set of synchronization signal bursts). The maximum number of SSBs that can be contained in the synchronization signal burst set is Lmax, for example, for an SSB of 120kHz subcarrier spacing, the base station uses 64 SSB beams at most, and Lmax is 64.

The time domain positions of the Lmax synchronization signal blocks are defined within a 5ms window (SSB window) in one SSB period, e.g., for an SSB of 120kHz subcarrier spacing, the 5ms window (SSB window) contains the time domain positions of 64 SSBs. The time domain positions of Lmax sync signal blocks are fixed within a 5ms window. The time domain position indices of the Lmax sync signal blocks are arranged consecutively, from 0 to Lmax-1. The transmission time instant of a synchronization signal block within this 5ms window is fixed and the index is also fixed.

Generally, the base station transmits the synchronization signal block by using a beam sweeping (beam sweeping), that is, the base station transmits the synchronization signal block at different time domain locations through different beams, and accordingly, the user equipment may measure the different beams and sense on which beam the received signal is strongest.

The base station 110 transmits the SSB to the user equipment 120. In an application scenario, the SSB is assumed to have a period of 20 ms, which is a typical configuration. For a 120kHz subcarrier spaced SSB, when the base station employs 64 SSB beams, the duration of the SSB within one SSB period is 5ms, so the total duration of the SSB within 100 ms is 25 ms, much larger than the 10 ms condition for short control signaling.

To configure SSBs as short control signaling, the present application provides an SSB packet-based communication scheme. Specifically, the base station 110 divides a plurality of SSB beams originally transmitted in one SSB period into m SSB groups (m is an integer greater than 1), and transmits the m SSB groups in m consecutive SSB periods (one SSB group is transmitted in each SSB period). Thus, the transmission of the SSBs is spread over a plurality of SSB cycles, and the duration of the SSBs corresponding to a fixed time interval is reduced, thereby meeting the need for short control signaling. The user equipment 120 receives m SSB groups in consecutive m SSB periods, wherein 1 SSB group is received in each SSB period.

For example, fig. 2 is a timing diagram of a communication process according to an embodiment of the present application. For SSBs of 120kHz subcarrier spacing, 64 SSBs (beams) are transmitted in one SSB period when the SSBs are not configured as short control signaling. When the SSBs are configured as short control signaling, as shown in fig. 2, the base station 110 divides 64 SSBs into 4 SSB groups (SSB group 01 to SSB group 04), each SSB group having 16 SSBs therein, and each SSB group transmits in one SSB period (20 msec) (S201 to S204).

Thus, 64 SSBs are sent using 4 SSB periods, which take 80 ms altogether, and the total duration of the 4 SSB groups is 8 ms, which satisfies that the total duration of the SSBs is less than 10 ms within 100 ms, i.e. the condition of short control signaling is satisfied.

Further, since the base station 110 employs the SSB grouping scheme, a plurality of SSBs that should be sent in one SSB period are sent in a plurality of SSB periods, respectively, and thus, the original scheme for confirming the SSB time domain position is no longer applicable to the application scenario of a plurality of sets of SSBs. After the packet mode is introduced, the user equipment 120 needs to acquire the time domain location of the SSB.

Therefore, the present application proposes a new SSB reception method, which is performed by the user equipment 120. In the SSB reception method proposed in the present application, the user equipment 120 determines the time domain position of the SSB group.

In an application scenario of a specific implementation, a plurality of different schemes may be adopted to determine the time domain position of the SSB group. Specific implementations are listed below.

In a first implementation, after the grouping manner is introduced, different SSB periods correspond to different SSB groups, and time domain positions of the different SSB groups within a 5ms window are different. For example, the base station 110 divides a plurality of SSB beams originally transmitted in one SSB period into m SSB groups (m is a positive integer), and transmits the m SSB groups in m consecutive SSB periods (one SSB group is transmitted in each SSB period). In the ith SSB period of the m SSB periods, the time domain position of the SSB group is the time domain position of the nth i to the nth (i + 1) -1 SSB within the 5 millisecond window, wherein i is the number of the SSB periods in the m SSB periods, i is an integer from 0 to m-1, and n is the number of the SSBs in the SSB group. The 5ms window is the half frame where the SSB is located.

Taking the application scenario shown in fig. 2 as an example, for the SSB with 120kHz subcarrier spacing, when the SSB is not configured as the short control signaling, 64 SSBs are sent in one SSB period, and the time domain positions of the 64 SSBs are the time domain positions of the 0 th to 63 th SSBs within the 5 millisecond window in the SSB period. After configuring the SSBs as short control signaling, the base station 110 divides 64 SSBs into 4 SSB groups (SSB group 01 to SSB group 04), and transmits the SSBs in 4 SSB periods (S201 to S204), that is, m =4,n =16.

In one embodiment, N = N/m, where N is the total number of time domain positions of the SSB within the 5 millisecond window, e.g., N =64. Likewise, the base station 110 may divide the 64 SSBs into 4 SSB groups, i.e., m =4.

In the 0 th SSB period S201 (within the first 20 msec), the time domain position of the SSB group 01 is the time domain position of the 0 th to 15 th SSBs within the 5 msec window; in the 1 st SSB period S202 (within the second 20 ms), the time domain position of the SSB group 02 is the time domain position of the 16 th to 31 th SSBs within the 5ms window; in the 2 nd SSB period S203 (in the third 20 msec), the time domain positions of the SSB group 03 are the 32 nd to 47 th SSBs time domain positions in the 5 msec window; in the 3 rd SSB period S204 (in the fourth 20 ms), the SSB group 04 time domain positions are the 48 th to 63 rd SSB time domain positions within the 5ms window.

Thus, in the first implementation, the user equipment 120 determines the time domain location of the SSB within the SSB period. Specifically, the user equipment 120 determines the time domain location of the SSB within the SSB period according to the index or number of the SSB period.

In an embodiment of the first implementation manner, the user equipment 120 determines that the time domain position of the SSB in the i-th SSB period is the time domain position of the nth × i to the nth × (i + 1) -1 SSB in the 5ms window, where i is an index or a number of the SSB period, i is an integer from 0 to m-1, m is a positive integer, and n is a positive integer.

In another embodiment of the first implementation, the user equipment 120 determines the time domain position of the SSB in the 0 th SSB period to be the time domain position of the 0 th to 15 th SSB within the 5 msec window, determines the time domain position of the SSB in the 1 st SSB period to be the time domain position of the 16 th to 31 th SSB within the 5 msec window, determines the time domain position of the SSB in the 2 nd SSB period to be the time domain position of the 32 th to 47 th SSB within the 5 msec window, and determines the time domain position of the SSB in the 3 rd SSB period to be the time domain position of the 48 th to 63 th SSB within the 5 msec window, that is, m =4, n =16.

In another embodiment of the first implementation, N = N/m, where N is the total number of SSBs within the 5 millisecond window, e.g., N =64. Likewise, the base station 110 may divide the 64 SSBs into 4 SSB groups, i.e., m =4.

In a first implementation, the user equipment 120 needs to determine the index or number of the acquisition SSB period. To implement the first implementation manner, the ue 120 determines the index or number of the SSB period according to the system frame number corresponding to the SSB.

For example, after the packet mode is introduced, the ue 120 performs cell search to find an SSB; the user equipment 120 acquires a System Frame Number (SFN) corresponding to the SSB, and the user equipment 120 acquires the System Frame Number by decoding a physical broadcast channel in the SSB and acquires an index or a Number of an SSB period by the System Frame Number; the user equipment 120 obtains the time domain position of the SSB in the SSB period by the index or number of the SSB period; the user equipment 120 obtains timing information (intra-frame timing) from the time domain location of the SSB.

Specifically, in an embodiment of the first implementation, the user equipment 120 determines that the index or number of the SSB period is F/s, where F is a system frame number corresponding to the SSB, and s is a frame number corresponding to one SSB period. In order to satisfy the condition of short control signaling (time sparseness), one SSB period is 10 ms or more, that is, one SSB period corresponds to at least one frame, so s is a positive integer.

For example, one SSB period contains two system frames. When the system frame number corresponding to the SSB is 0, the user equipment 120 determines that the index or number of the SSB period is 0; when the system frame number corresponding to the SSB is 2, the user equipment 120 determines that the index or number of the SSB period is 1; when the system frame number corresponding to the SSB is 4, the user equipment 120 determines that the index or number of the SSB period is 2; when the system frame number corresponding to the SSB is 6, the ue 120 determines that the index or number of the SSB period is 3.

Generally, the user equipment 120 obtains the SSB actually transmitted within the 5ms window through the SSB location high layer parameter (e.g., SSB-positioninburst). In the first implementation, the meaning of the SSB location higher layer parameters will change due to the introduction of the SSB packet. Specifically, the user equipment 120 obtains the SSBs actually transmitted in m periods or the SSBs actually transmitted in a 5ms window in each of the m periods through the SSB location higher layer parameters. For example, the user equipment 120 obtains the SSBs actually transmitted in 4 periods through the SSB location high-level parameters, or obtains the SSBs actually transmitted in a 5ms window in each of the 4 periods, that is, obtains the SSBs actually transmitted in the SSB group (16 SSBs) in each period.

In a second implementation manner, multiple SSB periods corresponding to multiple SSB groups are combined into an SSB extended period (the extended SSB period at least includes m consecutive SSB periods for sending m SSB groups), and different SSB groups correspond to different system frame numbers of the SSB extended period. Note: currently, the system frame number of the SSB in one cycle is the same. The user equipment 120 determines the system frame number corresponding to the SSB group in the SSB extension period according to the index or number of the SSB period in the SSB extension period.

Specifically, in an embodiment, the base station 110 divides a plurality of SSB beams originally transmitted in one SSB period into m SSB groups (m is an integer greater than 1), and transmits the m SSB groups in m consecutive SSB periods respectively (each SSB period transmits one SSB group).

Assume that each SSB period contains two system frames, the system frame numbers of the SSB periods are 0 and 1. The extended SSB period includes m consecutive SSB periods for transmitting m SSB groups, a 0 th system frame of a first SSB period of the m consecutive SSB periods is a 0 th system frame of the extended SSB period, a 1 st system frame of the first SSB period of the m consecutive SSB periods is a 1 st system frame of the extended SSB period, a 0 th system frame of a second SSB period of the m consecutive SSB periods is a 2 nd system frame of the extended SSB period, and so on.

Since the SSB group (5 ms window) is located in the 0 th system frame of the SSB period, the system frame number of the SSB group in the extended SSB period in the ith SSB period of the m consecutive SSB periods is s (i-1), where s is the frame number corresponding to one SSB period.

Taking the application scenario shown in fig. 2 as an example, for an SSB of 120kHz subcarrier spacing, the period of one SSB is 20 ms, which contains two system frame numbers. Extending the period of SSB from 20 ms to 100 ms, and within the first 20 ms (the first SSB period S201), the system frame number of the SSB group is 0; within the second 20 ms (second SSB period S202), the sfn of the SSB group is 2; in the third 20 ms (third SSB period S203), the system frame number of the SSB group is 4; within the fourth 20 ms (fourth SSB period S204), the system frame number of the SSB group is 6.

According to the first implementation manner and the second implementation manner, the total duration of the 4 SSB groups is 8 milliseconds within 100 milliseconds, and the condition that the total duration of the SSBs is less than 10 milliseconds within 100 milliseconds, that is, the short control signaling condition is satisfied, can be satisfied. Neither of these implementations changes the 5-millisecond time index inside the SSB (provided by the 4-bit information of the PBCH Demodulation Reference Signal (DMRS) sequence and the 4-bit information of the PBCH payload) nor the field indication inside the SSB (provided by the 1-bit information of the PBCH payload). Since the indication of the system frame number in the SSB changes, the ue performs soft combining (forming an SSB extension period) among multiple periods, and needs to perform special processing on the low bit position of the system frame number, so as to avoid bit difference at the low bit position of the system frame number during soft combining, which is the same as the current processing of the ue.

Further, after the base station 110 configures the SSB as the short control signaling, the ue 120 needs to know that the SSB is the short control signaling. To this end, the present application also proposes an SSB receiving method in which the user equipment 120 determines the SSB as short control signaling.

When the user equipment 120 determines that the SSB is short control signaling, the receiving method of the SSB in the first or second implementation may be used (when the SSB is 120kHz subcarrier spacing).

In an implementation scenario, the SSB may be determined as short control signaling by using various schemes. Specific implementations are listed below.

In a third implementation, the ue 120 determines the SSB to be the short control signaling according to a Master Information Block (MIB) or a System Information Block (SIB).

In the fourth implementation, the user equipment 120 determines the SSB as the short control signaling according to a Burst Transmission Window (DBTW). Specifically, the Burst Transmission Window (DBTW) is to cope with LBT, so that the base station has more opportunities to transmit the SSB, and when the SSB is a short control signaling, the base station can transmit the SSB without LBT, and the DBTW has no meaning. Therefore, when the user equipment 120 knows that the Discovery Burst Transmission Window (DBTW) is not configured, the user equipment 120 knows that the SSB is short control signaling.

In a fourth implementation, the user equipment 120 determines a short control signaling window and determines the SSB within the short control signaling window to be short control signaling.

Specifically, a short control signaling window is defined, the base station 110 configures the short control signaling window, and sends the SSB that needs to be configured as the short control signaling in the short control signaling window. The user equipment 120 receives the SSB within a short control signaling window. By configuring the short control signaling window, the base station 110 can tell the user equipment 120 that the SSB need only be measured within the short control signaling window.

In a simplified manner, the period and duration of the short control signaling window, at which the short control signaling window has a relatively fixed transmission occasion and duration on each transmission occasion within a time interval, can be directly defined.

In a more complex manner, a set of short control signaling windows is defined within a time interval (e.g., a first time interval), and the transmission occasions and the duration of the set of short control signaling windows on each transmission occasion within the time interval are defined. For example, a group of short control signaling windows is defined to have a transmission opportunity of 20 ms each (i.e. transmission starting point is 0 th, 20 th, 40 th, 60 th, 80 th ms) within 100 ms, and a duration of 2 ms on each transmission opportunity, so that the total transmission time is 10 ms within 100 ms, and the short control signaling condition is satisfied. Or, the period of the short control signaling window is directly defined to be 20 milliseconds, the duration is 2 milliseconds, the effect is the same, and the total sending time is 10 milliseconds within 100 milliseconds, so that the short control signaling condition is met.

The user equipment 120 determines a set of short control signaling windows within a first time interval (e.g., 100 milliseconds). For example, the user equipment 120 determines the transmission occasions of a set of short control signaling windows within a first time interval and the duration on each transmission occasion. As another example, the user equipment 120 determines the period and duration of the short control signaling window.

Further, the first time interval is a duration associated with the definition of the short control signaling, e.g., 100 milliseconds, which is not a periodic time period. Therefore, directly defining the period and duration of the short control signaling window may lead to inconsistent occurrence of the short control signaling window in different 100 ms, and thus, the period and duration of the short control signaling window may be limited to be valid only in a first time interval. Specifically, in one embodiment, the user equipment 120 also determines whether the period and duration of the short control signaling window is valid for only one first time interval.

Further, in an embodiment, to simplify the configuration overhead, only the transmission occasions of the short control signaling window are configured, and the duration on each transmission occasion is defined to be the same. Under this definition, the ue 120 knows the transmission occasions (number) within a first time interval (e.g., within 100 ms), and can derive the duration (e.g., 100 ms divided by the number of transmission occasions) of each transmission occasion.

It is to be understood that some or all of the steps or operations in the above-described embodiments are merely examples, and other operations or variations of various operations may be performed by the embodiments of the present application. Further, the various steps may be performed in a different order presented in the above-described embodiments, and it is possible that not all of the operations in the above-described embodiments are performed.

Further, in the 90 s of the 20 th century, improvements in a technology could clearly distinguish between improvements in hardware (e.g., improvements in circuit structures such as diodes, transistors, switches, etc.) and improvements in software (improvements in process flow). However, as technology advances, many of today's process flow improvements have been seen as direct improvements in hardware circuit architecture. Designers almost always obtain the corresponding hardware circuit structure by programming an improved method flow into the hardware circuit. Thus, it cannot be said that an improvement in the process flow cannot be realized by hardware physical blocks. For example, a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit whose Logic functions are determined by programming the Device by an accessing party. A digital device is "integrated" on a PLD by the designer's own programming without requiring the chip manufacturer to design and fabricate a dedicated integrated circuit chip. Furthermore, nowadays, instead of manually manufacturing an Integrated Circuit chip, such Programming is often implemented by "logic compiler" software, which is similar to a software compiler used in program development and writing, but the original code before compiling is also written by a specific Programming Language, which is called Hardware Description Language (HDL), and HDL is not only one but many, such as ABEL (Advanced Boolean Expression Language), AHDL (alternate Hardware Description Language), traffic, CUPL (core universal Programming Language), HDCal, jhddl (Java Hardware Description Language), lava, lola, HDL, PALASM, rhyd (Hardware Description Language), and vhigh-Language (Hardware Description Language), which is currently used in most popular applications. It will also be apparent to those skilled in the art that hardware circuitry for implementing the logical method flows can be readily obtained by a mere need to program the method flows with some of the hardware description languages described above and into an integrated circuit.

The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium that stores computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may thus be considered a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.

Specifically, the apparatuses proposed in the embodiments of the present application may be wholly or partially integrated into one physical entity or may be physically separated when actually implemented. And these modules can all be implemented in the form of software invoked by a processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of software called by the processing element, and part of the modules can be realized in the form of hardware. For example, the detection module may be a separate processing element, or may be integrated into a chip of the electronic device. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits determined to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, these modules may be integrated together and implemented in the form of a System-On-a-Chip (SOC).

An embodiment of the present application also proposes an electronic device (e.g., user equipment 120) comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the electronic device to perform the method steps as described in the embodiments of the present application.

In particular, in an embodiment of the present application, the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the apparatus, cause the apparatus to perform the method steps described in the embodiment of the present application.

Specifically, in an embodiment of the present application, a processor of the electronic device may be an on-chip device SOC, and the processor may include a Central Processing Unit (CPU), and may further include other types of processors. Specifically, in an embodiment of the present application, the processor of the electronic device may be a PWM control chip.

Specifically, in an embodiment of the present application, the processors may include, for example, a CPU, a DSP, a microcontroller, or a digital Signal processor, and may further include a GPU, an embedded Neural-Network Processor (NPU), and an Image Signal Processing (ISP), and the processors may further include necessary hardware accelerators or logic Processing hardware circuits, such as an ASIC, or one or more integrated circuits for controlling the execution of the program according to the present application. Further, the processor may have the functionality to operate one or more software programs, which may be stored in the storage medium.

Specifically, in one embodiment of the present application, the memory of the electronic device may be a read-only memory (ROM), other types of static memory devices that may store static information and instructions, a Random Access Memory (RAM), or other types of dynamic memory devices that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disk read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disks, laser disks, optical disks, digital versatile disks, blu-ray disks, etc.), magnetic disk storage media or other magnetic storage devices, or any computer-readable medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In particular, in an embodiment of the present application, the processor and the memory may be combined into a processing device, and more generally, independent components, and the processor is configured to execute the program code stored in the memory to implement the method described in the embodiment of the present application. In particular implementations, the memory may be integrated with the processor or may be separate from the processor.

Further, the apparatus set forth in the embodiments of the present application may be implemented by a computer chip or an entity, or by a product with certain functions.

An embodiment of the present application further proposes a communication chip, which is applied to the user equipment 120, the chip comprising a processor for and for executing program instructions stored on a memory, wherein the computer program instructions, when executed by the processor, trigger the communication chip to perform the method steps as described in the embodiments of the present application.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the medium.

In the several embodiments provided in the present application, any function, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application.

Specifically, an embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute the method provided by the embodiment of the present application.

An embodiment of the present application further provides a computer program product, which includes a computer program and when the computer program runs on a computer, the computer is caused to execute the method provided by the embodiment of the present application.

The description of embodiments herein is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices), and computer program products according to embodiments herein. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the embodiments of the present application, "at least one" means one or more, "and" a plurality "means two or more. "and/or" describes the association relationship of the associated objects, and indicates that three relationships may exist, for example, a and/or B, and may indicate that a exists alone, a and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a, b, c, a and b, a and c, b and c or a and b and c, wherein a, b and c can be single or multiple.

In the embodiments of the present application, the terms "include", "include" or any other variations are intended to cover non-exclusive inclusions, so that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.

The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein may be implemented as electronic hardware, a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The above description is only for the specific embodiments of the present application, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A synchronization signal block receiving method, comprising:

the time domain position of the synchronization signal block SSB is determined.

2. The method of claim 1, wherein determining the time-domain location of the SSB comprises:

the time domain location of the SSB within the SSB period is determined.

3. The method of claim 2, wherein determining the temporal location of the SSB within the SSB period comprises:

4. The method of claim 3, wherein the determining the temporal location of the SSB within the SSB period comprises:

5. The method of claim 4, wherein N is N/m, where N is a total number of SSB time domain positions within the 5 millisecond window.

6. The method of claim 5, wherein N =64.

7. The method of claim 4, wherein m =4.

8. The method of claim 4, wherein n =16.

9. The method of claim 4, wherein the determining the temporal location of the SSB within the SSB period comprises:

determining the time domain positions of the SSBs in the 0 th SSB period as the time domain positions of the 0 th to 15 th SSBs in the 5 millisecond window;

determining the time domain position of the SSB in the 1 st SSB period as the time domain positions of the 16 th to 31 th SSBs in the 5 millisecond window;

10. The method of claim 1, wherein determining the temporal location of the SSB comprises:

11. The method of claim 10, wherein the determining the index or number of the SSB period comprises:

12. The method of claim 10, wherein the determining the index or number of the SSB period comprises:

13. A synchronization signal block receiving method, comprising:

14. The method of claim 13, wherein determining the SSB as short control signaling comprises:

15. The method of claim 13, wherein determining the SSB to be short control signaling comprises:

16. The method of claim 13, further comprising:

17. The method of claim 16, wherein the determining the short control signaling window comprises: the period and duration of the short control signaling window is determined.

18. The method of claim 16, wherein the determining the short control signaling window comprises:

a set of short control signaling windows within a time interval is determined.

19. The method of claim 18, wherein determining a set of short control signaling windows within a time interval comprises:

the transmission occasions and the duration of the group of short control signaling windows over the time interval are determined.

20. An electronic device, characterized in that the electronic device comprises a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the electronic device to perform the method steps of any of claims 1-19.

21. A communication chip, characterized in that the communication chip comprises a memory for storing computer program instructions and a processor for executing the computer program instructions stored on the memory, wherein the computer program instructions, when executed by the processor, trigger the communication chip to perform the method steps of any of claims 1 to 19.

22. A computer-readable storage medium, in which a computer program is stored which, when run on a computer, causes the computer to carry out the method according to any one of claims 1 to 19.