CN115190071B

CN115190071B - Cache method and integrated circuit

Info

Publication number: CN115190071B
Application number: CN202110361730.4A
Authority: CN
Inventors: 喻径舟; 刘杨; 杨斐然; 郭玲波; 邢豫盛; 周立伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-04-02
Filing date: 2021-04-02
Publication date: 2025-08-22
Anticipated expiration: 2041-04-02
Also published as: WO2022206397A1; CN115190071A

Abstract

The embodiment of the application provides a caching method and an integrated circuit, which can avoid false hits. The caching method comprises the steps of obtaining a first message, wherein the first message comprises a target Internet Protocol (IP) address, searching a routing prefix matched with the target IP address from a cache, searching a tree structure corresponding to a routing table according to the target IP address in response to the routing prefix not being stored in the cache, determining a prefix node matched with the target IP address, determining a first prefix matching length by a processor in response to the prefix node not being a leaf node, wherein the first prefix matching length is equal to the length between a root node and a tail node of the tree structure, determining a first routing prefix according to the first prefix matching length and the target IP address, and triggering the cache to store a first corresponding relation, wherein the first corresponding relation is the first routing prefix and routing information corresponding to the prefix node.

Description

Caching method and integrated circuit

Technical Field

The present application relates to the field of communications technologies, and in particular, to a caching method and an integrated circuit.

Background

When a network device such as a router or a switch forwards a message, a destination internet protocol (Internet Protocol, IP) address carried in the message can be obtained, and routing information corresponding to the destination IP address is searched from a routing table, so that the message is forwarded according to the searched routing information. The routing table is an entry describing a routing prefix and routing information, and is stored in the network device in advance. The routing prefix is used to determine routing information that matches the destination IP address, which may be, for example, the first n bits of the IP address, where n is the length of the routing prefix. The routing information may be an identification of the network interface, indicating through which network interface the network device needs to forward the message.

When the routing table is searched, whether the destination IP address is matched with the routing prefix is judged. For example, assuming that a certain routing prefix has a length of m, and the first m bits of the destination IP address are consistent with the routing prefix, the destination IP address may be considered to be matched with the routing prefix, and the corresponding routing information is the routing information corresponding to the routing prefix. When the destination IP address matches two or more routing prefixes simultaneously, the routing prefix may be determined according to the longest prefix match (Longest Prefix Match, LPM) principle. That is, the route information of the longest route prefix among the plurality of route prefixes matching the destination IP address may be set as the route information corresponding to the destination IP address.

Since the lookup routing table needs to compare whether the routing prefix matches the destination IP address, the network device needs to look up the routing table. Obviously, the faster the routing table is called, the faster the network device forwards the message. Currently, in order to increase the speed of the network device calling the routing table, the correspondence between the partial routing prefix and the routing information may be stored in a cache. But this approach tends to suffer from false hits.

Disclosure of Invention

The embodiment of the application provides a caching method and an integrated circuit, which avoid false hit by recording the corresponding relation between a first routing prefix with the length longer than a destination IP address in a routing table and routing information in a cache.

In a first aspect, an embodiment of the present application provides a caching method, where the method may be applied to a processor in a network device. When the caching method is executed, the processor can firstly acquire the first message and determine the destination IP address carried in the first message. The processor may then look up the route prefix from the cache that matches the destination IP address. If the route prefix matched with the destination IP address is not stored in the cache, the processor can search the tree structure corresponding to the route table from other memories according to the destination IP address, so as to determine the prefix node matched with the destination IP address in the tree structure, namely the node of the route prefix matched with the destination IP address in the tree structure corresponding to the route table. When the prefix node is not a leaf node in the tree structure, i.e., the prefix node has child nodes, the processor may determine the length of the root node to the tail node of the tree structure as the first prefix matching length. The tail node is the last node on the searching path in the tree structure. The search path is a path from the root node to the leaf node in the tree structure corresponding to the routing table along the tree structure corresponding to the destination IP address in the tree structure corresponding to the routing table. After the first prefix matching length is obtained, the processor may determine a first routing prefix according to the destination IP address and the first prefix matching length, and trigger the cache to store a first correspondence, where the first correspondence is a correspondence between the first routing prefix and routing information corresponding to the prefix node. That is, when the prefix node is not a leaf node, the route prefix in the correspondence relationship is different from the route prefix described in the route table. That is, when there are other routing prefixes included in the routing table and having a length greater than the routing prefix corresponding to the destination IP address, the processor may determine a new first routing prefix according to the first prefix matching length, and store the correspondence between the new routing prefix and the routing information in the cache. Thus, the length of the first routing prefix may be greater than the length of the routing prefix in the memory routing table that matches the destination IP address. In this way, the probability of false hits occurring can be reduced compared to the prior art.

In one possible implementation, the length of the first routing prefix may be greater than the first prefix matching length. It is readily understood that the longer the length of the first routing prefix, the less probability of false hits occurring. When the length of the first routing prefix is greater than the first prefix matching length, the probability of false hits is 0.

In one possible implementation, when the destination IP address is a leaf node at a tail node in the tree structure corresponding to the routing table, the length of the first routing prefix may be equal to the first prefix matching length.

In one possible implementation, the corresponding tree structure of the routing table may be divided into a virtual tree structure and a plurality of subtree structures. The processor may determine a prefix node matching the destination IP address through the virtual tree structure and the sub-tree structure. The virtual tree structure may include any plurality of nodes in a tree structure corresponding to the routing table, where a root node of each sub-tree structure in the plurality of sub-tree structures corresponds to one node in the virtual tree structure. Specifically, the processor may first find a virtual tree structure corresponding to the routing table according to the destination IP address, and determine a virtual prefix that matches the destination IP address longest. Then, the processor may determine, according to the virtual prefix, that the routing prefix corresponding to the root node is a subtree structure of the virtual prefix, and find, from the subtree structure, a prefix node that matches the destination IP address. Then, assuming that the first length is the length from the root node of the virtual book structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node on the lookup path of the subtree structure, then the sum of the first length and the second length is the matching length of the first prefix. In this way, the tree structure corresponding to the routing table is divided into a virtual tree structure and a plurality of subtrees, so that the searching efficiency of the routing prefix can be improved.

In some possible implementations, the processor may further store a correspondence of the second routing prefix and the routing information. The routing prefix of the non-local node is the routing prefix corresponding to the unique child node on the forwarding path, and the unique child node is a child node only having a left child node or a right child node. Specifically, when the prefix node matching the destination IP address is not a leaf node, the processor may determine a unique node on the forwarding path according to the forwarding path of the destination IP address, and determine a second prefix matching length according to the belly node. The second prefix matching length is equal to the length from the root node to the unique child node. After determining the second prefix matching length, the processor may determine a second routing prefix according to the second prefix matching length, thereby storing a second correspondence.

In some possible implementations, the processor may also trigger the cache to store the type of first routing prefix. And after the processor receives other messages, if the destination IP address of the message hits the first routing prefix, the processor can acquire the routing information corresponding to the first routing prefix from the cache according to the first corresponding relation according to the indication of the type of the first routing prefix.

In some possible implementations, when the processor determines the prefix node through the virtual tree structure and the subtree structure, the processor may trigger the cache to store a third correspondence between the virtual prefix, the type of virtual prefix, and the information of the subtree structure. Similarly, if the destination IP address of the message hits in a virtual prefix, the processor may look up the sub-tree structure from the information of the sub-tree structure according to the indication of the type of the virtual prefix, thereby determining the routing information corresponding to the first routing prefix.

In some possible implementations, the processor may also trigger the cache to store the length of the first routing prefix, taking into account the maximum length matching principle.

In some possible implementations, the length of the first routing prefix is equal to the first prefix matching length plus 1.

In some possible implementations, the length of the first routing prefix is less than the length of the destination IP address.

In some possible implementations, the destination IP address includes the first routing prefix.

In some possible implementations, the cache includes at least one of a ternary content addressable memory (Ternary Content Addressable Memory, TCAM), a register, a line card, and a die.

The embodiment of the application provides an integrated circuit, which is applied to a processor and comprises an interface circuit and a control circuit, wherein the interface circuit is used for acquiring a first message, the first message comprises a destination Internet Protocol (IP) address, the control circuit is used for searching a route prefix matched with the destination IP address from a cache, searching a tree structure corresponding to a routing table according to the destination IP address in response to the route prefix not being stored in the cache, determining a prefix node matched with the destination IP address, determining a first prefix matching length in response to the prefix node not being a leaf node, the first prefix matching length is equal to the length between a root node and a tail node of the tree structure, the tail node is the last node on a searching path of the tree structure, determining a first route prefix according to the first prefix matching length and the destination IP address, and triggering the cache to store a first corresponding relation, wherein the first corresponding relation is the first route prefix and the route information corresponding to the prefix node.

In some possible implementations, the length of the first routing prefix is greater than or equal to the first prefix matching length.

In some possible implementations, the control circuit is configured to search a virtual tree structure corresponding to a routing table according to the destination IP address, determine a virtual prefix that matches the destination IP address longest, search a sub-tree structure corresponding to the virtual prefix according to the destination IP address, determine a prefix node that matches the destination IP address, where the virtual prefix is a root node of the sub-tree structure, and the first prefix matching length is equal to a sum of a first length and a second length, where the first length is a length from the root node of the virtual tree structure to the virtual prefix, the second length is a length from the virtual prefix to a tail node, and the tail node is a last node on a search path of the sub-tree structure.

In some possible implementations, the control circuit is further configured to determine, in response to the prefix node not being a leaf node, a second prefix matching length, where the second prefix matching length is equal to a length between a root node of the tree structure and a unique child node, where the unique child node is a node between the prefix node and the tail node having only a left child node or only a right child node, determine, according to the second prefix matching length and the destination IP address, a second routing prefix, where the second routing prefix has a length greater than the second prefix matching length, and trigger the cache to store routing information corresponding to the second routing prefix and the prefix node.

In some possible implementations, the control circuit is further configured to trigger the cache to store a type of the first routing prefix, where the type of the first routing prefix is used to indicate that, when the first routing prefix is hit, route information corresponding to the first routing prefix is obtained in the cache according to the first correspondence.

In some possible implementations, the control circuit is further configured to trigger the cache to store a third correspondence, where the third correspondence is a correspondence among the virtual prefix, a type of the virtual prefix, and information of the subtree structure, and the type of the virtual prefix is used to indicate that when the virtual prefix is hit, the subtree structure is searched according to the information of the subtree structure.

In some possible implementations, the control circuit is further configured to trigger the cache to store a length of the first routing prefix.

In some possible implementations, the cache includes at least one of a TCAM, a register, a line card, and a die.

In a third aspect, an embodiment of the present application provides a buffering apparatus, where the buffering apparatus includes an obtaining unit and a processing unit. The acquiring unit is configured to acquire a first packet, where the first packet includes a destination IP address. The processing unit is used for searching a routing prefix matched with the destination IP address from a cache, searching a tree structure corresponding to a routing table according to the destination IP address in response to the routing prefix not stored in the cache, determining a prefix node matched with the destination IP address, determining a first prefix matching length in response to the prefix node not being a leaf node, wherein the first prefix matching length is equal to the length between a root node and a tail node of the tree structure, the tail node is the last node on a searching path of the tree structure, determining a first routing prefix according to the first prefix matching length and the destination IP address, triggering the cache to store a first corresponding relation, and the first corresponding relation is the first routing prefix and routing information corresponding to the prefix node.

In a fourth aspect, embodiments of the present application provide a chip, the chip including a memory for storing instructions or program code, and a processor for calling and executing the instructions or program code from the memory to perform the caching method as described in the foregoing first aspect.

In a fifth aspect, embodiments of the present application provide an apparatus comprising a processor chip and a memory, the memory being for storing instructions or program code, the processor chip being for invoking and executing the instructions or program code from the memory to perform the caching method as described in the foregoing first aspect.

In a sixth aspect, embodiments of the present application provide a computer readable storage medium comprising instructions, a program or code which, when executed on a computer, causes the computer to perform the caching method of the foregoing first aspect.

Drawings

FIG. 1 is a schematic diagram of a processor according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a tree structure corresponding to a routing prefix according to an embodiment of the present application;

fig. 3-a is a schematic diagram of a network system 300 according to an embodiment of the present application;

Fig. 3-b is a schematic structural diagram of a network device 350 according to an embodiment of the present application;

Fig. 3-c is another schematic structural diagram of a network device 350 according to an embodiment of the present application;

fig. 3-d is a schematic diagram of another structure of a network device 350 according to an embodiment of the present application;

fig. 3-e is a schematic structural diagram of a network device 360 according to an embodiment of the present application;

fig. 3-f is a schematic structural diagram of a chip 370 of a network device according to an embodiment of the present application;

fig. 3-g is a schematic structural diagram of a virtual router 380 according to an embodiment of the present application;

Fig. 4 is a flow chart of a caching method according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a tree structure corresponding to a routing table according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a subtree structure according to an embodiment of the present application;

Fig. 7 is a schematic structural diagram of a tree structure corresponding to a routing table according to an embodiment of the present application;

fig. 8 is a schematic diagram of an integrated circuit 800 according to an embodiment of the application;

Fig. 9 is a schematic structural diagram of a buffering device 900 according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a chip 1000 according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an apparatus 1100 according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of an apparatus 1200 according to an embodiment of the present application.

Detailed Description

The following describes a conventional technology and a caching method provided by an embodiment of the present application with reference to the accompanying drawings.

The basic structure of the device including the cache will be described first. Referring to fig. 1, a schematic diagram of an apparatus 100 is shown. The device 100 comprises a processor 110 and a memory 120, the processor 110 comprising a processing unit 111 and a cache 112. Wherein the buffer 112 may be used for loading data from the memory 120, and the processing unit 111 may be used for reading data from the buffer 112 and processing the data. Alternatively, when the processor 110 is packaged as a chip, the chip may be referred to as a central processing unit (central processing unit, CPU).

Cache, known as cache, is mostly composed of memory devices with faster data exchange speed. In an embodiment of the present application, the cache may also be referred to as temporary memory (temporary storage) or temporary storage. The cache is respectively connected with a processing unit inside the processor and a memory outside the processor, and can store part or all of data stored in the memory.

The memory may be divided into a memory device such as a hard disk (HARD DISK DRIVE, HDD) and a memory device such as a synchronous dynamic random access memory (synchronous dynamic random-access memory, SDRAM) or Double speed synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR). And the cache is a storage device such as a static memory (Static Random Access Memory, SRAM). In the process of data exchange with the processor, the data exchange speed of the SRAM is larger than that of the DDR (or SDRAM), and the data exchange speed of the DDR is larger than that of the hard disk. For when the network device stores part or all of the routing table through the cache, a routing table with empty content may be created in the cache. In the embodiment of the present application, the routing table stored in the cache may be referred to as a cache routing table, and the routing table stored in the memory may be referred to as a memory routing table.

When the processor determines that the destination IP address matches a routing prefix in the memory routing table, the processor may store the routing prefix and routing information in the cache routing table. Thus, when the network device receives the new message and the destination IP address of the new message matches the routing prefix stored in the cache routing table, the processor can obtain the corresponding routing information from the cache routing table. Therefore, the data exchange speed between the processor and the cache is high, so that the searching speed of the routing table is improved. When the first n bits of the IP address are respectively consistent with the routing prefix, the IP address can be said to be matched with the routing prefix

Optionally, the Cache routing table may include a Cache Tag (Cache Tag) entry and a Cache data (CACHE DATA) entry. Wherein the cache tag entry may include a routing prefix and the cache data entry may be used to store routing information. Correspondingly, the corresponding relationship between the cache tag item and the cache data item may represent the corresponding relationship between the routing prefix and the routing information.

The cache tag entry may also include a length (length) of the routing prefix, considering that the network device needs to determine the routing prefix matching the destination IP address according to the longest matching principle. In this way, when the destination IP address matches multiple route prefixes in the routing table in the cache at the same time, the processor may determine the longest length route prefix as the route prefix that matches the destination IP address.

For example. It is assumed that the network device has a network interface a and a network interface B, and the corresponding relationship between the routing prefix 0001010 and the network interface a and the corresponding relationship between the routing prefix 0 and the network interface B are recorded in the memory of the network device.

If the network device receives the message M, the destination IP address of the message M is 0001010010100010. The processor of the network device may first look up the route prefix and route information from the memory routing table that matches the destination IP address. After determining that the destination IP address 0001010010100010 matches the routing prefix 0001011, the processor may store the routing prefix 0001010, the length of the routing prefix 0001010, and the routing information (i.e., network interface a) corresponding to the routing prefix 0001010 in a cached routing table. The cache routing table may be as shown in table 1.

TABLE 1

Cache tag	Cache data
		0001010*,len=7	A

Where the first row in table 1 indicates that the routing prefix 000101101 corresponds to network interface a, then a packet with a first bit of 0 of the destination IP address may be forwarded through network interface a, e.g., a packet with a destination IP address of 0001010010100010 may be forwarded through network interface a.

If the network device receives the message N again, the destination IP address of the message N is 0001011010010001. Since the first 7 bits of the destination IP address are 0001011, which is inconsistent with the routing prefix 0001010, the processor of the network device may look up the routing prefix matching the destination IP address 0001011010010001 from the memory routing table. After determining that the destination IP address 0001011010010001 matches the routing prefix 0, the processor may store the routing prefix 0, the length of the routing prefix 0, and routing information (i.e., the network interface a) corresponding to the routing prefix 0 in the cache routing table. The cache routing table may be as shown in table 2.

TABLE 1

Cache tag	Cache data
		0001010*,len=7	A
0*,len=1	B

If the network device receives a packet with an IP address 0001011011110100 again, the first bit of the destination IP address is consistent with the routing prefix 0, and the first seven bits of the destination IP address are inconsistent with the routing prefix 0001010, the processor may determine that the packet corresponds to the routing prefix 0, so as to forward the packet through the network interface B. Obviously, because the speed of the processor for acquiring the data from the cache is higher, the speed of the network equipment for forwarding the message can be improved by storing the corresponding relation between part or all of the routing prefixes and the routing information in the cache routing table.

However, since the information in the cache routing table increases gradually with the forwarding of the message, the cache routing table and the memory routing table are not consistent in this process. Then, if the longer route prefix is not stored in the cache routing table and the shorter route prefix is stored in the cache routing table in the two routes with higher similarity, the processor may erroneously determine the shorter route prefix as the route prefix matching the message, and thus forward the message according to the wrong route information, which is called false hit.

For example, assume that the destination IP address of a message matches a route prefix X and a route prefix Y, and that route prefix X has been stored in the cache routing table, route prefix Y has not been stored in the cache routing table. If the length of the routing prefix X is shorter than the length of the routing prefix Y, the routing information to which the message theoretically corresponds should be the routing information to which the routing prefix Y corresponds. But the processor, upon receiving the message, preferentially looks up the route prefix matching the destination IP address from the cached routing table. Because the cache routing table includes the routing prefix X, the processor may be able to find the routing prefix X that matches the destination IP address from the cache routing table, thereby forwarding the message using the routing information corresponding to the routing prefix X. It can be seen that, because the cache routing table is different from the routing prefixes stored in the memory routing table, a network device may have a false hit when forwarding a packet with a destination IP address matching multiple routing prefixes.

The network device will be described by taking the example of receiving the message M and the message N. Assuming that the network device receives the packet N first, the cache routing table may be as shown in table 3:

TABLE 3 Table 3

Cache tag	Cache data
		0*,len=1	B

If the network device receives the message M again, because the destination IP address of the message M is 0001010010100010, the first bit of the message M is 0, which is consistent with the routing prefix 0 recorded in the cache routing table, the processor may consider that the message M matches with the routing prefix 0, so that the message M is forwarded by using the network interface B. Obviously, the network interface to which the message M actually corresponds should be the network interface a. There are cases of false hits due to incomplete information included in the cache routing table.

In order to solve the above-mentioned problems, an embodiment of the present application provides a caching method, where the method can record in a cache a corresponding relationship between a first routing prefix having a length greater than that of a destination IP address in a routing table and routing information, so as to avoid occurrence of false hits.

The following, first, will briefly introduce terms related to the present application:

Tree structure a tree (tree) structure is a non-linear data structure. A tree structure may include a plurality of nodes, each of which may be used to store data. The connection relationship between the nodes of the tree structure represents a relationship between the data stored in the nodes, and may represent, for example, a sequential relationship or a subordinate relationship of the data. The topmost node in the tree structure is called the root node. A tree structure may comprise a plurality of sub-tree structures, each sub-tree structure may in turn comprise one or more sub-tree structures. The topmost node of each sub-tree structure may be referred to as the root node of the sub-tree structure. Typical tree structures may include binary, trigeminal, and quadtree.

In the embodiment of the application, the routing prefix can be represented by a tree structure such as a binary tree, and the specific value of each bit of the routing prefix is embodied by the connection relation between two adjacent layers of nodes in the tree structure. Similarly, routing tables may also be represented by tree structures by similar rules. For example, each routing prefix in the routing table may be represented by a tree structure, and then root nodes of the tree structures are stacked together, so that the resulting tree structure is the corresponding tree structure of the routing table. In order to distinguish among the routing prefixes in the routing table, the node corresponding to the last bit of each routing prefix may be labeled as a prefix node. The tree structure corresponding to the routing table may be used to express the distribution of prefix nodes in the routing table.

In the embodiment of the application, the routing prefix and the routing table can be represented by a binary tree or a quadtree or a hexadecimal tree. The binary tree is described below. It should be noted that, for convenience of understanding, the tree structure of the routing table is taken as a binary tree for example, and the tree structure of the routing table is not represented as a binary tree in all embodiments of the present application. When the routing prefix is represented by a quadtree structure, each child node corresponds to a two-digit number in the routing prefix, e.g., four child nodes of the root node may represent "00", "01", "10", and "11", respectively. If the routing table is represented in a tree structure, the tree structure may be split into a virtual tree structure and a plurality of sub-tree structures. The description of the virtual tree structure may be taken in the following and will not be repeated here.

Binary tree (binary tree) is an ordered tree with a degree of nodes in the tree structure not greater than 2. That is, the binary tree has one root node, and any one node in the binary tree has at most two child nodes, and when one node has two child nodes, the child node on the left side may be referred to as a left child node, and the child node on the right side may be referred to as a right child node. Any node in the binary tree. A binary tree may include a plurality of sub-binary trees.

When the routing prefix is represented by a binary tree, each bit of the IP address corresponds to a level of the binary tree, starting from a child node of the root node. If a bit of the IP address is 0, the binary tree extends to the left at this level, and if a bit of the routing prefix is 1, the binary tree extends to the right at this level. That is, if the first bit of the routing prefix is 0, then the root node of the binary tree to which the routing prefix corresponds has a left child node and does not have a right child node.

The tree structure corresponding to, for example, routing prefix 10010 may be as shown in fig. 2. The node 2 is a right child node of the root node 1, a first bit representing an IP address is connected to the node 1, the node 3 is a left child node of the node 2, a second bit representing the IP address is connected to the node 0, the node 4 is a left child node of the node 3, a third bit representing the IP address is connected to the node 0, the node 5 is a right child node of the node 4, a fourth bit representing the IP address is connected to the node 1, the node 6 is a left child node of the node 5, and a fifth bit representing the IP address is connected to the node 0.

Similarly, when the routing table is represented by a binary tree, the routing table may be as shown in FIG. 5. For this part, reference is made to the following, and no further description is given here.

Unique child node-a unique child node is a node in the binary tree that has only left child nodes or only right child nodes.

Leaf node-a node in the tree structure that does not have child nodes.

And the prefix node is a node corresponding to the routing prefix in a tree structure corresponding to the routing table.

And searching paths, namely searching paths from the root node to leaf nodes in the tree structure corresponding to the routing table along the tree structure corresponding to the destination IP address in the tree structure corresponding to the routing table.

Tail node, which is the last node in the search path.

The method provided by the embodiment of the application can be applied to the system 300 shown in fig. 3-a. The system 300 includes a network device 310, a network device 320, a network device 330, and a network device 340.

In an embodiment of the present application, network device 320 includes a processor 321, a cache 322, and a memory 323. The processor 321 is a unit having data processing capability inside the network device 320, for example, may be a unit for data processing in a processor core (core), the cache 322 may be a high-speed storage device such as SRAM, and the storage 323 may include any one or more of a memory and an external memory.

It should be noted that, the cache 322 in fig. 3-a is independent from the processor 321, and does not necessarily indicate that the cache provided in the embodiment of the present application is necessarily encapsulated in the processor. In some possible implementations, the cache may also be a storage device that is packaged inside the processor. In addition, in the embodiment shown in fig. 1, the network device 320 includes a processor 321 and a cache 322, which is not intended to represent that the device provided in the embodiment of the present application includes only one processor and one cache. In some possible implementations, a device may include one or more processors, which may include one or more processing units, and one or more caches. One cache may correspond to one processing unit or a plurality of processing units, and one processing unit may also correspond to one or a plurality of caches. The embodiment of the application does not limit the specific architecture of the processor.

In some possible implementations, the network device may have a multi-level cache structure, i.e., multiple caches of different levels are built using multiple storage media, with higher levels exchanging data at a faster rate and smaller size. Then, for a computer with a multi-level cache structure, the cache in the embodiment of the present application may be a level one cache (level one cache is the highest level cache), and the memory may include other caches with a level lower than the level one cache, for example, a level two cache, a level three cache, and so on. That is, in the embodiment of the present application, the storage device with the highest data exchange speed is cached, and the storage device is a generic term of all other storage devices with data exchange speed lower than that of the cache.

In the embodiment of the application, in order to facilitate quick searching of the routing table entry, the cache may further include a ternary content addressable memory (Ternary Content Addressable Memory, TCAM), a register, a line card board, a die and other hardware modules.

The following describes some application scenarios of the caching method provided by the embodiment of the present application. It should be noted that, the application scenarios provided by the embodiments of the present application are only typical application scenarios, and the caching method provided by the embodiments of the present application is not represented only for these application scenarios.

Referring to fig. 3-b, the structure of a network device according to an embodiment of the present application is shown. In the embodiment shown in fig. 3-b, network device 350 includes a processor 351, a TCAM352, and a memory 353. Processor 351 is connected to TCAM352 and memory 353, respectively. The memory 353 may be used to store a master routing table, the TCAM352 may be used as a cache to store the cache routing table or to find corresponding routing information according to the destination IP address, and the processor 351 may be used to store the routing prefix and the routing information in the TCAM352 according to the destination IP address or to forward the message according to the routing information found by the TCAM 352.

Alternatively, when the network device has multiple processors, each processor may correspond to a respective TCAM, and the multiple processors may correspond to the same memory. In particular, referring to fig. 3-c, when the network device 350 further comprises a processor 354, the network device 350 may further comprise a TCAM355. The processor 351 is connected to the TCAM355 and the memory 353, respectively. The TCAM355 may act as a cache for storing routing tables used by the processor 354. Similarly, TCAM352 may be used to store routing tables used by processor 351. Thus, each processor has a relatively independent TCAM for storing its own required routing table without storing all of the routing tables. Therefore, the storage space is saved, and the speed of the processor for reading the routing table is improved because the content stored in the TCAM is less. It should be noted that in the embodiment shown in fig. 3-c, the speed of the processor 351 reading data from the TCAM352 may be no faster than the speed of the processor 351 reading data from the memory 353.

The TCAM352 may be operated in the following manner according to the embodiment shown in table 7, and will not be described herein.

Alternatively, the function played by the TCAM described above may be implemented by parallel comparison logic circuits and registers. In particular, referring to FIG. 3-d, the role of TCAM352 in the embodiment shown in FIG. 3-b may be implemented by parallel compare logic 356 and register 357. The processor 351 is connected to a parallel comparison logic circuit 356, and the parallel comparison logic circuit 356 is connected to a register 357. The register 357 is used for storing a routing table, and the parallel comparison logic circuit is used for determining routing information corresponding to the destination IP address.

Alternatively, in the embodiments illustrated in FIGS. 3-b, 3-c, and 3-d, processor 351 and/or processor 354 may be referred to as a processor core (core).

Referring to fig. 3-e, the structure of a network device according to an embodiment of the present application is shown. In the embodiment shown in fig. 3-e, network device 360 includes line card board 361, line card board 362, line card board 363, switch board 364, and switch board 365. The switch board 364 is connected to the line card 361, the line card 362, and the line card 363, respectively, and the switch board 365 is connected to the line card 361, the line card 362, and the line card 363, respectively.

In the embodiment shown in fig. 3-e, each line card may include a cache for storing a cache routing table that the line card needs to use. For example, the line card board 361 includes a buffer 361-1 for storing a buffer routing table that the line card board 361 needs to use, the line card board 362 includes a buffer 362-1 for storing a buffer routing table that the line card board 362 needs to use, and the line card board 363 includes a buffer 363-1 for storing a buffer routing table that the line card board 363 needs to use. The switching fabric may store a routing table containing all routing information, i.e. the aforementioned master routing table. The master routing table may be stored in switch board 364 and/or switch board 365 or split into two parts and stored in switch board 364 and switch board 365, respectively. Alternatively, the master routing table may be stored in a cache of the switching fabric.

Referring to fig. 3-f, the structure of a chip of a network device according to an embodiment of the present application is shown. In the embodiment shown in fig. 3-f, chip 370 includes die 371, die 372, die 373, and die 374. Wherein die 371 is connected to die 372 and die 374, respectively, and die 373 is connected to die 372 and die 374, respectively. Of course, in some other implementations, the dies in the chip may also be connected in other ways.

A cache may be included in any one die in the chip. For example, die 371 may include cache 371-1, die 372 may include cache 372-1, die 373 may include cache 373-1, and die 374 may include cache 374-1. Any one or more of buffers 371-1, 372-1, 373-1, and 374-1 may be used to store the buffer routing table, and any one or more buffers may be used to store the master routing table.

In an actual application scenario, a plurality of network devices may serve as a virtual router to forward a message. For example, referring to fig. 3-g, the structure of a virtual router according to an embodiment of the present application is shown. In the embodiment shown in fig. 3-g, virtual router 380 includes network device 381, network device 382, network device 383, network device 384, and network device 385. Wherein network device 383 is connected to network device 381, network device 382, network device 384, and network device 385, respectively. In virtual router 380, network device 385 may be used to store master routing tables, and network device 381, network device 382, network device 384, and network device 385 may each store the respective required cached routing tables. Optionally, network device 383 may store the master routing table in a cache of network device 383.

Referring to fig. 4, fig. 4 is a data interaction diagram of a caching method according to an embodiment of the present application. The caching method provided by the embodiment of the application comprises the following steps:

s401, the processor acquires a first message.

In the embodiment of the present application, the processor may be a processor in a network device. For example, the processor may be the processor 321 in the network device 320 in fig. 3-a, or may be a processing unit for processing data in the processor 321. The processor may receive the first message sent by the other device through the network interface, for example, when the processor is the processor 321 in fig. 3-a, the processor 321 may receive the first message sent by the network device 310. Of course, in some possible implementations, the processor may also receive the first message sent by the terminal device. Of course, the cache described below may be a cache in a network device, such as cache 322 in FIG. 3-a. The memory may be a memory in a network device. For example, memory 323 in fig. 3-a.

The IP address of the destination device of the first message is referred to as the destination IP address of the first message, indicating to which device the first message needs to be sent. Then, after receiving the first message, the processor may parse the first message, thereby determining a destination IP address of the first message.

And S402, the processor searches the route prefix matched with the destination IP address from the cache.

After determining the destination address of the first message, the processor may look up the route prefix matching the destination IP address from the cache, e.g., the processor may look up the route prefix matching the destination IP address from the cache routing table. When there are multiple route prefixes in the cache route table that match the destination IP address, the processor may determine the longest length route prefix as the route prefix that matches the destination IP address. In some possible implementations, the processor may also convert the cache routing table into a corresponding tree structure, such as a binary tree or a multi-way tree, and determine the routing prefix that matches the destination IP address through the tree structure.

If the processor can find the routing prefix matched with the destination IP address from the cache, the processor can acquire the routing information corresponding to the destination IP address from the cache, so that the first message is forwarded through the routing information. If the processor cannot find the routing prefix matched with the destination IP address from the cache, the routing prefix corresponding to the destination IP address is not stored in the cache routing table. The processor may look up the route prefix and route information from the memory that matches the destination IP address and update the cached routing table based on the found route prefix and route information.

Optionally, before updating the cache routing table, the processor may first determine whether a storage space for storing the routing prefix and the routing information exists in the cache routing table. If the storage space of the cache is full, the processor may not update the cache routing table or delete the routing prefix and the routing information stored in the cache, thereby storing the new routing prefix and the routing information using the new storage space.

The method of updating the cache routing table by the processor in the case that the route prefix matching the destination IP address is not included in the slave cache is described below.

And S403, responding to the cache not storing the routing prefix, and searching the prefix node and the routing information corresponding to the destination IP address from a memory by the processor.

If the route prefix corresponding to the destination IP address is not stored in the cache, the processor may look up the route prefix and the route information corresponding to the destination IP address from the memory. Alternatively, the processor may determine the routing prefix corresponding to the destination IP address through a tree structure corresponding to the routing table. Then, the processor may determine a prefix node corresponding to the destination IP address from a tree structure corresponding to the routing table, and obtain routing information of the prefix node.

The method by which the processor determines the prefix node is described below.

Assume that the routing table stored in the memory is as shown in Table 4

TABLE 5

Routing prefix	Routing information
		0*	Network interface X
11*	Network interface A
		0000*	Network interface B
0001010*	Network interface C
		00010111*	Network interface D
0001011111*	Network interface E
		00010110000*	Network interface F
00010110010*	Network interface G

A schematic diagram of the attribute structure corresponding to the routing table may be shown in fig. 5. Wherein the numbers within each node in fig. 5 represent the number of that node. Then, the node 2 is a prefix node corresponding to the routing prefix 0, the node 2 is a prefix node corresponding to the routing prefix 11, the node 7 is a prefix node corresponding to the routing prefix 0000, the node 11 is a prefix node corresponding to the routing prefix 0001010, the node 14 is a prefix node corresponding to the routing prefix 00010111, the node 19 is a prefix node corresponding to the routing prefix 0001011111, the node 20 is a prefix node corresponding to the routing prefix 00010110000, and the node 21 is a prefix node corresponding to the routing prefix 00010110010.

If the destination IP address of the first packet is 0001011010010001, the processor may determine that the prefix node corresponding to the destination IP address is node 2 and the corresponding routing information is network interface X, because the destination IP address is only matched with the routing prefix 0. If the destination IP address of the first packet is 0001010010100010, the processor may determine that the prefix node corresponding to the destination IP address is node 11 and the corresponding routing information is network interface C, because the destination IP is matched with the routing prefix 0x and the routing prefix 0001010 x and the length of the routing prefix 0001010 x is greater than the length of the routing prefix 0 x.

In an actual application scenario, the number of correspondence relations stored in the routing table is often large, and the corresponding tree structure is also complex. Then, in order to quickly find the prefix node corresponding to the destination IP address, the tree structure corresponding to the routing table may be split into a plurality of sub-tree structures, and the tree structure composed of the root nodes of these sub-tree structures is referred to as a virtual tree structure. The root node of each sub-tree structure corresponds to a virtual prefix. The routing prefixes represented by the nodes in the subtree structure may be determined based on the virtual prefixes and the locations of the nodes in the virtual tree structure. For example, assuming that the virtual prefix of a certain subtree structure is 1000, the routing prefix corresponding to the right child node of the root node of the subtree structure is 10001.

When searching the route prefix corresponding to the destination IP address, the processor can search the virtual prefix which is matched with the destination IP address longest from the virtual tree structure, and determine the virtual prefix with the longest length from the virtual prefixes which are matched with the destination IP address. The processor may then determine a prefix node from the subtree structure corresponding to the virtual prefix that matches the destination IP address. If the subtree corresponding to the virtual prefix does not have the prefix node matched with the destination IP address, the processor can determine the prefix node corresponding to the virtual prefix as the prefix node of the destination IP address.

For example. For the binary tree shown in fig. 5, it can be divided into three sub-tree structures. The root nodes of the three sub-tree structures are respectively root node 1, node 6 and node 12, and the virtual prefixes are respectively 00 and 0001011. Then, when the virtual tree structure is represented in the form of a table, the table may be as shown in table 6. Three subtrees may be as shown in fig. 6.

TABLE 6

Virtual prefix	Prefix length	Subtree information
			*	0	Subtree 0
00*	2	Subtree 1
			0001011*	7	Subtree 2

Where the first row of table 6 indicates that a virtual prefix with length 0 corresponds to subtree 0, i.e. the destination IP address does not match other virtual prefixes in table 6, the processor may determine the prefix node determined by the destination IP address from subtree 0. The second row of table 6 indicates that a virtual prefix 00 of length 2 corresponds to sub-tree 1. The third row of table 6 shows that a virtual prefix 0001011 of length 7 corresponds to subtree 2.

When the first message with the destination IP address 0001010010100010 is received, the processor can search the prefix node matching the destination IP address from the subtree 1 because the destination IP address matches the virtual prefix 00 x longest. Since the routing prefix of node 11 in subtree 1 is 0001010 x matched with the destination IP address and node 11 is a prefix node, the processor can determine the routing prefix 0001010 x as the routing prefix matched with the destination IP address 0001010010100010 and node 11 is the corresponding prefix node.

When the first message with the destination IP address 0001011010010001 is received, the processor can search the prefix node matching the destination IP address from the subtree 1 because the destination IP address matches the virtual prefix 00 x longest. Since subtree 1 does not have prefix nodes with matched destination IP addresses, the processor may determine the prefix node corresponding to virtual prefix 00 as the prefix node corresponding to the destination IP address. The processor may determine that the prefix node that matches the destination IP address 0001011010010001 is node 2 and the matching routing prefix is 0.

And S404, the processor determines a corresponding relation set according to the prefix node and the routing information.

After determining the prefix node and the routing information corresponding to the destination IP address, the processor may determine a set of correspondence relationships from the prefix node and the routing information. The corresponding relation set may include a corresponding relation between a routing prefix of the prefix node and the routing information, or may include a corresponding relation between the first routing prefix and the routing information. In the embodiment of the present application, the correspondence between the first routing prefix and the routing information may be referred to as a first correspondence. Specifically, when the prefix node matched with the destination IP address is a leaf node, the corresponding relation may include a corresponding relation between a routing prefix of the prefix node and routing information, and when the prefix node matched with the destination IP address is not a leaf node, the corresponding relation may include a first corresponding relation. The description of the first routing prefix may be found below.

These two cases are described separately below.

In a first possible implementation, the prefix node matching the destination IP address is a leaf node, that is, the tail node of the lookup path is a prefix node, and the processor may determine that the correspondence is between the routing prefix of the prefix node and the routing information.

Since a leaf node is a node without a child node, the prefix node also has no child node. That is, among one or more route prefixes described in the route table, there are no other route prefixes whose first n bits match the route prefix and whose length is greater than n. Where n is the length of the routing prefix.

Still referring to fig. 5, assuming that the destination IP address is 0001010010100010, the prefix node matching the destination IP address is node 11. Node 11 acts as a leaf node and has no child nodes. If node 11 has a left child node or a right child node, then the route prefix corresponding to the left child node of node 11 is 00010100 and the queue route prefix corresponding to the right child node of node 11 is 00010101. Since these two child nodes do not exist, it is stated that the routing table does not include two routing prefixes 00010100 and 00010101, and naturally does not include other routing prefixes whose first 7 bits are 0001010 and whose length is greater than 7.

It can be seen that since there are no other routing prefixes in the routing table where the first n bits are identical to the routing prefix of the prefix node and the length is greater than n (n is the length of the routing prefix). Naturally, a destination IP address matching a routing prefix of the prefix node cannot be matched with other routing prefixes of length greater than n. Therefore, after the route prefix of the prefix node is stored in the cache route table, false hit is not generated, that is, the condition that the destination IP address should be matched with a route prefix with a length greater than n is not generated, but the route prefix stored in the cache route table is not fully matched with the route prefix.

The processor may then retrieve the routing information corresponding to the routing prefix of the prefix node from the memory to store the correspondence between the routing prefix and the routing information in the cache in a subsequent step.

In a second possible implementation, the prefix node matching the destination IP address is not a leaf node, i.e. the tail node of the lookup path is not a prefix node, and the set of correspondence relationships may include the first correspondence relationship. The processor may first determine the first routing prefix when determining the first correspondence. The first routing prefix is matched with the destination IP address, and the length of the first routing prefix is determined according to the first prefix matching length, wherein the first prefix matching length is the length from the root node of the tree structure to the tail node of the searching path, namely the number of nodes between the tail node of the searching path and the root node is increased by 1.

In the embodiment of the present application, the length of the first routing prefix may be greater than the first prefix matching length, may be equal to the first prefix matching length, or may be less than the first prefix matching length. The following description will be made separately.

First, a case where the first routing prefix is greater than the first prefix matching length will be described.

In the tree structure corresponding to the routing table, since the prefix node corresponding to the destination IP address is not a leaf node, it is explained that other prefix nodes are included in the subtree of the prefix node, that is, other routing prefixes including the routing prefix corresponding to the destination IP address exist in the cache routing table, and the routing prefixes are not matched with the destination IP address. Thus, to avoid false hits, the processor may determine a routing prefix that is outside the tree structure to which the routing table corresponds and that matches the destination IP address as the first routing prefix.

Specifically, the processor may select a portion having a length greater than the first prefix matching length from the destination IP address as the first routing prefix. The first prefix matching length is the length of a tail node of a lookup path from a root node of the tree structure to a destination IP address, i.e., the length of a routing prefix corresponding to the tail node. Because the prefix node corresponding to the destination IP address is not a leaf node, the tail node in the search path is not a prefix node, and the difference between the tree structure corresponding to the destination IP address and the tree structure corresponding to the forwarding table from the position of the tail node is described. Therefore, the part with the length longer than the matching length of the first prefix is selected from the destination IP address as the first routing prefix, so that the tail node corresponding to the first routing prefix is ensured to be out of the tree structure corresponding to the forwarding table, namely, the first routing prefix is not overlapped with any routing prefix in the tree structure corresponding to the routing table. Thus, the first routing prefix is not described in the routing table, and it is naturally impossible to describe other routing prefixes having a length longer than the first routing prefix and including the first routing prefix. That is, assuming that the first routing prefix is n in length, there are no other routing prefixes in the routing table that have the first n bits consistent with the destination IP address and a length greater than n. Naturally, any IP address that includes the first routing prefix cannot be matched with a routing prefix of length greater than n in the destination routing table. Therefore, after the route prefix of the prefix node is stored in the cache route table, false hit is not generated, that is, the condition that the destination IP address should be matched with a route prefix with a length greater than n is not generated, but the route prefix stored in the cache route table is not fully matched with the route prefix.

Still, the description will be given by taking fig. 5 as an example. Assuming that the destination IP address is 0001011010010001, the routing prefix matched with the destination IP address is 0, and the search path of the destination IP address in the tree structure is "1-2-4-6-8-9-10-12-13". The tail node is node 13, and the first prefix matching length is 8. The destination IP address is represented by a tree structure in a portion other than the routing table, and the resulting tree structure can be shown in fig. 7. On the basis of the embodiment shown in fig. 5, the tree structure shown in fig. 7 is newly added with nodes 22, 23, 24, 25, 26, 27, 28 and 29. These nodes correspond to bits 9-16 of the destination IP address, respectively. Since these nodes do not exist in the corresponding tree structure of the routing table, these nodes may also be referred to as virtual nodes.

Because the virtual node is located at a part of the tree structure corresponding to the destination IP address, which is outside the tree structure of the routing table, the routing prefix corresponding to the virtual node is greater than the first prefix matching length. Therefore, when determining the first routing prefix, the processor may determine the routing prefix corresponding to any one virtual node as the first routing prefix. For example, the processor may determine a routing prefix corresponding to a virtual node directly connected to the end node as the first routing prefix. In the embodiment shown in fig. 6, the processor may determine a routing prefix 000101101 corresponding to node 22 as the first routing prefix, where the length of the first routing prefix is one more than the first prefix matching length. Of course, in some possible implementations, the processor may also determine the route prefix corresponding to any other virtual node as the first route prefix. For example, the routing prefix 00010110100 corresponding to the node 24 may be determined as the first routing prefix.

As can be seen from the foregoing description, when determining the prefix node matching the destination IP address, the processor may determine, according to the virtual tree structure, the virtual prefix and the sub-tree structure corresponding to the destination IP address, and then determine, according to the sub-tree structure, the prefix node matching the destination IP address. Similarly, the processor may also determine the first routing prefix through the virtual tree structure.

Specifically, it is assumed that the first length is a length from a root node of the virtual tree structure to a virtual prefix corresponding to the destination IP address, that is, a length of the virtual prefix matching the destination IP address, and the second length is a length from the virtual prefix to a tail node of the lookup path, that is, a length from the root node to the tail node in the subtree structure corresponding to the destination IP address. Because the searching path of the destination IP address is from the root node of the virtual tree structure to the root node of the subtree structure corresponding to the virtual prefix, and from the root node of the subtree structure to the tail node, the sum of the first length and the second length is the first prefix matching length. When determining the first routing prefix, the processor may determine the virtual prefix as a first half of the first routing prefix, and then select a portion of the destination IP address having a length greater than the second length to determine as a second half of the first routing prefix.

Taking the embodiment shown in fig. 6 as an example, assuming that the destination IP address is 0001011010010001, the virtual prefix matching the destination IP address is the virtual prefix corresponding to the node 12, that is, 0001011. The processor may determine the first 7 bits of the first routing prefix as 0001011. Since the tail node of the destination IP address in the subtree 2 is node 13, the length from node 12 to node 13 is 1, i.e. the second length is 1, and the processor may intercept a portion with a length greater than 1 from the 8 th bit of the destination IP address as the second half of the first routing prefix. For example, the processor may use the 8 th and 9 th bits of the destination IP address as the second half of the first routing prefix, where the first routing prefix is 000101101 x.

The following describes a case where the length of the first routing prefix is equal to the first prefix matching length.

In an actual application scenario, the leaf nodes in the tree structure may not be prefix nodes, since the modification of the routing table and the modification of the tree structure may not be synchronized. Then, when the prefix node corresponding to the destination IP address is not a leaf node and the tail node of the lookup path of the destination IP address in the tree structure is a leaf node, the processor may determine the routing prefix corresponding to the leaf node as the first routing prefix. In this way, the length of the first routing prefix may also be equal to the first prefix matching length.

Specifically, after a certain routing prefix in the routing table is deleted, a node (hereinafter referred to as node a) corresponding to the routing prefix in the tree structure may not be deleted yet. But node a is not a prefix node since the routing table has been modified. If node A does not have child nodes, then node A is a leaf node in the tree structure that is not a prefix node.

For example, in the embodiment shown in fig. 5, it is assumed that the routing prefix 0000 is deleted from the routing table, but node 7 may still remain in the tree structure. Then the node 7 is a leaf node of the non-prefix node.

After the first message is received, if the destination IP address of the first message is 0000101010101010, the routing prefix matched with the destination IP address is 0, the corresponding prefix node is node 2, the tail node of the search path is node 7, the routing prefix of node 7 is 0000, and the matching length of the first prefix is 4. Then the processor may determine the routing prefix 0000 of node 7 as the first routing prefix. It can be seen that in this case the length of the first routing prefix coincides with the first prefix matching length.

The following describes the case where the length of the first routing prefix is smaller than the first prefix matching length.

In some possible implementations, the length of the first routing prefix may also be smaller than the first prefix matching length and larger than the length of the routing prefix corresponding to the prefix node, i.e. the length of the routing prefix matching the destination IP address in the memory routing table. That is, the corresponding node of the first routing prefix in the tree structure is the node of the lower layer of the prefix node and the upper layer of the tail node in the search path. In this way, although the length of the first routing prefix is smaller than the matching length of the first prefix, since the length of the first routing prefix is still greater than the length of the routing prefix matched with the destination IP address in the memory routing table, compared with the prior art, storing the correspondence between the first routing prefix and the routing information in the cache can still play a role in reducing the probability of false hit occurrence. It is readily understood that the longer the length of the first routing prefix, the less probability of false hits occurring. When the length of the first routing prefix is greater than the first prefix matching length, the probability of false hits is 0.

For example. Assuming that the destination IP address is 0001011010010001, the prefix node matching the destination IP address is node 2, the length of the corresponding routing prefix is 1, the tail node is node 12, and the corresponding first prefix matching length is 8. Then, the processor may prefix the first route from the first m bits of the destination IP address, where m is a positive integer greater than 1 and less than 8. For example, the processor may determine route prefix 00010110 as the first route prefix.

The method for determining the first routing prefix by the processor is described above, after determining the first routing prefix, the processor may search the routing information from the routing table stored in the memory according to the routing prefix matched with the destination IP address, and further determine the correspondence between the routing information and the first routing prefix as the first correspondence.

Optionally, when the processor determines, through the virtual tree structure, a prefix node that matches the destination IP address, a third correspondence may be included in the set of correspondences. The third correspondence may include a virtual prefix, a type of the virtual prefix, and information of a subtree structure. The virtual prefix is a virtual prefix matched with the destination IP address, and the information of the subtree structure is used for indicating which subtree the destination IP address corresponds to. The type of the virtual prefix is used for indicating that when the virtual prefix is hit, the corresponding subtree structure is searched according to the information of the subtree structure.

That is, after receiving the new packet, if the destination IP address of the packet matches the virtual prefix stored in the cache, the processor may search the subtree structure corresponding to the virtual prefix according to the type of the virtual prefix, thereby determining the subtree structure corresponding to the virtual prefix according to the third correspondence, and further determining the routing prefix matching the destination IP address according to the subtree structure.

In order to improve the searching efficiency, in some possible implementations, the corresponding relation set may further include a second corresponding relation. The second correspondence is a correspondence between the second routing prefix and the routing information. The routing information is the routing information of the routing prefix corresponding to the destination IP address of the first message.

The method by which the processor determines the second routing prefix is described below.

After determining that the prefix node corresponding to the destination IP address is not a leaf node, the processor may determine, according to the tree structure, all the unique child nodes after the prefix node in the lookup path, that is, the node having only the left child node or the right child node. The processor may then determine a length of the routing prefix corresponding to the unique child node as a second prefix matching length. I.e. the second prefix matching length is equal to the length between the root node of the tree structure and the unique child node. The processor may then determine a second routing prefix based on the second prefix matching length and the destination IP address. Assuming that the second prefix match length is n, the processor may determine the first n of the destination IP address as the second routing prefix.

Because the unique node is the node after the prefix node in the searching path of the destination IP address, the routing prefix corresponding to any unique node is not in the cache routing table, and the prefix nodes corresponding to the messages matched with the unique nodes are all prefix nodes of the destination IP address. Thus, the routing prefixes of the IP addresses that match the individual nodes are all the routing prefixes of the prefix nodes. And because the individual nodes are located on the searching path of the destination IP address, the destination IP address comprises the routing prefix of each individual node. Therefore, the second prefix matching length is determined according to the unique node, and then the second routing prefix is selected from the destination IP address according to the second prefix matching length, so that the obtained second routing prefix is matched with the routing information corresponding to the prefix node of the destination IP address. Therefore, the processor may record the correspondence between the second routing prefix and the routing information as a second correspondence, and add the set of correspondences to be cached.

The embodiment shown in fig. 5 is still taken as an example. After receiving the first message with destination IP address 0001011010010001, the processor may determine that the prefix node is node 2. The tail node is node 13, and the unique sub-nodes between the prefix node and the tail node comprise node 4, node 8 and node 9. The second prefix matching length corresponding to the node 4 is 2, the second prefix matching length of the node 8 is 4, and the second prefix matching length of the node 9 is 5. Then, the processor may determine the first 2 bits, the first 4 bits, and the first 5 bits of the destination IP address as the second routing prefix, i.e., routing prefix 00, and routing prefix 0001 and routing prefix 00010 are both second routing prefixes. The processor may then determine a correspondence between the three routing prefixes and the routing information "network interface X" corresponding to the routing prefix 0 as a second correspondence.

And S405, triggering the cache to store the corresponding relation set by the processor.

After obtaining the corresponding relation set, the processor may trigger the cache to store the corresponding relation set. Optionally, the processor may also trigger the cache to store the length of the first routing prefix, taking into account the longest prefix matching principle.

In addition, when the first correspondence is included in the correspondence set, the processor may further trigger the cache to store a type of the first routing prefix. The type of the first routing prefix is used for indicating the processor to acquire the routing information corresponding to the first routing prefix in the cache according to the first corresponding relation when the first routing prefix is hit. That is, after receiving the new packet, if the destination IP address of the packet matches the first routing prefix stored in the cache, the processor may search the routing information corresponding to the first routing prefix from the cache routing table according to the type of the first routing prefix, without searching the routing information corresponding to the first routing prefix from the memory.

The process of searching the corresponding routing information for the TCAM destination IP address is described below.

It is assumed that the TCAM serving as the cache routing table stores a correspondence between the routing prefix 000101101 and the network interface X, and a correspondence between the routing prefix 0001011 and the routing prefix 0000 and the network interface B. The entries stored in the TCAM may be as shown in table 7.

TABLE 7

TCAM key	TCAM mask	TCAM AD
			000101101*	1111111110000000	Network interface X
0000*	1111000000000000	Network interface B

The first entry in the header in table 7 is a TCAM mask (TCAM key) for recording the routing prefix to be matched. The first entry in the header in table 7 is a TCAM mask (TCAM mask) for detecting the matching degree of the destination IP address and the TCAM keyword. The first entry of the header in table 7 is TCAM Associated Data (AD) for recording routing information corresponding to TCAM keywords.

The first row in table 7 indicates that the TCAM may determine, through the TCAM mask 1111111110000000, whether the destination IP address of the packet matches the TCAM keyword 000101101, and send the packet through the network interface X after determining that the destination IP address TCAM keyword 000101101 matches. The second row in table 7 indicates that the TCAM may determine whether the destination IP address of the packet matches TCAM keyword 0000 through TCAM mask 1111000000000000, and send the packet through network interface B after determining that the destination IP address TCAM keyword 0000 matches.

When judging whether the target IP address of the message is matched with the TCAM keyword, the TCAM can carry out the AND operation on the TCAM mask and the target IP address bit by bit, and also carries out the AND operation on the TCAM keyword and the TCAM mask bit by bit. And finally, comparing whether the results obtained by the two operations are completely consistent bit by bit. If the results obtained by the two operations are completely consistent, the TCAM can determine that the target IP address is matched with the TCAM keyword, so that the message is sent according to the routing information recorded in the TCAM associated data.

For example. Assuming that the network device receives the packet with the destination IP address 0001011010010001, the processor may bitwise and the destination IP address 0001011010010001 with the TCAM key 1111111110000000 and the TCAM mask 1111000000000000, respectively.

When performing bitwise AND operation, if the values of the destination IP address and the TCAM mask on a certain bit are both 1, the result is 1, and if not, the result is 0. For example, the first bit of the destination IP address is 0, the first bit of tcam mask 1111111110000000 is 1, and the result of the and operation is 0. The fourth bit of the destination IP address is 1, the fourth bit of tcam mask 1111111110000000 is 1, and the result of the and operation is 1.

And so on, the result of the bitwise and operation of destination IP address 0001011010010001 with TCAM mask 1111111110000000 is 0001011010000000. The result of the bitwise AND operation of destination IP address 0001011010010001 with TCAM mask 1111000000000000 is 0001000000000000. Similarly, bitwise and operation of TCAM key 000101101 with TCAM mask 1111111110000000 yields 0001011010000000. The result of the bitwise and operation of TCAM key 0000 with TCAM mask 1111111110000000 is 000000000000.

Then, since the result obtained by the operation of the destination IP address is completely consistent with the result obtained by the operation of TCAM keyword 000101101, TCAM can determine that the destination IP address matches with routing prefix 000101101, so as to send the packet through network interface X. Since the result obtained by the operation according to the destination IP address is inconsistent with the result obtained by the operation according to TCAM keyword 0000, TCAM can determine that the destination IP address is not matched with route prefix 0000, so that the message is not sent through network interface B.

Referring to fig. 8, an embodiment of the present application further provides an integrated circuit 800, where the integrated circuit 800 may implement the functions of the processor in the embodiment shown in fig. 4. The integrated circuit includes an interface circuit 801 and a control circuit 802. The control circuit 802 is connected to the interface circuit 801 via a communication line 803. Interface circuit 801 is used to enable integrated circuit 800 to connect to other devices via a communication link. The interface circuit 801 is used to implement S401, S402, S403, and S405 in the embodiment shown in fig. 4, and the control circuit 802 is used to implement S402, S403, S404, and S405 in the embodiment shown in fig. 4.

Specifically, the interface circuit 801 is configured to obtain a first packet, where the first packet includes a destination IP address.

The control circuit 802 is configured to search a route prefix matching the destination IP address from a cache, search a tree structure corresponding to a routing table according to the destination IP address in response to the route prefix not being stored in the cache, determine a prefix node matching the destination IP address, determine a first prefix matching length in response to the prefix node not being a leaf node, the first prefix matching length being equal to a length between a root node and a tail node of the tree structure, the tail node being a last node on a search path of the tree structure, determine a first route prefix according to the first prefix matching length and the destination IP address, and trigger the cache to store a first correspondence, the first correspondence being the first route prefix and route information corresponding to the prefix node.

Reference is made to the detailed description of the corresponding steps in the embodiment shown in fig. 4, and details are not repeated here.

Optionally, the integrated circuit 800 provided in an embodiment of the present application may further include a cache. The interface circuit 801 and the control circuit 802 in the integrated circuit 800 may be one or more.

The integrated circuit 600 may be, for example, an FPGA, an ASIC, a system on chip (SoC), a CPU, an NP, a digital signal processing circuit (DIGITAL SIGNAL processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.

Referring to fig. 9, the embodiment of the present application further provides an apparatus 900, where the buffering apparatus 900 may implement the functions of the processor in the embodiment shown in fig. 4. The buffering device 900 includes an acquisition unit 901 and a processing unit 902. The acquiring unit 901 is configured to implement S401 in the embodiment shown in fig. 4, and the processing unit 402 is configured to implement S402, S403, S404, and S405 in the embodiment shown in fig. 4.

Specifically, the obtaining unit 901 is configured to obtain a first packet, where the first packet includes a destination IP address.

The processing unit 902 is configured to search a routing prefix matched with the destination IP address from a cache, search a tree structure corresponding to a routing table according to the destination IP address in response to the routing prefix not being stored in the cache, determine a prefix node matched with the destination IP address, determine a first prefix matching length in response to the prefix node not being a leaf node, the first prefix matching length being equal to a length between a root node and a tail node of the tree structure, the tail node being a last node on a search path of the tree structure, determine a first routing prefix according to the first prefix matching length and the destination IP address, and trigger the cache to store a first correspondence, the first correspondence being the first routing prefix and routing information corresponding to the prefix node.

It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. The functional units in the embodiment of the application can be integrated in one processing unit, or each unit can exist alone physically, or two or more units are integrated in one unit. For example, in the above embodiment, the acquisition unit and the processing unit may be the same unit or different units. The integrated units may be implemented in hardware or in software functional units.

Referring to fig. 10, the embodiment of the present application further provides a chip 1000, where the chip 1000 may implement the functions of the processor in the embodiment shown in fig. 4. The chip includes a memory 1001 and a processor 1002. The memory 1001 is used for storing instructions or program codes, and the processor 1002 is used for calling and executing the instructions or program codes from the memory 1001 to implement S401, S402, S403, S404, and S405 in the embodiment shown in fig. 4.

Alternatively, the processor 1002 may be the integrated circuit 800 of FIG. 8. The processor 1002 may include a cache. When the processor 1002 does not include a cache, the memory 1001 may include a cache.

Fig. 11 is a schematic structural diagram of an apparatus 1100 according to an embodiment of the present application. The above device where the processor is located may be implemented by a device located as shown in fig. 11. Referring to FIG. 11, the device 1100 includes at least one processor chip 1101 and at least one memory 1102. Optionally, the device 1100 may also include a communication bus 1103 and at least one network interface 1104.

The processor chip 1101 may be a general purpose central processing unit (centralprocessing unit, CPU), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits (INTEGRATED CIRCUIT, IC) for controlling the execution of the programs of the present application. The processor chip 1101 may be used to implement the data caching method provided in an embodiment of the present application.

For example, when the network device in fig. 1 is implemented by using the device shown in fig. 11, the processor may be configured to obtain a first packet, where the first packet includes a destination IP address, search a cache for a routing prefix that matches the destination IP address, search a tree structure corresponding to a routing table according to the destination IP address in response to the routing prefix not being stored in the cache, determine a prefix node that matches the destination IP address, determine a first prefix matching length in response to the prefix node not being a leaf node, where the first prefix matching length is equal to a length between a root node and a tail node of the tree structure, where the tail node is a last node on a search path of the tree structure, determine a first routing prefix according to the first prefix matching length and the destination IP address, and trigger the cache to store a first correspondence, where the first correspondence is the first routing prefix and routing information corresponding to the prefix node.

Alternatively, processor chip 1101 may be chip 1000 in the embodiment shown in FIG. 10 or integrated circuit 800 in the embodiment shown in FIG. 8. When the processor chip 1101 does not include a cache, the memory 1102 may include a cache, a memory, and an external memory, and when the processor chip 1101 includes a cache, the memory 1102 may include a memory and an external memory.

Memory 1102 may be a read-only Memory (ROM) or other type of static storage device that can store static information and instructions, memory 1102 may also be a random access Memory (random access Memory, RAM) or other type of dynamic storage device that can store information and instructions, and may also be a read-only optical disc (compact disc read-only Memory, CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation. The memory 1102 may be separate and coupled to the processor 1101 by a communication bus 1103. The memory 1102 may also be integral with the processor 1101. Optionally, the memory 1102 may include a cache.

Optionally, the memory 1102 is used for storing program code or instructions for performing the aspects of the present application and is controlled for execution by the processor 1101. The processor 1101 is configured to execute program code or instructions stored in the memory 1102. One or more software modules may be included in the program code. Alternatively, the processor 1101 may store program code or instructions for performing the inventive arrangements, in which case the processor 1101 does not need to read the program code or instructions into the memory 1102.

Alternatively, the memory 1102 may be used to implement the role of the memory 120 in the device shown in FIG. 1.

Communication bus 1103 is used to transfer information between processor chip 1101, network interface 1104, and memory 1102.

The network interface 1104 may be a device, such as a transceiver, for communicating with other devices or communication networks, which may be an ethernet, a Radio Access Network (RAN), or a wireless local area network (wireless local area networks, WLAN), etc. In the embodiment of the present application, the network interface 904 may be configured to receive a packet sent by another node in the segment routing network, and may also send a packet to another node in the segment routing network. The network interface 1104 may be an ethernet interface, a fast ethernet (FAST ETHERNET, FE) interface, a gigabit ethernet (gigabit ethernet, GE) interface, or the like.

In a particular implementation, device 1100 may include multiple processor chips, such as processor chip 1101 and processor chip 1105 shown in FIG. 9, as one embodiment. Each of these processor chips may be a single-core (single-CPU) processor or may be a multi-core (multi-CPU) processor. Alternatively, different steps in the caching method shown in fig. 4 may be performed by different processor chips. A processor chip herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

Fig. 12 is a schematic structural diagram of an apparatus 1200 according to an embodiment of the present application. The device 100 of fig. 1 may be implemented by the device shown in fig. 12. Referring to the schematic device architecture shown in fig. 12, a device 1200 includes a master control board and one or more interface boards. The main control board is in communication connection with the interface board. The main control board is also called a main processing unit (main processing unit, MPU) or a routing processing card (route processor card), and includes a CPU and a memory, and is responsible for controlling and managing various components in the device 1200, including routing computation, device management, and maintenance functions. The interface board is also called a line processing unit (line processing unit, LPU) or line card (line card) for receiving and transmitting messages. In some embodiments, communication is via a bus between the master control board and the interface board or between the interface board and the interface board. In some embodiments, the interface boards communicate via a switch fabric, in which case the device 1200 also includes a switch fabric communicatively coupled to the master board and the interface boards, the switch fabric configured to forward data between the interface boards, which may also be referred to as a switch fabric unit (switch fabric unit, SFU). The interface board includes a CPU, memory, forwarding engine, and interface cards (INTERFACE CARD, IC), where the interface cards may include one or more network interfaces. The network interface may be an Ethernet interface, an FE interface, a GE interface, or the like. The CPU is in communication connection with the memory, the forwarding engine and the interface card respectively. The memory is used for storing a forwarding table. The forwarding engine is used for forwarding the received message based on the forwarding table stored in the memory, if the destination address of the received message is the IP address of the device 1200, the message is sent to the CPU of the main control board or the interface board for processing, if the destination address of the received message is not the IP address of the device 1200, the forwarding table is searched according to the destination, and if the next hop and the outgoing interface corresponding to the destination address are searched from the forwarding table, the message is forwarded to the outgoing interface corresponding to the destination address. The forwarding engine may be a network processor (network processor, NP). The interface card is also called a sub-card, can be installed on the interface board, and is responsible for converting the photoelectric signal into a data frame, and forwarding the data frame to a forwarding engine for processing or an interface board CPU after performing validity check. In some embodiments, the CPU may also perform the functions of a forwarding engine, such as soft forwarding based on a general purpose CPU, so that no forwarding engine is needed in the interface board. In some embodiments, the forwarding engine may be implemented by an ASIC or field programmable gate array (field programmable GATE ARRAY, FPGA). In some embodiments, the memory storing the forwarding table may also be integrated into the forwarding engine as part of the forwarding engine.

Alternatively, the processor in the system-on-chip may be one or more. The processor may be implemented in hardware or in software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implemented in software, the processor may be a general purpose processor, implemented by reading software code stored in a memory. Alternatively, the memory in the system-on-chip may be one or more. The memory may be integral with the processor or separate from the processor, and the application is not limited. The memory may be a non-transitory processor, such as a ROM, which may be integrated on the same chip as the processor, or may be separately provided on different chips, and the type of memory and the manner of providing the memory and the processor are not particularly limited in the present application.

The system-on-chip may be, for example, an FPGA, an ASIC, a system-on-chip (SoC), a CPU, an NP, a digital signal processing circuit (digital signalprocessor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.

It should be understood that the steps in the above-described method embodiments may be accomplished by integrated logic circuitry in hardware in a processor or instructions in the form of software. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution.

Embodiments of the present application also provide a computer-readable storage medium comprising instructions that, when run on a computer, cause the computer to perform the caching method provided by the method embodiment above, performed by a processor.

Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the caching method provided by the method embodiment above, performed by a processor.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and the division of the units, for example, is merely a logic module division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be acquired according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each module unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units described above may be implemented either in hardware or in software module units.

The integrated units, if implemented in the form of software module units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The above embodiments are further described in detail for the purpose, technical solution and advantageous effects of the present invention, and it should be understood that the above description is only an embodiment of the present invention.

While the application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the foregoing embodiments may be modified or equivalents may be substituted for some of the features thereof, and that the modifications or substitutions do not depart from the spirit of the embodiments.

Claims

1. A caching method, characterized in that the method comprises:

The processor obtains a first message, where the first message includes a destination Internet Protocol (IP) address;

The processor searches a cache for a routing prefix that matches the destination IP address;

In response to the routing prefix not being stored in the cache, the processor searches a tree structure corresponding to a routing table according to the destination IP address to determine a prefix node that matches the destination IP address;

In response to the prefix node not being a leaf node, the processor determines a first prefix matching length, where the first prefix matching length is equal to a length from a root node to a tail node of the tree structure, where the tail node is a last node on a search path of the tree structure;

The processor determines a first routing prefix based on the first prefix matching length and the destination IP address;

The processor triggers the cache to store a first corresponding relationship, where the first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

2 . The method according to claim 1 , wherein the length of the first routing prefix is greater than or equal to the first prefix matching length.

3. The method according to claim 1 or 2, wherein the processor searches a tree structure corresponding to a routing table according to the destination IP address, and determining a prefix node matching the destination IP address comprises:

The processor searches the virtual tree structure corresponding to the routing table according to the destination IP address and determines the virtual prefix that has the longest match with the destination IP address;

The processor searches for a subtree structure corresponding to the virtual prefix according to the destination IP address, and determines a prefix node matching the destination IP address, where the virtual prefix is a root node of the subtree structure;

The first prefix matching length is equal to the sum of a first length and a second length, where the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node, where the tail node is the last node on the search path of the subtree structure.

4. The method according to claim 1 or 2, further comprising:

In response to the prefix node not being a leaf node, the processor determines a second prefix matching length, where the second prefix matching length is equal to a length between a root node and a single child node of the tree structure, where the single child node is a node between the prefix node and the tail node that has only a left child node or only a right child node;

The processor determines a second routing prefix according to the second prefix matching length and the destination IP address, where the length of the second routing prefix is greater than the second prefix matching length;

The processor triggers the cache to store a second corresponding relationship, where the second corresponding relationship is routing information corresponding to the second routing prefix and the prefix node.

5. The method according to any one of claims 1 to 2, further comprising:

The processor triggers the cache to store a type of the first routing prefix, where the type of the first routing prefix is used to indicate that when the first routing prefix is hit, routing information corresponding to the first routing prefix is obtained from the cache according to the first corresponding relationship.

6. The method according to claim 3, further comprising:

The processor triggers the cache to store a third correspondence, where the third correspondence is a correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the type of the virtual prefix is used to indicate that when the virtual prefix is hit, the subtree structure is searched according to the information of the subtree structure.

7. The method according to any one of claims 1-2, characterized in that the method further comprises:

The processor triggers the cache to store the length of the first routing prefix.

8. The method according to claim 2, wherein the length of the first routing prefix is equal to the first prefix matching length plus 1.

9. The method according to any one of claims 1-2, characterized in that the length of the first routing prefix is smaller than the length of the destination IP address.

10. The method according to any one of claims 1-2, characterized in that the destination IP address includes the first routing prefix.

11. The method according to any one of claims 1-2, wherein the cache comprises at least one of the following:

TCAM, registers, line cards, and dies.

12. An integrated circuit, characterized in that the integrated circuit comprises an interface circuit and a control circuit;

The interface circuit is configured to obtain a first message, wherein the first message includes a destination Internet Protocol (IP) address;

The control circuit is configured to search a cache for a routing prefix that matches the destination IP address; in response to the routing prefix not being stored in the cache, search a tree structure corresponding to a routing table according to the destination IP address, and determine a prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, where the first prefix matching length is equal to the length from a root node to a tail node of the tree structure, where the tail node is the last node on a search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; and trigger the cache to store a first corresponding relationship, where the first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

13 . The integrated circuit according to claim 12 , wherein a length of the first routing prefix is greater than or equal to the first prefix matching length.

14. The integrated circuit according to claim 12 or 13, characterized in that

The control circuit is configured to search a virtual tree structure corresponding to a routing table according to the destination IP address, and determine a virtual prefix that matches the destination IP address for the longest time; search a subtree structure corresponding to the virtual prefix according to the destination IP address, and determine a prefix node that matches the destination IP address, where the virtual prefix is the root node of the subtree structure; the first prefix matching length is equal to the sum of a first length and a second length, where the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to a tail node, where the tail node is the last node on the search path of the subtree structure.

15. The integrated circuit according to claim 12 or 13, characterized in that

The control circuit is further configured to, in response to the prefix node not being a leaf node, determine a second prefix matching length, where the second prefix matching length is equal to the length between the root node and the only child node of the tree structure, where the only child node is a node between the prefix node and the tail node that has only a left child node or only a right child node; determine a second routing prefix based on the second prefix matching length and the destination IP address, where the length of the second routing prefix is greater than the second prefix matching length; and trigger the cache to store a second corresponding relationship, where the second corresponding relationship is routing information corresponding to the second routing prefix and the prefix node.

16. The integrated circuit according to any one of claims 12 to 13, characterized in that:

The control circuit is further used to trigger the cache to store the type of the first routing prefix, where the type of the first routing prefix is used to indicate that when the first routing prefix is hit, routing information corresponding to the first routing prefix is obtained in the cache according to the first corresponding relationship.

17. The integrated circuit according to claim 14, wherein:

The control circuit is also used to trigger the cache to store a third correspondence, where the third correspondence is a correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the type of the virtual prefix is used to indicate that when the virtual prefix is hit, the subtree structure is searched according to the information of the subtree structure.

18. The integrated circuit according to any one of claims 12 to 13, characterized in that:

The control circuit is further configured to trigger the cache to store the length of the first routing prefix.

19. The integrated circuit of claim 13, wherein a length of the first routing prefix is equal to the first prefix matching length plus 1.

20 . The integrated circuit according to claim 12 , wherein the length of the first routing prefix is smaller than the length of the destination IP address.

21. The integrated circuit according to any one of claims 12-13, wherein the destination IP address includes the first routing prefix.

22. The integrated circuit according to any one of claims 12 to 13, wherein the cache comprises at least one of the following:

TCAM, registers, line cards, and dies.

23. A chip, characterized in that the chip comprises a memory and a processor, the memory being used to store instructions or program codes, and the processor being used to call and run the instructions or program codes from the memory to execute the caching method according to any one of claims 1 to 11.

24. A device, characterized in that the device comprises a processor chip and a memory, the memory being used to store instructions or program codes, and the processor chip being used to call and run the instructions or program codes from the memory to execute the caching method according to any one of claims 1 to 11.

25. A computer-readable storage medium, comprising instructions, programs or codes, which, when executed on a computer, enable the computer to execute the caching method according to any one of claims 1 to 11.