CN115188664A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115188664A CN115188664A CN202210601785.2A CN202210601785A CN115188664A CN 115188664 A CN115188664 A CN 115188664A CN 202210601785 A CN202210601785 A CN 202210601785A CN 115188664 A CN115188664 A CN 115188664A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 238000005468 ion implantation Methods 0.000 claims abstract description 80
- 238000002513 implantation Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 52
- 238000000137 annealing Methods 0.000 claims abstract description 19
- -1 germanium ions Chemical class 0.000 claims description 38
- 238000002955 isolation Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 14
- 229910052785 arsenic Inorganic materials 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910001449 indium ion Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 229910021478 group 5 element Inorganic materials 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 36
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 21
- 230000000694 effects Effects 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 239000007943 implant Substances 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
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- 238000005530 etching Methods 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
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- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
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- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000005240 physical vapour deposition Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Abstract
The present disclosure provides a semiconductor structure and a method for fabricating the same, the method for fabricating the semiconductor structure including: providing a semiconductor substrate; carrying out continuous ion implantation on the semiconductor substrate, and carrying out implantation according to the sequence of the atomic mass of the implanted ions from large to small; and performing annealing treatment. According to the preparation method of the semiconductor structure, the crystal lattice damage can be reduced, and the leakage current can be reduced.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
With the development of the semiconductor industry, the feature size and depth of the semiconductor structure are shrinking continuously, the Device performance is complicated, the Device is more sensitive to the leakage current, and the reduction of the lattice damage of the substrate material plays a very important role in the leakage current of the Device, especially when the ion implantation is performed in the preparation process of the semiconductor structure, the impact force of the implanted ions on atoms in the substrate material is different, so that the damage of the ion implantation on the lattice and the difference of the implantation depth and diffusion are caused, and the leakage current defect of the semiconductor structure is easily caused.
Disclosure of Invention
The present disclosure provides a method for manufacturing a semiconductor structure, which can reduce lattice damage and leakage current.
The preparation method of the semiconductor structure according to the embodiment of the disclosure comprises the following steps: providing a semiconductor substrate; carrying out continuous ion implantation on the semiconductor substrate, and carrying out implantation according to the sequence of the atomic mass of the implanted ions from large to small; and performing annealing treatment.
According to some embodiments of the disclosure, the implanted ions include at least two ions of a third and fifth main group element.
According to some embodiments of the present disclosure, the implant ions are at least two of germanium ions, arsenic ions, boron ions, indium ions, and phosphorus ions.
According to some embodiments of the disclosure, the implanted ions comprise ions of a first type and ions of a second type, the ions of the first type having an atomic mass greater than the ions of the second type, and in the step of performing successive ion implantations of the semiconductor substrate: performing ion implantation of the first type of ions at a first dose and a first energy; ion implantation of the second type of ions is performed at a second dose and at a second energy.
According to some embodiments of the disclosure, the first dose and the first energy satisfy: the first dose is 1.01E12-1.11E16atom/cm 2 Or the first energy is 1.8KeV to 198KeV.
According to some embodiments of the disclosure, the first dose is 1.01e12 to 1.11e16atom/cm 2 The first energy is 2 KeV-200 KeV.
According to some embodiments of the disclosure, the first dose is 1E12 to 1E16atom/cm 2 The first energy is 1.8KeV to 198KeV.
According to some embodiments of the disclosure, the first species of ions comprises arsenic ions and the second species of ions comprises boron ions.
According to some embodiments of the disclosure, the first type of ions comprises phosphorous ions and the second type of ions comprises boron ions.
According to some embodiments of the present disclosure, the step of performing continuous ion implantation on the semiconductor substrate comprises: and carrying out continuous ion implantation into the semiconductor substrate to form a well region.
According to some embodiments of the present disclosure, the step of performing the continuous ion implantation on the semiconductor substrate further comprises: and carrying out continuous ion implantation in the semiconductor substrate to form a source drain region.
According to some embodiments of the present disclosure, before the continuously implanting the semiconductor substrate, further comprising: and forming an oxide layer on the surface of the semiconductor substrate.
According to some embodiments of the present disclosure, the method of fabricating a semiconductor structure further comprises: forming an isolation structure through the oxide layer and at least partially within the semiconductor substrate; forming a photoresist layer on the surface of the isolation structure; and carrying out continuous ion implantation on the semiconductor substrate by taking the photoresist layer as a mask.
According to some embodiments of the present disclosure, before performing the annealing process, further comprising the steps of: and removing the photoresist layer.
The present disclosure also provides a semiconductor structure formed by the method for manufacturing the semiconductor structure of the above embodiment.
Therefore, according to the semiconductor structure and the preparation method thereof disclosed by the embodiment of the disclosure, ion implantation is performed according to the order of atomic mass from large to small, the implantation stop mechanism of the implanted ions with large atomic mass is mainly collision stop when ion implantation is performed, so that the implanted ions with large atomic mass collide with the atomic structure in the substrate to cause atomic sequence disorder and are easy to recover after subsequent annealing treatment, while the implanted ions with small atomic mass are electric field resistance stop when ion implantation is performed, the implanted ions with large atomic mass enter the ion implantation first, at the moment, atomic lattices are disturbed, and the ion implantation is performed after the implanted ions with small atomic mass, so that secondary damage to the lattices can be reduced, the implantation depth of the implanted ions with small atomic mass is easy to control, and the ion implantation depth of the semiconductor structure is also beneficial to control, so as to achieve the effect of reducing leakage current.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional technology, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
2-6 are cross-sectional views of steps of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure.
Reference numerals:
1: a semiconductor substrate; 2: oxide layer, 3: isolation structure, 4: photoresist layer, 5: and the well region.
Detailed Description
A semiconductor structure and a method for fabricating the same according to the present disclosure are further described in detail with reference to the accompanying drawings and the detailed description.
As described in the background art, in the manufacturing method of the semiconductor structure, leakage current is easily caused when ion implantation is performed, and the inventors have studied and found that, when an ion implantation process is performed, an impact force of implanted ions with small atomic mass on atoms in a substrate is small, and the atoms are easily aggregated to cause a defect that lattice forms aggregated atoms, and the defect is not easily repaired even if an annealing process is subsequently performed, and thus leakage current is easily caused.
The inventors have also found that when performing continuous ion implantation, i.e. when performing at least two ion implantations during the semiconductor structure manufacturing process, such as the process of forming the well region 5 and the source/drain regions, two ion implantations are required, and the implantation sequence of the implanted ions affects the leakage current effect of the semiconductor structure, for example, when performing continuous ion implantation on the same region, if the implanted ions with small atomic mass are implanted first and then the implanted ions with large atomic mass are implanted, because the implanted ions with small atomic mass have small impact force on silicon atoms, they are easy to form aggregated silicon atoms, which results in generation of lattice defects, and they are also not easy to recover in the subsequent process, and affect the depth and diffusion range of the ion implantation, while the implanted ions with large atomic mass also cause secondary impact on the silicon atom structure after implantation due to large atomic mass, which also causes secondary impact on the silicon atom structure after implantation with small atomic mass, which increases lattice damage to the semiconductor structure, resulting in generation of larger leakage current. The concept of the large atomic mass and the small atomic mass is obtained by comparing the atomic masses of the implanted ions when continuous ions are implanted. Not limited to the size of the atomic mass of the implanted ions themselves.
The inventor provides a preparation method of a semiconductor structure, which can reduce the crystal lattice damage of the semiconductor structure and reduce the leakage current problem. Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure, and fig. 2-6 are cross-sectional views of a semiconductor structure at various steps of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure.
A method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is described below with reference to the drawings.
As shown in fig. 1, a method for fabricating a semiconductor structure according to an embodiment of the present disclosure includes providing a semiconductor substrate 1; carrying out continuous ion implantation on the semiconductor substrate 1, and carrying out implantation according to the sequence of the atomic mass of the implanted ions from large to small; an annealing process is performed.
As shown in fig. 2, the semiconductor substrate 1 may be, but is not limited to, a silicon substrate, and the semiconductor substrate 1 in this embodiment may include a silicon substrate. In other examples, the semiconductor substrate 1 may include a semiconductor substrate 1 such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The semiconductor substrate 1 may include device structures formed therein, for example, the semiconductor substrate 1 may have isolation structures 3 formed therein.
As shown in fig. 3 to 6, the semiconductor substrate 1 is subjected to successive ion implantation, and the implantation is performed in the order of decreasing atomic mass of the implanted ions, that is, when the ion implantation is performed, the implanted ions having large atomic mass are implanted into the semiconductor substrate 1 first, and then the implanted ions having small atomic mass are implanted into the semiconductor substrate 1.
Specifically, when performing continuous ion implantation on the semiconductor substrate 1, implantation regions of implanted ions with different atomic masses in the continuous ion implantation process are at least partially the same, or the continuous ion implantation process needs to be implanted into the same region, it should be noted that the continuous ion implantation process refers to performing at least two times of ion implantation on at least part of the same region of the same semiconductor substrate 1, and the following description of the present disclosure takes two times of continuous ion implantation as an example for description, where the processes of two times of continuous ion implantation are not necessarily consecutive, for example, other processes may be included between two times of ion implantation, as long as two times of continuous ion implantation are performed into at least part of the same region.
As shown in fig. 3 to fig. 6, a specific example of continuous ion implantation into the same region in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure is shown, specifically, continuous ion implantation into the same region in a semiconductor substrate forms a source drain region in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, as shown in fig. 3, an implantation region for continuous ion implantation is defined first, a shielding material may be formed on the surface of the semiconductor substrate 1, the shielding material shields a region not requiring ion implantation, so that the implantation region requiring ion implantation is exposed, then implantation ions with large atomic mass and implantation ions with small atomic mass are sequentially implanted into the implantation region in order from large atomic mass to small atomic mass, and finally, annealing treatment is performed to repair lattice damage.
Fig. 4 is a schematic view of a semiconductor structure after implantation of implanted ions with large atomic mass, as shown in fig. 4, when the implanted ions with large atomic mass are implanted into the semiconductor substrate 1, the implanted ions with large atomic mass are implanted to a shallow depth and distributed more uniformly, and the implanted ions with large atomic mass are generally mainly concentrated in a relatively upper region of the semiconductor substrate 1, i.e., a region a shown in fig. 4; as shown in fig. 5, after the implantation of the implanted ions with small atomic mass, the implanted ions with small atomic mass are generally concentrated and distributed in the lower region of the semiconductor substrate 1 relative to the region a, i.e., the region B shown in fig. 5, as shown in fig. 6, which is a schematic structural diagram of the semiconductor structure after the ion implantation and annealing, and after the annealing treatment, the damage to the lattice of the silicon atomic structure in the semiconductor structure is repaired.
Therefore, according to the manufacturing method of the semiconductor structure disclosed by the embodiment of the disclosure, the injection stopping mechanism of the injected ions with large atomic mass during ion injection is mainly collision stopping, so that the injected ions with large atomic mass collide with the silicon atomic structure to cause disorder of silicon atomic sequences, and are easy to recover after subsequent annealing treatment, while the injected ions with small atomic mass are stopped by electric field resistance during ion injection, and the injected ions with large atomic mass firstly enter the ion injection, so that the silicon atomic crystal lattice is disordered, and the injected ions with small atomic mass are injected with ions later, so that the secondary damage to the crystal lattice can be reduced, the injection depth of the injected ions with small atomic mass is easy to control, and the ion injection depth of the semiconductor structure is also easy to control, so as to achieve the effect of reducing leakage current.
As shown in fig. 4, after ion implantation is performed on implanted ions with large atomic mass, the silicon atom sequence of the semiconductor substrate is disturbed, and implanted ions with small atomic mass easily pass through the disturbed region of the silicon atom sequence and do not cause secondary damage to the semiconductor substrate, so that damage to crystal lattices by ion implantation can be reduced, and the repair difficulty of a subsequent annealing process can be reduced.
In some embodiments of the present disclosure, the implanted ions may include at least two ions of the third main group and the fifth main group elements, that is, the implanted ions may include at least two ions of the third main group, or the implanted ions may include at least two ions of the fifth main group, or the implanted ions may include at least one ion of the third main group and at least one ion of the fifth main group, for example, the implanted ions may include arsenic ions, boron ions, and indium ions.
In some specific examples of the present disclosure, the implant ions may be at least two of germanium ions, arsenic ions, boron ions, indium ions, and phosphorus ions, that is, the implant ions of the continuous ion implantation may include two, three, or four of germanium ions, arsenic ions, boron ions, indium ions, and phosphorus ions, for example, the implant ions of the continuous ion implantation may include arsenic ions and boron ions, or the implant ions of the continuous ion implantation may include phosphorus ions and boron ions, and the type and number of the implant ions may be specifically selected according to actual needs, wherein the implant ions of the at least two are implanted in order of decreasing atomic mass.
In some embodiments of the present disclosure, the implanted ions may include a first type of ions and a second type of ions, the atomic mass of the first type of ions being greater than the atomic mass of the second type of ions, and in the step of performing successive ion implantation on the semiconductor substrate 1: performing ion implantation of a first type of ions at a first dose and a first energy; and the second type of ions are implanted by the second dosage and the second energy, and the implantation depth and the damage to crystal lattices can be controlled by controlling the implantation dosage and the implantation energy of the first type of ions and the second type of ions, so that the effects of reducing leakage current and improving the electrical stability of the semiconductor structure are achieved. Alternatively, the first type of ions may comprise arsenic ions and the second type of ions may comprise boron ions.
Because the ion implantation is performed according to the order of the atomic mass from large to small, the ion implantation depth of the implanted ions with small atomic mass becomes shallow, and the current becomes small when the electrical property of the semiconductor structure is ensured.
In order to simplify the manufacturing method of the semiconductor structure, the implantation dose and implantation energy of one of the implantation ions with large atomic mass or the implantation ions with small atomic mass may be adjusted, for example, the stability of the semiconductor structure may be enhanced by increasing the implantation dose of the implantation ions with large atomic mass or decreasing the energy of the implantation ions with large atomic mass, specifically, in the manufacturing method of the semiconductor structure according to the embodiment of the present disclosure, by performing ion implantation in the order from large atomic mass to small, the implantation dose may be increased by 1% to 10% or the implantation energy may be decreased by 1% to 10% when the implantation ions with large atomic mass are implanted first to maintain the electrical stability of the device, and the specific adjustment of the implantation dose and implantation energy may be set according to the process and the type of the implantation ions.
Alternatively, the implantation energy and the implantation dose of the implanted ions with large atomic mass may be adjusted, and the implantation energy and the implantation dose of the implanted ions with small atomic mass may be adjusted only, for example, the implantation dose of the implanted ions with small atomic mass may be decreased or the implantation energy of the implanted ions with small atomic mass may be increased, or the implantation dose of the implanted ions with small atomic mass and the implantation energy of the implanted ions with small atomic mass may be decreased at the same time, and the magnitude of the implantation dose and the implantation energy may be controlled to achieve the effect of decreasing the leakage current.
Alternatively, the implantation dose of the implanted ions with large mass in the continuous ion implantation is generally 1E12atom/cm 2 ～1E16atom/cm 2 The injection energy is 2 KeV-200 KeV; in some specific examples of the disclosure, the first dose and the first energy may satisfy: the first dose is 1.01E12-1.1E16atom/cm 2 Or the first energy is 1.8KeV to 198KeV, so that the electrical stability can be improved by increasing the implantation dose of the implantation ions with large atomic mass by 1 to 10 percent or reducing the implantation energy of the implantation ions with large atomic mass by 1 to 10 percent. For example, when the ion implantation with small atomic mass is performed first and then the ion implantation with large atomic mass is performed in the related art, the implantation energy of the ion implantation with large atomic mass is 1E14atom/cm 2 If the implantation dose is 20KeV, the implantation dose of the implantation ions having a large atomic mass may be 1.01e14 to 1.1e14atom/cm when the implantation ions having a large atomic mass are implanted first in the preparation method of the embodiment of the present invention 2 Alternatively, the implantation energy of the implanted ions having a large atomic mass may be 18KeV to 19.8KeV. Wherein the first dose and the first energy are adjustable according to actual conditions. Or can be at the same timeThe implantation dose of the implantation ions with large atomic mass is increased and the implantation energy of the implantation ions with large atomic mass is reduced, and the same effect is achieved by relatively adjusting the increased implantation dose or the reduced implantation energy.
In some embodiments of the present disclosure, the first dose of the first type of ions may be 1.01E12 to 1.1E16Atm/cm 2 The first energy may be 2KeV to 200KeV, for example the first dose may be 1.1E13atom/cm 2 、1.1E14atom/cm 2 、1.1E15atom/cm 2 (ii) a The first energy may be 20KeV, 50KeV, 150KeV. In other embodiments of the present disclosure, the first dose may be 1E12 to 1E16atom/cm 2 The first energy may be 1.8KeV to 198KeV, for example, the first dose may be 1E13atom/cm 2 、1E14atom/cm 2 、1E15atom/cm 2 (ii) a The first energy may be 18KeV, 45KeV, 135KeV.
In some embodiments of the present disclosure, the step of performing the continuous ion implantation to the semiconductor substrate 1 may include: continuous ion implantation is performed into the semiconductor substrate 1 to form source and drain regions. Illustratively, ion source gas accelerated to a first energy is accelerated and injected into a semiconductor substrate 1, such as a silicon substrate, by an ion implanter, so that after first ions enter the silicon substrate, the original arrangement of silicon atoms is disturbed, as shown in a region a of fig. 4, where the silicon substrate contains the disordered arrangement of silicon atoms and the injected first ions; and then continuing to accelerate the ion source gas accelerated to the second energy into the silicon substrate by using the ion implanter, so that after the second type of ions enter the silicon substrate, the original silicon atom arrangement is disturbed, and as shown in a region B in fig. 4, the silicon substrate in the region B contains the disorderly arranged silicon atoms and the implanted second type of ions. Therefore, the ion implantation process of the source and drain regions of the active region can be performed according to the sequence of atomic mass from large to small, so that the leakage current of the transistor in the active region can be effectively reduced, and the performance of the semiconductor structure is improved. For example, a first type of ions, such as arsenic ions, may be implanted into the semiconductor substrate 1, and then a second type of ions, such as boron ions, may be implanted into the semiconductor substrate 1 to form source and drain regions.
In other exemplary embodiments, a gate trench is formed on the surface of the semiconductor substrate 1 where the source and drain regions are formed, then a gate oxide layer and a diffusion barrier layer are sequentially formed on the inner surface of the gate trench, and then a metal material is deposited in the gate trench to form a word line. Illustratively, the gate oxide layer may be formed by performing thermal oxidation or other deposition processes on the surface of the gate trench, and generally, the gate oxide layer may be made of silicon oxide; the diffusion barrier layer may be formed on the surface of the gate oxide layer away from the semiconductor substrate by a deposition process, and typically, the diffusion barrier layer may be made of titanium nitride or tantalum nitride for reducing or preventing diffusion between the word line and the semiconductor substrate. And depositing a metal layer on the surface of the diffusion barrier layer, wherein the metal layer can be selected from tungsten or other common word line conductive materials. At this time, both sides of the word line are a source region and a drain region.
In some embodiments of the present disclosure, before the continuous implantation of the semiconductor substrate 1, the method further includes: the oxide layer 2 is formed on the surface of the semiconductor substrate 1, specifically, the oxide layer 2 can be formed on the surface of the semiconductor by performing thermal oxidation treatment on the semiconductor substrate 1, or the oxide layer 2 can be formed on the surface of the semiconductor substrate 1 by deposition by using a physical vapor deposition method, a chemical vapor deposition method or an atomic layer deposition method, the oxide layer 2 has an insulating effect, implanted ions are implanted into the semiconductor substrate 1 through the oxide layer 2, and the direction of ion beams can be randomized, so that the implanted ions can enter the semiconductor substrate 1 at different angles without directly entering a channel.
In some embodiments of the present disclosure, as shown in fig. 3-6, the method for manufacturing a semiconductor structure further includes: forming an isolation structure 3 which penetrates through the oxide layer 2 and is at least partially located within the semiconductor substrate 1; forming a photoresist layer 4 on the surface of the isolation structure 3; the semiconductor substrate 1 is subjected to continuous ion implantation using the photoresist layer 4 as a mask.
The method of forming the isolation structure 3 may include: forming a mask layer (not shown in the figure) on the semiconductor substrate 1, wherein the mask layer is provided with an etching opening, the position and the shape of an isolation structure are defined by the etching opening, then, the oxide layer 2 and the semiconductor substrate 1 are etched along the etching opening to form an isolation groove, isolation layers are formed on the surface of the oxide layer 2 and in the isolation groove, the isolation groove is filled with the isolation layers, the isolation layers on the surface of the oxide layer 2 are removed, the isolation layers in the isolation groove are reserved to form an isolation structure 3 in the semiconductor substrate 1, the isolation structure 3 is made of at least one of silicon nitride and silicon oxide, and the isolation structure 3 isolates a plurality of active regions arranged at intervals in the semiconductor substrate 1; as shown in fig. 3, a photoresist layer 4 is formed on the surface of the isolation structure 3, wherein the photoresist layer 4 may have a shielding effect, and the semiconductor substrate 1 is subjected to a continuous ion implantation using the photoresist layer 4 as a mask to define an implantation region for the ion implantation.
Optionally, before performing the annealing treatment, the following steps are further included: the photoresist layer 4 is removed, the photoresist layer 4 is not easy to remove after annealing, and the photoresist is removed before the annealing process is performed, which is beneficial to completely removing the photoresist layer 4.
In some embodiments, the annealing process may be a Rapid Thermal Processing (RTP) process.
In some exemplary embodiments, before the continuous ions are implanted into the same region of the semiconductor substrate 1 to form the source and drain regions in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, the continuous ions may be implanted into the same region of the semiconductor substrate 1 to form the well region 5 in the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure, as shown in fig. 7. In the preparation process of the well region 5, an isolation structure 3 is formed in the semiconductor substrate 1, then an implantation region which needs continuous ion implantation is defined, a mask material can be formed on the surface of the semiconductor substrate 1, the mask material shields the region which does not need the ion implantation, so that the implantation region which needs the ion implantation is exposed, then implantation ions with large atomic mass and implantation ions with small atomic mass are sequentially implanted into the implantation region according to the sequence of the atomic mass from large to small, and finally, annealing treatment is carried out to repair lattice damage. The implanted ions with large atomic mass are implanted into the semiconductor substrate 1, the implanted ions with small atomic mass are implanted into the implanted ions with large atomic mass, and the implantation depth of the implanted ions with large atomic mass in the semiconductor substrate 1 is smaller than that of the implanted ions with small atomic mass in the semiconductor substrate. After annealing treatment, the damage of the silicon atom structure lattice in the semiconductor structure is repaired.
In some exemplary embodiments, the step of performing the continuous ion implantation to the semiconductor substrate 1 may include: continuous ion implantation is performed into the semiconductor substrate 1 to form a well region 5, specifically, a P-type well region 5 doped with P-type impurities or an N-type well region 5 doped with N-type impurities may be formed at the bottom of the semiconductor substrate 1, and the implantation depth of the well region 5 is greater than the depth of the isolation structure 3. Illustratively, ion source gas accelerated to a first energy is accelerated and injected into a semiconductor substrate 1, such as a silicon substrate, by an ion implanter, after first ions enter the silicon substrate, the original arrangement of silicon atoms is disturbed, a region of the silicon substrate into which the first ions are injected is called a first region, and the silicon substrate in the first region contains the disorderly arranged silicon atoms and the injected first ions; and then continuously utilizing the ion implanter to accelerate and implant the source gas of the ions accelerated to the second energy into the silicon substrate, so that after the second type of ions enter the silicon substrate, the original silicon atom arrangement is disturbed, the region of the silicon substrate implanted with the second type of ions is called a second region, the silicon substrate of the second region contains the silicon atoms and the implanted second type of ions which are disorderly arranged, so as to form a well region in the semiconductor substrate, wherein the first region is positioned above the second region in the direction vertical to the silicon substrate. Thus, the ion implantation process of the well region 5 of the semiconductor substrate 1 can be performed in the order of decreasing atomic mass, thereby effectively preventing the ion diffusion of the well region 5 and improving the performance of the semiconductor structure. For example, a first type of ions such as boron ions may be implanted into the semiconductor substrate 1, and then a second type of ions such as fluorine ions may be implanted into the semiconductor substrate 1 to form the P-type well region 5. In other exemplary embodiments, a continuous ion implantation may be performed within the semiconductor substrate 1 forming the well region 5 to form source and drain regions on the well region 5.
The present disclosure also provides a semiconductor structure.
According to the semiconductor structure of the embodiment of the disclosure, the semiconductor structure is prepared by the method of the semiconductor structure of the embodiment, and the semiconductor structure is implanted in the ion implantation process according to the sequence of the atomic masses from large to small, so that the leakage current can be reduced, and the electrical stability effect can be improved.
The above semiconductor structure may be applied to a memory, which may be a computing memory (e.g., DRAM, SRAM, DDR3SDRAM, DDR2SDRAM, DDRSDRAM, etc.), a consumer memory (e.g., DDR3SDRAM, DDR2SDRAM, DDRSDRAM, SDRSDRAM, etc.), a graphic memory (e.g., DDR3SDRAM, GDDR3SDMRA, GDDR4SDRAM, GDDR5SDRAM, etc.), a mobile memory, and the like. The manufacturing method of the semiconductor structure can be referred to the above description, and is not repeated herein.
The foregoing is illustrative of the preferred embodiments of the present disclosure, and it is noted that modifications and embellishments may be made by those of ordinary skill in the art without departing from the principles of the present disclosure, and should be considered within the scope of the present disclosure.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate;
carrying out continuous ion implantation on the semiconductor substrate, and carrying out implantation according to the sequence of the atomic mass of the implanted ions from large to small;
an annealing process is performed.
2. The method of claim 1, wherein the implanted ions comprise at least two ions of a group iii element and a group v element.
3. The method of claim 1, wherein the implanted ions comprise at least two of germanium ions, arsenic ions, boron ions, indium ions, and phosphorus ions.
4. The method of claim 1, wherein the implanted ions comprise a first type of ions and a second type of ions, the first type of ions having a greater atomic mass than the second type of ions, and wherein, in the step of performing a sequential ion implantation of the semiconductor substrate:
performing ion implantation of the first type of ions at a first dose and a first energy;
ion implantation of the second type of ions is performed at a second dose and at a second energy.
5. The method of claim 4, wherein the first dose and the first energy satisfy: the first dosage is 1.01E12-1.1E16atom/cm 2 Or the first energy is 1.8 KeV-198 KeV.
6. The method of claim 5, wherein the first dose is 1.01E12 to 1.1E16atom/cm 2 The first energy is 2KeV to 200KeV.
7. The method of claim 5, wherein the first dose is 1E 12-1E 16atom/cm 2 The first energy is 1.8KeV to 198KeV.
8. The method of claim 5, wherein the first ions comprise arsenic ions and the second ions comprise boron ions.
9. The method of claim 5, wherein the first ions comprise phosphorus ions and the second ions comprise boron ions.
10. The method of claim 4, wherein the step of performing a sequential ion implantation into the semiconductor substrate comprises: and carrying out continuous ion implantation in the semiconductor substrate to form a well region.
11. The method of claim 4, wherein the step of performing a continuous ion implantation into the semiconductor substrate further comprises: and carrying out continuous ion implantation in the semiconductor substrate to form a source drain region.
12. The method of claim 1, further comprising, prior to the step of continuously implanting the semiconductor substrate: and forming an oxide layer on the surface of the semiconductor substrate.
13. The method of claim 12, further comprising:
forming an isolation structure through the oxide layer and at least partially within the semiconductor substrate;
forming a light resistance layer on the surface of the isolation structure;
and carrying out continuous ion implantation on the semiconductor substrate by taking the photoresist layer as a mask.
14. The method of claim 13, further comprising the step of, prior to performing the annealing process: and removing the photoresist layer.
15. A semiconductor structure prepared by the method of any one of claims 1-14.
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