CN115172262A - Method for forming semiconductor structure and method for manufacturing semiconductor device - Google Patents

Method for forming semiconductor structure and method for manufacturing semiconductor device Download PDF

Info

Publication number
CN115172262A
CN115172262A CN202210716509.0A CN202210716509A CN115172262A CN 115172262 A CN115172262 A CN 115172262A CN 202210716509 A CN202210716509 A CN 202210716509A CN 115172262 A CN115172262 A CN 115172262A
Authority
CN
China
Prior art keywords
fin
fins
epitaxial structure
material layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210716509.0A
Other languages
Chinese (zh)
Inventor
刘洋
杨渝书
耿金鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Original Assignee
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai IC R&D Center Co Ltd, Shanghai IC Equipment Material Industry Innovation Center Co Ltd filed Critical Shanghai IC R&D Center Co Ltd
Priority to CN202210716509.0A priority Critical patent/CN115172262A/en
Publication of CN115172262A publication Critical patent/CN115172262A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a forming method of a semiconductor structure and a manufacturing method of a semiconductor device, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area, the first area is provided with a first fin, the second area is provided with a second fin, and the conductivity types of the first fin and the second fin are opposite; sequentially forming a hard mask material layer and a side wall material layer, and combining the side wall material layers between the adjacent first fins and second fins to form a boundary side wall; and forming a first epitaxial structure in the first region and a second epitaxial structure in the second region by using the hard mask material layer and taking the boundary side wall as a spacer layer of the first region and the second region. In the invention, the side wall material layer is combined between the first fin and the second fin to form the boundary side wall which is used as a spacing layer of the subsequent first epitaxial structure and the second epitaxial structure, thereby preventing the short circuit problem of the first epitaxial structure and the second epitaxial structure.

Description

Method for forming semiconductor structure and method for manufacturing semiconductor device
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for forming a semiconductor structure and a method for manufacturing a semiconductor device.
Background
In the field of semiconductor technology, a Static Random Access Memory (SRAM) device is widely used as a typical semiconductor device in electronic devices such as computers, mobile phones, and digital cameras. In the prior art, fin field effect transistors (finfets) are used as transistor devices of SRAM cells in some designs to improve the density and performance of SRAM.
Taking a FinFET as a transistor of an SRAM device as an example, an N-type FinFET and a P-type FinFET are simultaneously disposed in a storage region of the SRAM device, and the N-type FinFET (nFET) and the P-type FinFET (pFET) are relatively close to each other, which causes a short circuit (short circuit) problem between an embedded epitaxial structure (as a source-drain structure, e.g., siP) of the N-type FinFET and an embedded epitaxial structure (as a source-drain structure, e.g., siGe) of the P-type FinFET due to the laterally protruding topography of the N-type FinFET and the P-type FinFET.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor structure and a method for manufacturing a semiconductor device, which aim to solve the problem of short circuit caused by the fact that an embedded epitaxial structure of an N-type FinFET and an embedded epitaxial structure of a P-type FinFET are close to each other.
In order to solve the above technical problem, a method for forming a semiconductor structure provided by the present invention includes: providing a substrate, wherein the substrate is provided with a first area and a second area, the first area is provided with a plurality of first fins, the second area is provided with a plurality of second fins, the conductivity types of the first fins are opposite to that of the second fins, and the distance between the adjacent first fins and the distance between the adjacent second fins are both larger than the distance between the adjacent first fins and the adjacent second fins; sequentially forming a hard mask material layer and a side wall material layer, wherein the hard mask material layer is used for covering the surface of the substrate, the outer wall of the first fin and the outer wall of the second fin in a conformal manner, the side wall material layer is used for covering the hard mask material layer, and the side wall material layers between the first fin and the second fin which are adjacent are combined to form a boundary side wall; and taking the boundary side wall as a spacing layer of the first area and the second area, forming a first epitaxial structure in the first area, and forming a second epitaxial structure in the second area, so that the boundary side wall isolates the adjacent first epitaxial structure and the second epitaxial structure.
Optionally, an isolation dielectric layer covers the substrate, and the isolation dielectric layer is filled to a partial height of the first fin and the second fin.
Optionally, before forming the hard mask material layer, a plurality of dummy gates arranged at intervals are formed on the isolation dielectric layer, and the dummy gates cross over the first fins and the second fins.
Optionally, the hard mask material layer and the side wall material layer are formed by using an ALD process, and the hard mask material layer covers the isolation dielectric layer, the first fin, the second fin and the dummy gate in a conformal manner.
Optionally, the step of forming the first epitaxial structure in the first region includes: forming a first graphical mask layer, covering the second region and at least part of the boundary side wall, and exposing the first region; removing the side wall material layer, the hard mask material layer and the first fin with at least partial height of the first region by using the first patterned mask layer; and removing the first patterned mask layer, and epitaxially forming the first epitaxial structure on the rest first fins, wherein the first epitaxial structure is in contact with one side of the boundary side wall.
Optionally, after the first epitaxial structure is formed, an ISSG process is used to form an oxide layer on the outer wall of the first epitaxial structure.
Optionally, the step of forming the second epitaxial structure in the second region includes: forming a second graphical mask layer, covering the first region and at least part of the boundary side wall, and exposing the second region; removing the side wall material layer, the hard mask material layer and the second fin with at least partial height of the second region by using the second patterned mask layer; and removing the second patterned mask layer, and epitaxially forming a second epitaxial structure on the rest second fins, wherein the second epitaxial structure is in contact with one side of the boundary side wall.
Optionally, the hard mask material layer includes silicon nitride, and the sidewall material layer includes silicon oxide.
Optionally, the first region is a P-type region, the first epitaxial structure includes SiGe, the second region is an N-type region, and the second epitaxial layer includes SiP.
According to another aspect of the present invention, a manufacturing method of a semiconductor device is also provided, and the manufacturing method of the semiconductor device includes the forming method of the semiconductor structure.
In summary, in the invention, when the hard mask material layer and the sidewall material layer are formed, the hard mask material layer covers the first region and the second region to serve as a hard mask, the sidewall material layer covers the hard mask material layer, the sidewall material layer is combined between the first fin and the second fin to form a boundary sidewall, and the boundary sidewall is located between the first fin and the second fin and can serve as a spacer layer of a first epitaxial structure formed on the first fin and a second epitaxial structure formed on the second fin subsequently, so that the short circuit problem of the first epitaxial structure and the second epitaxial structure is prevented, the forming process of the first epitaxial structure and the second epitaxial structure is simplified, and the yield is improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1 is a flowchart of a method for forming a semiconductor structure provided in the present embodiment;
fig. 2 to 11 are schematic structural diagrams corresponding to respective steps of the method for forming a semiconductor structure provided in this embodiment.
In the drawings:
10-a substrate; 11-an isolation dielectric layer; AA-first region; BB-a second area; 12-a first fin; 13-second fins; d1-a first direction; d2-a second direction;
21-a hard mask material layer; 22-side wall material layer; 23-boundary sidewall; 31-a first patterned masking layer; 32-a first epitaxial structure;
33-an oxide layer; 41-a second patterned mask layer; 42-second epitaxial structure.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are intended to be part of actual structures. In particular, the drawings are intended to show different emphasis, sometimes in different proportions.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or at least two of the feature unless the content clearly dictates otherwise.
Example one
Fig. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment.
As shown in fig. 1, the method for forming a semiconductor structure provided in this embodiment includes the following steps:
s01: providing a substrate, wherein the substrate is provided with a first area and a second area, the first area is provided with a plurality of first fins, the second area is provided with a plurality of second fins, the conductivity types of the first fins are opposite to that of the second fins, and the distance between the adjacent first fins and the distance between the adjacent second fins are both larger than the distance between the adjacent first fins and the adjacent second fins;
s02: sequentially forming a hard mask material layer and a side wall material layer, wherein the hard mask material layer is used for covering the surface of the substrate, the outer wall of the first fin and the outer wall of the second fin in a conformal manner, the side wall material layer is used for covering the hard mask material layer, and the side wall material layers between the first fin and the second fin which are adjacent are combined to form a boundary side wall;
s03: and taking the boundary side wall as a spacing layer of the first area and the second area, forming a first epitaxial structure in the first area, forming a second epitaxial structure in the second area, and isolating the adjacent first epitaxial structure and the second epitaxial structure by using the boundary side wall.
Fig. 2 to fig. 11 are schematic structural diagrams corresponding to respective steps of a method for forming a semiconductor structure provided in this embodiment, and the method for forming a semiconductor structure will be described in detail with reference to fig. 2 to fig. 11.
First, referring to fig. 2, step S01 is performed to provide a substrate 10, the substrate 10 has a first area AA and a second area BB, a first fin 12 is formed on the first area AA, a second fin 13 is formed on the second area BB, the first fin 12 and the second fin 13 have opposite conductivity types, and the distance between the adjacent first fins 12 and the distance between the adjacent second fins 13 are both greater than the distance between the adjacent first fins 12 and the adjacent second fins 13.
The substrate 10 may be any suitable base material known to those skilled in the art, and may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), and the like. The material of the substrate 10 in this embodiment is illustrated by taking silicon (silicon substrate) as an example.
Specifically, the silicon substrate may be etched by using a dual patterning technique or a multiple patterning technique to form a plurality of fins (including the first fin 12 and the second fin 13) arranged at intervals on the substrate 10, the plurality of fins may be arranged along a first direction D1 and each fin extends along a second direction D2, and the first direction D1 and the second direction D2 are orthogonal on the surface of the substrate 10. The plurality of fins may have the same height or as much as possible. The substrate 10 is covered with an isolation dielectric layer 11, and the isolation dielectric layer 11 fills a part of the height of the fins and exposes the fins with the rest height so as to expose the fins on the isolation dielectric layer 11 for forming active regions later. The substrate 10 is formed to have a first region AA and a second region BB, the fins on the first region AA can be the first fins 12, the fins on the second region BB can be the second fins 13, and the first fins 12 and the second fins 13 can have opposite conductivity types by at least two ion implantation processes of different conductivity types. Specifically, the first fins 12 in the first region AA may have a first pitch, the second fins 13 in the second region BB may have a second pitch, and the adjacent first fins 12 and second fins 13 have a smaller pitch than the first pitch and the second pitch. The first pitch may be the same as or different from the second pitch, and the width of the first fins 12 may be the same as or different from the width of the second fins 13. It is understood that, due to the smaller distance between the adjacent first fins 12 and the second fins 13, the risk of shorting the epitaxial structures when the laterally protruding epitaxial structures are formed later is greater than the risk of shorting the epitaxial structures between the first fins 12 or between the second fins 13.
In the present embodiment, the first region AA may be a P-type region, and the second region BB may be an N-type region, i.e., the first fin 12 is used to form a P-type FinFET, and the second fin 13 is used to form an N-type FinFET. Of course, in practice, limited by the etching process, the angle between the sidewall of the formed fin and the surface of the substrate 10 may be 85 ° to 90 °, that is, the cross-sectional shape of the fin along the first direction D1 is trapezoidal (narrow at the top and wide at the bottom).
In one embodiment, taking the first region AA as a P-type region and the second region BB as an N-type region as an example, the first pitch may be 52nm, the second pitch may be 69nm, and the pitch between adjacent first fins 12 and second fins 13 may be 48.5nm.
Next, a plurality of dummy gates (not shown) arranged at intervals are formed on the isolation dielectric layer 11, the plurality of dummy gates cross the first fin 12 and the second fin 13 along the first direction D1 (each dummy gate extends along the first direction D1 and the plurality of dummy gates are arranged along the second direction D2), a region where the dummy gate covers the first fin 12 and the second fin 13 is used as a gate region, a gate structure (for example, a metal gate structure) is formed in the subsequent step, and regions on two sides of the first fin 12 and the second fin 13, which are exposed by the dummy gates, are used as source and drain regions to form source and drain structures (source and drain). And moreover, a side wall structure can be formed on the side wall of the virtual grid electrode to protect the virtual grid electrode. It should be noted that, in the drawings in this embodiment, all the source and drain regions are cross-sectional views along the first direction D1, and the dummy gate, the sidewall structure, and the like are not shown.
Next, referring to fig. 3, step S02 is performed to form a hard mask material layer 21, which covers the isolation dielectric layer 11, the outer walls of the first fins 12, the outer walls of the second fins 13, and the outer walls of the dummy gates.
Specifically, the hard mask material layer 21 may be a hard material with a better isolation effect, such as silicon nitride or silicon carbonitride, and is preferably formed by an ALD (atomic layer deposition) process to improve step coverage and film quality. The thickness of the hard mask material layer 21 is thin, for example, 10 to 50 angstroms, so as to reduce the stress. Of course, the hard mask material layer 21 will also extend to cover the dummy gate and the sidewall structures, which are not shown in the figure.
Next, referring to fig. 4, a sidewall material layer 22 is formed to cover the outer wall of the hard mask material layer 21 until the sidewall material layers 22 between the adjacent first fins 12 and second fins 13 are combined to form a boundary sidewall 23.
The material of the sidewall material layer 22 is different from the material of the hard mask material layer 21, and the two materials are easy to realize a larger etching selectivity. Taking the hard mask material layer 21 as an example of silicon nitride, the sidewall material layer 22 may be silicon oxide, and formed by using an ALD process, so as to improve the step coverage and the film quality. Moreover, the feature that the ALD process is easy to control the film thickness can be further utilized to preferably control the thickness of the formed sidewall material layer 22, so that the sidewall material layers 22 between the adjacent first fins 12 and second fins 13 are combined to form the boundary sidewall 23, the boundary sidewall 23 is located between the first area AA and the second area BB, and the sidewall material layers 22 between the first fins 12 or between the second fins 13 are not combined because the distance between the first fins 12 or between the second fins 13 is relatively large.
Next, step S03 is performed, the boundary sidewall 23 is used as a spacer of the first area AA and the second area BB, a first epitaxial structure 32 is formed in the first area AA, a second epitaxial structure 42 is formed in the second area BB, and the boundary sidewall 23 is used to isolate the adjacent first epitaxial structure 32 and the second epitaxial structure 42.
The step of forming the first epitaxial structure 32 at the first area AA may, for example, comprise:
referring to fig. 5, a first patterned mask layer 31 is formed to cover the second region BB and at least a portion of the boundary sidewall 23, and expose the first region AA. The first patterned mask layer 31 may be a patterned photoresist layer, and covers the sidewall material layer 22 and the boundary sidewall 23 of the second region BB, and the width of the covered boundary sidewall 23 may be determined according to the width of the first epitaxial structure 32 (the width of the side close to the boundary sidewall 23) next to the boundary sidewall 23. That is, the wider the width of the first epitaxial structure 32 next to the boundary sidewall 23, the narrower the width of the first patterned mask layer 31 covering the boundary sidewall 23. In practice, the first patterned mask layer 31 covers at least half of the width of the boundary sidewall 23, so as to prevent the boundary sidewall 23 from being deformed (inclined or bent) due to over-etching and being too narrow, which is not favorable for the boundary sidewall 23 to function as a spacer.
Referring to fig. 6, the exposed sidewall material layer 22, the hard mask material layer 21, and the first fin 12 with at least a partial height are sequentially removed by using the first patterned mask layer 31. Specifically, a dry etching process may be used to remove the sidewall material layer 22 and the exposed boundary sidewall 23 on the first area AA, remove the hard mask material layer 21 on the first area AA and on the outer wall of the first fin 12, and then remove the first fin 12 with at least a portion of the height above the isolation dielectric layer 11.
Preferably, the first fin 12 with a (remaining) partial height and the hard mask material layer 21 on the sidewall of the first fin 12 are also remained according to the size (height and width) of the subsequent first epitaxial structure 32, wherein the height of the remaining hard mask material layer 21 is higher than the height of the remaining first fin 12 (height above the isolation dielectric layer 11), and the remaining hard mask material layer 21 can be used to preferably constrain the shape and size of the subsequent first epitaxial structure growth. It should be understood that, while ensuring that the top surface of the subsequently formed first epitaxial structure is substantially the same as the height of the first fin 12, the higher the height of the remaining first fin 12, the smaller the size of the first epitaxial structure grown on the remaining first fin 12.
Referring to fig. 7, the first patterned mask layer 31 is removed, and a first epitaxial structure 32 is epitaxially formed on the remaining first fins 12, where the first epitaxial structure 32 may contact one side of the boundary sidewall 23. Taking the first region AA as a P-type region as an example, the first epitaxial structure 32 may be formed on the remaining first fins 12 by an epitaxial process, the material of the first epitaxial structure 32 may include SiGe, and the first epitaxial structures 32 on both sides of the dummy gate are used to apply a compressive stress to the first fins 12 (conductive channel) under the dummy gate, so as to improve the mobility of hole carriers. The first epitaxial structure 32 is formed to grow upward along the remaining first fins 12, and the cross-sectional shape of the first epitaxial structure 32 along the first direction D1 is diamond-shaped (diamond-shaped), and two side surfaces thereof protrude outward to encroach on spaces (gaps) on two sides thereof.
In particular, since the boundary sidewall 23 is disposed between the first fin 12 and the second fin 13, the side of the first epitaxial structure 32 close to the second fin 13 is limited by the boundary sidewall 23, that is, the side of the first epitaxial structure 32 grown on the first fin 12 contacts the boundary sidewall 23, thereby being beneficial to maintaining the isolation between the first fin 12 and the second fin 13. Of course, the first epitaxial structures 32 grown on the other first fins 12 away from the second fins 13 are not affected.
Referring to fig. 8, an oxide layer 33 is formed to cover the outer wall of the first epitaxial structure 32.
Specifically, for example, an ISSG process (in-situ steam generation) may be used to form the oxide layer 33 on the outer wall of the first epitaxial structure 32 for protecting the first epitaxial structure 32, so as to take account of the formation rate of the oxide layer 33 and the film quality. For example, the material of the first epitaxial structure 32 includes SiGe, and the material of the oxide layer 33 may be silicon oxide.
Next, the step of forming the second epitaxial structure in the second region BB may, for example, include:
referring to fig. 9, a second patterned mask layer 41 is formed to cover the first region AA and at least a portion of the boundary sidewall 23, and expose the second region BB.
The second patterned mask layer 41 may be a patterned photoresist layer covering the isolation dielectric layer 11 in the first area AA, the oxide layer 33 of the first epitaxial structure 32, and at least a portion of the boundary sidewall 23, and the width of the covered boundary sidewall 23 may be determined according to the width of the second epitaxial structure next to the boundary sidewall 23. That is, the wider the width of the second epitaxial structure (to be subsequently formed) near the boundary sidewall 23, the narrower the width of the second patterned mask layer 41 covers the boundary sidewall 23. In practice, the second patterned mask layer 41 may cover at least half of the distance between the adjacent first fins 12 and the second fins 13, so as to prevent the boundary sidewall 23 from being narrowed after over-etching, thereby causing the boundary sidewall 23 to be deformed (inclined or bent).
Referring to fig. 10, the exposed sidewall material layer 22, the hard mask material layer 21, and the second fin 13 with at least a partial height are sequentially removed by using the second patterned mask layer 41, and the boundary sidewall 23 (or the remaining boundary sidewall 23) is located between the first area AA and the second area BB. Specifically, the method for removing the sidewall material layer 22, the hard mask material layer 21 and the second fin 13 with at least a portion of the height in the second area BB may refer to the method for removing the sidewall material layer, the hard mask material layer and the second fin in the first area AA by using the first patterned mask layer, which is not described herein again.
Referring to fig. 11, the second patterned mask layer 41 is removed, and a second epitaxial structure 42 is epitaxially formed on the remaining second fin 13, where the second epitaxial structure 42 contacts one side of the boundary sidewall 23.
Taking the second region BB as an N-type region as an example, the second epitaxial structure 42 may be formed on the remaining second fin 13 by an epitaxial process, the material of the second epitaxial structure 42 may include SiP, and the second epitaxial structures 42 on both sides of the dummy gate are utilized to subject the second fin 13 (conductive channel) under the dummy gate to a tensile stress, so as to improve the mobility of electron carriers. The second epitaxial structure 42 is formed to grow upward along the remaining second fins 13, and the cross-sectional shape of the second epitaxial structure 42 along the first direction D1 is diamond-shaped (diamond-shaped), and two side surfaces of the diamond-shaped cross-sectional shape protrude outward to occupy spaces on two sides of the diamond-shaped cross-sectional shape.
In particular, since the boundary sidewall 23 is disposed between the first fin 12 and the second fin 13, a side of the second epitaxial structure 42 close to the first fin 12 is limited by the boundary sidewall 23, that is, one side of the second epitaxial structure 42 may contact the boundary sidewall 23, and the boundary sidewall 23 is used to isolate the first epitaxial structure 32 from the second epitaxial structure 42, thereby preventing a short circuit (short circuit) between the adjacent first epitaxial structure 32 and the second epitaxial structure 42. Of course, the first epitaxial structures 32 grown on the other second fins 13 that are distant from the first fins 12 are not affected.
Example two
The second embodiment also provides a manufacturing method of a semiconductor device, and the semiconductor device comprises the semiconductor structure. In one embodiment, the semiconductor device may be, for example, an SRAM device. Specifically, the SRAM device comprises a storage area and a logic area, wherein a storage unit is formed on the storage area, a logic unit is formed on the logic area, and FinFETs are used as transistor devices for the storage unit and the logic unit. The memory cell and the logic cell each include a P-type FinFET and an N-type FinFET, wherein the memory cell has a pull-up transistor (e.g., a P-type FinFET) and a pull-down transistor (e.g., an N-type FinFET) that are adjacent (parallel), and the pull-up transistor and the pull-down transistor are spaced closer (e.g., smaller than the pitch between other P-type finfets or other N-type finfets), that is, the memory region (memory cell) of the SRAM device may be formed by the above-mentioned semiconductor structure forming method, so as to prevent the epitaxial structures of the adjacent pull-up transistor and pull-down transistor from being shorted. The spacing between the P-type FinFET and the N-type FinFET in the logic region can be set normally (the same as or larger than the spacing between other P-type FinFETs or other N-type FinFETs), so that the semiconductor structure can be formed in the logic region synchronously with the memory region without an additional photomask and a corresponding process. However, it is worth mentioning that when the side wall material layers of the storage region are combined to form the boundary side wall, the side wall material layers of the logic region are not combined to form the boundary side wall, but the formation of the semiconductor structure in the logic region is not affected, and the effect of preventing the epitaxial structure from being short-circuited is also achieved in the process. Of course, it is also feasible that no boundary sidewall spacer is formed between the P-type FinFET and the N-type FinFET in the logic region.
In other words, the method for manufacturing a semiconductor device provided by the present embodiment may include the method for forming a semiconductor structure as described above.
In summary, in the invention, when the hard mask material layer and the sidewall material layer are formed, the hard mask material layer covers the first region and the second region to serve as a hard mask, the sidewall material layer covers the hard mask material layer, the sidewall material layer is combined between the first fin and the second fin to form a boundary sidewall, and the boundary sidewall is located between the first fin and the second fin and can serve as a spacer layer of a first epitaxial structure formed on the first fin and a second epitaxial structure formed on the second fin subsequently, so that the short circuit problem of the first epitaxial structure and the second epitaxial structure is prevented, the forming process of the first epitaxial structure and the second epitaxial structure is simplified, and the yield is improved.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first area and a second area, the first area is provided with a plurality of first fins, the second area is provided with a plurality of second fins, the conductivity types of the first fins are opposite to that of the second fins, and the distance between the adjacent first fins and the distance between the adjacent second fins are both larger than the distance between the adjacent first fins and the adjacent second fins;
sequentially forming a hard mask material layer and a side wall material layer, wherein the hard mask material layer is used for covering the surface of the substrate, the outer wall of the first fin and the outer wall of the second fin in a conformal manner, the side wall material layer is used for covering the hard mask material layer, and the side wall material layers between the first fin and the second fin which are adjacent are combined to form a boundary side wall;
and taking the boundary side wall as a spacing layer of the first area and the second area, forming a first epitaxial structure in the first area, and forming a second epitaxial structure in the second area, so that the boundary side wall isolates the adjacent first epitaxial structure and the second epitaxial structure.
2. The method as claimed in claim 1, wherein the substrate is covered with an isolation dielectric layer, and the isolation dielectric layer is filled to a portion of the height of the first fin and the second fin.
3. The method as claimed in claim 2, wherein before the hard mask material layer is formed, a plurality of dummy gates are formed on the isolation dielectric layer at intervals, wherein the dummy gates cross over the first fins and the second fins.
4. The method as claimed in claim 3, wherein the hard mask material layer and the sidewall spacer material layer are formed by an ALD process, and the hard mask material layer conformally covers the isolation dielectric layer, the first fin, the second fin and the dummy gate.
5. The method of claim 1, wherein the step of forming the first epitaxial structure in the first region comprises:
forming a first graphical mask layer, covering the second region and at least part of the boundary side wall, and exposing the first region;
removing the side wall material layer, the hard mask material layer and the first fin with at least partial height of the first region by using the first patterned mask layer;
and removing the first patterned mask layer, and epitaxially forming the first epitaxial structure on the rest first fins, wherein the first epitaxial structure is in contact with one side of the boundary side wall.
6. The method as claimed in claim 5, wherein an ISSG process is performed to form an oxide layer on the outer wall of the first epitaxial structure after the first epitaxial structure is formed.
7. The method as claimed in claim 5 or 6, wherein the step of forming the second epitaxial structure in the second region comprises:
forming a second graphical mask layer, covering the first region and at least part of the boundary side wall, and exposing the second region;
removing the side wall material layer, the hard mask material layer and the second fin with at least part of the height of the second region by using the second patterned mask layer;
and removing the second patterned mask layer, and epitaxially forming a second epitaxial structure on the rest second fins, wherein the second epitaxial structure is in contact with one side of the boundary side wall.
8. The method as claimed in claim 1, wherein the hard mask material layer comprises silicon nitride, and the spacer material layer comprises silicon oxide.
9. The method as claimed in claim 1, wherein the first region is a P-type region, the first epitaxial structure comprises SiGe, the second region is an N-type region, and the second epitaxial layer comprises SiP.
10. A manufacturing method of a semiconductor device, characterized by comprising the forming method of the semiconductor structure according to any one of claims 1 to 9.
CN202210716509.0A 2022-06-22 2022-06-22 Method for forming semiconductor structure and method for manufacturing semiconductor device Pending CN115172262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210716509.0A CN115172262A (en) 2022-06-22 2022-06-22 Method for forming semiconductor structure and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210716509.0A CN115172262A (en) 2022-06-22 2022-06-22 Method for forming semiconductor structure and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
CN115172262A true CN115172262A (en) 2022-10-11

Family

ID=83487696

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210716509.0A Pending CN115172262A (en) 2022-06-22 2022-06-22 Method for forming semiconductor structure and method for manufacturing semiconductor device

Country Status (1)

Country Link
CN (1) CN115172262A (en)

Similar Documents

Publication Publication Date Title
US9362181B1 (en) Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
US7358142B2 (en) Method for forming a FinFET by a damascene process
KR101412906B1 (en) Structure and method for a field effect transistor
US7470951B2 (en) Hybrid-FET and its application as SRAM
TWI466293B (en) Integrated circuit having metal gate stacks and method for manufacturing the same
US10388747B1 (en) Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure
US11276651B2 (en) IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structure
US10366930B1 (en) Self-aligned gate cut isolation
US7303963B2 (en) Method for manufacturing cell transistor
US11502200B2 (en) Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material
US8274102B2 (en) Semiconductor device
CN110875191A (en) Method for manufacturing fin type transistor
CN115172262A (en) Method for forming semiconductor structure and method for manufacturing semiconductor device
US20210057288A1 (en) Semiconductor device and method of fabricating the same
CN114188223A (en) Method for manufacturing fin field effect transistor
US10727133B2 (en) Method of forming gate structure with undercut region and resulting device
US8148243B2 (en) Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same
CN113644050A (en) High dielectric constant metal gate MOS transistor and manufacturing method thereof
CN112687622A (en) Single diffusion region cutting structure of fin field effect transistor and forming method thereof
US10204914B2 (en) Method for fabricating semiconductor device
US20220293475A1 (en) Method for manufacturing fin field effect transistor
JP5307971B2 (en) Manufacturing method of semiconductor device
TWI830217B (en) Semiconductor device and method of manufacturing the same
CN111477548A (en) Method for forming fin field effect transistor
US20200020589A1 (en) Method for fabricating a row of mos transistors

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination