CN115171753A - Read disturbance detection method, system, device and storage medium for phase change memory - Google Patents

Abstract

One or more embodiments of the present specification provide a read disturb detection method of a phase change memory, a memory system, an electronic device, and a storage medium. The phase change memory comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data, and the other memory page is used for storing an error correction code corresponding to the data; the method comprises the following steps: receiving a reading instruction aiming at the phase change memory, and determining a target storage page where to-be-read data indicated by the reading instruction is located; checking according to the data stored in the target storage page and an error correcting code corresponding to the data to obtain the error bit number of the target storage page; and determining whether the target storage page has read interference according to the error bit number. The embodiment can effectively reduce the storage consumption.

Description

Read disturb detection method, system, device and storage medium for phase change memory

Technical Field

One or more embodiments of the present disclosure relate to the field of storage technologies, and in particular, to a read disturb detection method for a phase change memory, a memory system, an electronic device, and a computer-readable storage medium.

Background

In recent years, in the field of nonvolatile memory, some significant progress has been made in Phase Change Memory (PCM), which brings a new opportunity for improving the memory efficiency of computer systems. Phase change memories are generally memory devices that store data using the difference in conductivity exhibited by a phase change material (e.g., a chalcogenide compound) when it is transformed between a crystalline state and an amorphous state.

However, phase change materials (e.g., chalcogenides) undergo temperature change when they are switched between crystalline and amorphous states, and the resistance of the phase change material may drift cumulatively after undergoing multiple temperature changes, thereby causing a Read Disturb (RD) phenomenon. The read disturb phenomenon in the phase change memory refers to: when the phase change memory is read, after the phase change material in the phase change memory undergoes temperature change for many times, the resistance value of the phase change material accumulates and drifts, and after a certain number of times, the information read from the storage unit in the memory is inverted, so that data errors are generated.

A read disturb detection method for a phase change memory in the related art is: a read table entry is maintained to record the number of reads to each page in the phase change memory. For example, when the number of reads for a certain memory page reaches a preset read threshold, it is determined that there is read disturb. But the manner of detection of maintenance read entries increases storage consumption.

Disclosure of Invention

In view of the above, one or more embodiments of the present disclosure provide a read disturb detection method for a phase change memory, a memory system, an electronic device, and a computer-readable storage medium.

To achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:

according to a first aspect of one or more embodiments of the present specification, a method for detecting read disturb in a phase change memory is provided, where the phase change memory includes one or more memory blocks, each memory block includes one or more memory pages, at least one memory page is used for storing data and another memory page is used for storing an error correction code corresponding to the data; the method comprises the following steps:

receiving a reading instruction aiming at the phase change memory, and determining a target storage page where to-be-read data indicated by the reading instruction is located;

checking according to the data stored in the target storage page and an error correcting code corresponding to the data to obtain the error bit number of the target storage page;

and determining whether the target storage page has reading interference according to the error bit number.

Optionally, the determining whether there is read interference in the target memory page according to the size of the error bit number includes:

if the error bit number is larger than a preset threshold value, determining that reading interference exists in the target storage page;

if the error bit number is not larger than a preset threshold value, determining that no reading interference exists in the target storage page; wherein the preset threshold is greater than 0 and less than the maximum error correctable bit number of the error correcting code.

Optionally, the preset threshold is smaller than the maximum error correctable bit number of the error correcting code and is greater than half of the maximum error correctable bit number of the error correcting code.

Optionally, the method further comprises:

under the condition that the target storage page is determined to have reading interference, returning corrected data to a processor which sends the reading instruction, and synchronously refreshing the target storage page; the refresh operation includes: and writing the corrected data back to the target storage page, wherein the corrected data is determined according to the data stored in the target storage page and the result of checking the error correction code corresponding to the data.

Optionally, after the obtaining the number of error bits of the target memory page, the method further includes:

if the number of the error bits is larger than 0, caching corrected data in a preset cache region, wherein the corrected data is determined according to the data stored in the target storage page and the result of the verification of the error correction code corresponding to the data; otherwise, caching the data stored in the target storage page in the preset cache region.

Optionally, after the determining that the target storage page of the data to be read indicated by the read instruction is located, the method further includes:

and if the preset cache region is detected to cache the data of the target storage page, reading the data of the target storage page from the preset cache region and returning the data to the processor sending the reading instruction, otherwise, reading the data stored in the target storage page and an error correction code corresponding to the data from the phase change memory and executing a verification step.

Optionally, the method is applied to a memory controller, wherein the memory controller comprises an ECC component; the checking according to the data stored in the target memory page and the error correcting code corresponding to the data to obtain the error bit number of the target memory page includes:

inputting the data read from the target memory page and the error correcting codes corresponding to the data read from other memory pages into the ECC component, so that the ECC component obtains the number of error bits of the target memory page by performing the following steps:

coding according to the data stored in the target storage page to obtain a new error correcting code; and obtaining the error bit number of the target storage page according to the difference between the new error correcting code and the error correcting code stored in the target storage page.

According to a second aspect of one or more embodiments herein, there is provided a memory system comprising a phase change memory and a memory controller;

the phase change memory comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data, and the other memory page is used for storing an error correction code corresponding to the data;

the storage controller is configured to perform the method of any of the first aspects.

According to a second aspect of one or more embodiments herein, there is provided an electronic device comprising the memory system of the third aspect and a processor;

the processor is configured to send a read instruction for a phase change memory to a memory controller in the memory system.

According to a second aspect of one or more embodiments of the present description, there is provided a computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the steps of the method according to any one of the first aspects.

The embodiment of the specification provides a read interference detection method for a phase change memory without maintaining read table entries, when each read operation occurs, checking is performed according to data stored in a target storage page and an error correction code corresponding to the data, the number of error bits of the target storage page is determined, and then whether read interference exists in the target storage page is determined according to the number of the error bits, so that the storage consumption can be effectively reduced, the mode without maintaining the read table entries has good compatibility with iteration of related firmware in the subsequent phase change memory, and the impact on entry management caused by increase of storage capacity of the phase change memory can be avoided.

Drawings

Fig. 1 is a schematic diagram of a memory structure of a phase change memory according to an exemplary embodiment.

Fig. 2 and fig. 3 are different flow charts illustrating a method for detecting read disturb in a phase change memory according to an exemplary embodiment.

Fig. 4 and 5 are schematic diagrams of different structures of a memory system according to an exemplary embodiment.

Fig. 6 is a schematic structural diagram of an electronic device according to an exemplary embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of one or more embodiments of the specification, as detailed in the claims which follow.

It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described herein. In some other embodiments, the methods may include more or fewer steps than those described herein. Moreover, a single step described in this specification may be broken down into multiple steps in other embodiments; multiple steps described in this specification may be combined into a single step in other embodiments.

A Phase-change memory (PCM) is a non-volatile memory device that generally stores data by using a difference in conductivity exhibited when a Phase-change material (e.g., chalcogenide) is transformed into a crystalline state and an amorphous state. Illustratively, phase change memory may be used in place of computer main memory, hard disks, and flash memory; of course, the method can also be applied to fixed line or wireless communication devices, consumer electronics, PCs and other embedded application devices.

Referring to fig. 1, a Phase Change Memory (PCM) may be logically divided into a plurality of memory blocks (blocks), each of which is further logically divided into addressable memory pages (pages), each of which may include one or more memory cells (cells); the storage unit is the minimum storage unit in the phase change memory, and the page is the minimum read-write unit in the phase change memory, that is, assuming that data of a certain storage unit in a certain storage page needs to be read, the content of the whole page needs to be read. In some application scenarios, one memory cell may store 1bit of data, and the read-write unit of one memory page of the phase change memory may be 32 bits.

As mentioned above, when a memory page is read for multiple times, the resistance of the phase change material may drift cumulatively due to multiple temperature changes of the phase change material, so that a read disturb phenomenon occurs, that is, after the memory page is read for multiple times, data stored in some memory cells of the memory page may be inverted.

With the development of the technology, the storage capacity of the phase change memory is gradually increased, one phase change memory may include tens of thousands of storage pages, and in the related art, a read disturb detection method for recording the number of times of reading each storage page in the phase change memory by maintaining one read table entry is used.

For the problems in the related art, embodiments of the present specification provide a read disturb detection method for a phase change memory without maintaining a read table entry, where when each read operation occurs, a check is performed according to data stored in a target storage page and an error correction code corresponding to the data to determine a number of error bits of the target storage page, and then whether the target storage page has read disturb is determined according to the number of the error bits, so that storage consumption can be effectively reduced, a manner without maintaining a read table entry also has good compatibility with respect to iteration of related firmware in a subsequent phase change memory, and impact on entry management caused by increase of storage capacity of the phase change memory can be avoided.

In some embodiments, the read disturb detection method provided by the embodiments of the present specification may be performed by a memory controller of the phase change memory. The memory controller is a device for performing necessary control on the access of the memory according to a certain timing rule, and comprises control of address signals, data signals and various command signals, so that a device accessing the memory can use memory resources on the memory according to the requirement of the device. The memory controller mainly performs interface conversion, converts commands such as read and write commands issued by a device accessing the memory into signals capable of being recognized by the memory, and also performs address decoding and data format conversion (such as data bit width) between the device accessing the memory and the memory.

In some embodiments, please refer to fig. 2, and fig. 2 is a flowchart illustrating a read disturb detection method for a phase change memory according to an embodiment of the present disclosure. The reading interference detection method is used for performing reading interference detection on the phase change memory, the phase change memory comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data, and the other memory page is used for storing an error correction code corresponding to the data. Error Checking and Correction (ECC) codes may be used to detect whether data stored in a memory is erroneous and correct the erroneous portion, thereby ensuring that the memory operates stably. The method is applicable to a storage controller, and comprises the following steps:

in step S101, a read instruction for the phase change memory is received, and a target memory page where data to be read indicated by the read instruction is located is determined.

In step S102, a check is performed according to the data stored in the target memory page and the error correction code corresponding to the data, so as to obtain the number of error bits of the target memory page.

In step S103, it is determined whether there is read interference in the target memory page according to the size of the error bit number.

The inventor finds that the more times of reading operation is performed on a certain memory page, the more bits of error in the memory page is, so that the embodiment of the present specification detects the read disturb phenomenon of the phase change memory based on the ECC error correction function, does not need to maintain the read table entry, and can effectively reduce the storage consumption and the data management difficulty. In order to ensure stable operation of the memory, most of the memory systems currently have an ECC error correction function, and when data is stored, in addition to storing the data, an error correction code corresponding to the data is also stored, so that error data can be reconstructed through the error correction code under the condition that some bits in the data are in error.

It can be understood that, in this embodiment, no limitation is imposed on a specific encoding manner of the error correction code, and the specific setting may be performed according to an actual application scenario. For example, the storage data may be encoded by using at least one of the following encoding methods to obtain an error correction code corresponding to the storage data: a hamming Code, BCH Code, or LDPC (Low Density Parity Check Code) Code, and the like.

In some embodiments, in the phase change memory, the data and the error correction code corresponding to the data are stored in different memory pages, and the memory controller is preset with storage information of the memory page in which the error correction code of the different data is located. After receiving a read instruction for the phase change memory, the memory controller firstly determines a target memory page where data to be read indicated by the read instruction is located, then reads the stored data from the target memory page, reads an error correction code corresponding to the data from other memory pages according to the storage information, and then can check according to the data stored in the target memory page and the error correction code corresponding to the data to obtain the error bit number of the target memory page. For example, a new error correction code may be encoded according to the data stored in the target memory page, and then the number of error bits of the target memory page may be obtained according to a difference between the new error correction code and the error correction code stored in the target memory page.

In some possible embodiments, an ECC component is included in the memory controller; the ECC error correction function may be implemented by an ECC component, and the memory controller may input, to the ECC component, data read from a target memory page and an error correction code corresponding to the data read from other memory pages, so that the ECC component obtains the number of error bits of the target memory page by performing the following steps: the ECC component may encode, in a same encoding manner as the error correction code, data stored in the target memory page to obtain a new error correction code, and then obtain the number of error bits of the target memory page according to a difference between the new error correction code and the error correction code stored in the target memory page. The present embodiment implements ECC error correction functionality by dedicated hardware components.

Of course, the memory controller may also be provided with an ECC correction function by software. For example, for some phase change memories without ECC error correction function, if read disturb detection is to be performed by using the method provided in the embodiment of the present specification, the ECC error correction function and the read disturb detection function provided in the embodiment of the present specification may be implemented by Over-the-Air Technology (OTA). The ECC correction function realized by software and hardware is realized by the same idea.

In some embodiments, after determining the number of error bits of the target memory page, the memory controller may determine whether there is a read disturb for the target memory page according to the size of the number of error bits. For example, a preset threshold value, which is greater than 0 and less than the maximum error correctable bit number of the error correcting code, may be preset. The memory controller may compare the error bit number with the preset threshold, and determine that the target memory page has read interference if the error bit number is greater than the preset threshold; and if the error bit number is not larger than a preset threshold value, determining that no reading interference exists in the target storage page. The embodiment detects the read interference phenomenon of the phase change memory based on the ECC function, does not need to maintain the read table entry, and can effectively reduce the storage consumption and the data management difficulty. And setting the preset threshold to be smaller than the maximum error correctable bit number of the error correcting code, that is, under the condition that the reading interference exists in the target storage page, the number of error bits in the target storage page is smaller than the maximum error correctable bit number of the error correcting code, and the error bits can still be corrected by using the error correcting code, so that the condition that data errors cannot be corrected is avoided, and the data is ensured to be accurately and safely stored.

In some embodiments, the data stored in the target memory page may be corrected according to the data stored in the target memory page and a result of checking the error correction code corresponding to the data, so as to obtain corrected data. Illustratively, the memory controller includes an ECC assembly therein; the ECC correction function may be implemented by an ECC component, and the correction process may be performed by the ECC component and output the corrected data.

Under the condition that the target storage page is determined to have reading interference, the storage controller can return corrected data to the processor which sends the reading instruction, and synchronously refresh the target storage page; the refresh operation includes: and writing the corrected data back to the target storage page. In the embodiment, the accumulated drift of the resistance value of the phase change material caused by multiple temperature changes is eliminated through the refreshing operation, so that the read interference condition of the target storage page is corrected.

In some embodiments, it is considered that a refresh operation takes a certain time period and a memory controller cannot perform a read operation on a certain memory page during the execution of the refresh operation on the memory page. When the number of error bits of the memory page does not exceed the maximum number of error-correctable bits of the error-correcting code, erroneous data can be reconstructed by the error-correcting code. Therefore, in order to reduce or avoid the problem of excessive read delay caused by frequent refresh operations, the preset threshold may be set to be less than the maximum error correctable bit number of the error correcting code and greater than half of the maximum error correctable bit number of the error correcting code. That is, in a case that the number of error bits of the target memory page stored in the target memory page is small (for example, smaller than half of the maximum error correctable bit number of the error correcting code), the memory controller may return the corrected data to a processor (for example, a processor, a CPU, or the like) that sends the read instruction, and does not perform a refresh operation on the target memory, thereby ensuring that the target memory page has high read efficiency and avoiding an excessive read delay caused by frequent refresh operations.

In some embodiments, it is considered that in a scenario of repeatedly reading the same memory page, when it is detected that the number of error bits of the memory page is greater than a preset threshold and a refresh operation needs to be performed, a next read operation for the memory page needs to wait for the refresh operation, so that a read delay is greatly increased. Therefore, for the situation of repeatedly reading the same storage page, a buffer area may be preset, the storage controller is in communication connection with the buffer area, and the preset buffer area may be used to store data of one or more storage pages read from the phase change memory; illustratively, the cache region may be a cache memory (cache). After the data stored in the target storage page is read from the phase change memory, the data of the target storage page can be cached in the preset cache region, and if the data to be read indicated by the next reading instruction is still in the target storage page, the data can be directly read from the preset cache region, so that the reading efficiency can be improved, and the situation of reading delay caused by the refreshing operation can be solved.

In a possible implementation manner, after the number of error bits of data stored in the target storage page is checked, if the number of error bits is greater than 0, caching corrected data in a preset cache region, where the corrected data is determined according to a result of checking the data stored in the target storage page and an error correction code corresponding to the data; otherwise, caching the data stored in the target storage page in the preset cache region. Illustratively, the memory controller includes an ECC component therein; the ECC correction function may be implemented by an ECC component, and the correction process may be executed by the ECC component and output corrected data, and the ECC component may also directly output if it detects that the target memory page is error-free, that is, the ECC component always outputs accurate data, and thus, the memory controller may directly buffer the data output by the ECC component into the buffer.

In an exemplary embodiment, please refer to fig. 3, and fig. 3 is a flowchart illustrating a read disturb detection method according to an embodiment of the present disclosure. The method may be performed by a storage controller, the method comprising:

in step S201, a read instruction for the phase change memory is received, and a target storage page where data to be read indicated by the read instruction is located is determined.

In step S202, detecting whether the preset cache region caches data of the target storage page; if yes, go to step S203; if not, go to step S204.

In step S203, the data of the target storage page is read from the preset cache region, and returned to the processor that sent the read instruction.

In step S204, the data stored in the target memory page and the error correction code corresponding to the data are read from the phase change memory, and the number of error bits of the target memory page is obtained by checking the data stored in the target memory page and the error correction code corresponding to the data.

In step S205, it is determined whether the error bit number is greater than a preset threshold; if yes, go to step S206, otherwise go to step S207.

In step S206, returning the corrected data to the processor that sent the read instruction, and synchronously performing a refresh operation on the target memory page; the refresh operation includes: and writing the corrected data back to the target storage page.

In step S207, the corrected data is returned to the processor that sent the read instruction.

In this embodiment, a read table entry does not need to be maintained, and with a storage page as a unit, when a read operation is performed on the phase change memory each time, the error bit number of a read target storage page is checked, and a refresh operation is performed on the target storage page under the condition that the error bit number is greater than a preset threshold, so as to ensure the accuracy of refreshed data. And aiming at the situation of repeatedly reading the same memory page, the data of the memory page of the last reading operation is recorded through a preset cache region, and if the current reading operation is also the memory page, the memory page can be directly read from the cache region, so that the problem of reading delay caused by the refreshing operation is avoided.

Accordingly, referring to fig. 4, an embodiment of the present disclosure further provides a memory system 100 including a phase change memory 10 and a memory controller 20.

The phase change memory 10 comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data and another memory page is used for storing an error correction code corresponding to the data;

the memory controller 20 is configured to receive a read instruction for the phase change memory 10, and determine a target memory page where data to be read indicated by the read instruction is located; checking according to the data stored in the target storage page and an error correcting code corresponding to the data to obtain the error bit number of the target storage page; and determining whether the target storage page has reading interference according to the error bit number.

In some embodiments, the storage controller 20 is further configured to: if the error bit number is larger than a preset threshold value, determining that reading interference exists in the target storage page; if the error bit number is not larger than a preset threshold value, determining that no reading interference exists in the target storage page; wherein the preset threshold is greater than 0 and less than the maximum error correctable bit number of the error correcting code.

Illustratively, the preset threshold is smaller than the maximum error correctable bit number of the error correcting code and larger than half of the maximum error correctable bit number of the error correcting code.

In some embodiments, the storage controller 20 is further configured to: under the condition that the target storage page is determined to have reading interference, returning corrected data to a processor which sends the reading instruction, and synchronously refreshing the target storage page; the refresh operation includes: and writing the corrected data back to the target storage page, wherein the corrected data is determined according to the data stored in the target storage page and the result of checking the error correction code corresponding to the data.

In some embodiments, referring to fig. 5, the memory system further includes a buffer 30, and the memory controller 20 is communicatively connected to the buffer, and the buffer may be a cache memory (cache) or other memory (e.g., a RAM memory). The storage controller 20 is further configured to: if the number of error bits is greater than 0, caching corrected data in a preset cache region 30, wherein the corrected data is determined according to the data stored in the target storage page and the result of checking the error correction code corresponding to the data; otherwise, the data stored in the target storage page is cached in the preset cache region 30.

In some embodiments, the storage controller 20 is further configured to: if the preset cache region 30 is detected to cache the data of the target storage page, reading the data of the target storage page from the preset cache region 30 and returning the data to the processor sending the reading instruction, otherwise, reading the data stored in the target storage page and the error correction code corresponding to the data from the phase change memory 10 and executing a checking step.

In some embodiments, referring to fig. 5, the memory controller 20 includes an ECC component 21; the memory controller 20 is further configured to input the data read from the target memory page and the error correction code corresponding to the data read from the other memory pages into the ECC component 21. The ECC component 21 is configured to encode data stored in the target memory page to obtain a new error correction code; and obtaining the error bit number of the target storage page according to the difference between the new error correcting code and the error correcting code stored in the target storage page.

In some embodiments, referring to fig. 6, an embodiment of the present specification further provides an electronic device, which includes the memory system 100 and the processor 200;

the processor 200 is configured to send a read instruction for the phase change memory to a memory controller in the memory system.

The Processor 200 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The electronic device may be a smartphone/cell phone, a tablet computer, a Personal Digital Assistant (PDA), a laptop computer, a desktop computer, a media content player, a video game station/system, a virtual reality system, an augmented reality system, a wearable device (e.g., a watch, glasses, gloves, headwear (e.g., a hat, a helmet, a virtual reality headset, an augmented reality headset, a Head Mounted Device (HMD), a headband), a pendant, an armband, a leg loop, a shoe, a vest), a remote control, or any other type of device. The device may include, but is not limited to, a processor 200, a memory system 100. Those skilled in the art will appreciate that fig. 6 is merely an example of an electronic device and is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or different components, e.g., the device may also include input-output devices, network access devices, buses, etc.

The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.

In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as a memory comprising instructions, executable by a processor of an apparatus to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

A non-transitory computer readable storage medium, instructions in the storage medium, when executed by a processor of a terminal, enable the terminal to perform the above-described method.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

In a typical configuration, a computer includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present description to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of one or more embodiments herein. The word "if," as used herein, may be interpreted as "at \8230; \8230when" or "when 8230; \823030when" or "in response to a determination," depending on the context.

The above description is only for the purpose of illustrating the preferred embodiments of the one or more embodiments of the present disclosure, and is not intended to limit the scope of the one or more embodiments of the present disclosure, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the one or more embodiments of the present disclosure should be included in the scope of the one or more embodiments of the present disclosure.

Claims (10)

1. A read disturb detection method for a phase change memory comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data, and another memory page is used for storing an error correction code corresponding to the data; the method comprises the following steps:

receiving a reading instruction aiming at the phase change memory, and determining a target storage page where to-be-read data indicated by the reading instruction is located;

checking according to the data stored in the target storage page and an error correcting code corresponding to the data to obtain the error bit number of the target storage page;

and determining whether the target storage page has reading interference according to the error bit number.

2. The method of claim 1, the determining whether there is a read disturb for the target memory page according to the size of the number of erroneous bits, comprising:

if the error bit number is larger than a preset threshold value, determining that reading interference exists in the target storage page;

if the error bit number is not larger than a preset threshold value, determining that no reading interference exists in the target storage page; wherein the preset threshold is greater than 0 and less than the maximum error correctable bit number of the error correcting code.

3. The method according to claim 2, wherein the preset threshold is smaller than the maximum number of error correctable bits of the error correcting code and larger than half the maximum number of error correctable bits of the error correcting code.

4. The method of any of claims 1 to 3, further comprising:

under the condition that the target storage page is determined to have reading interference, returning the corrected data to a processor which sends the reading instruction, and synchronously refreshing the target storage page; the refresh operation includes: and writing the corrected data back to the target storage page, wherein the corrected data is determined according to the data stored in the target storage page and the result of checking the error correction code corresponding to the data.

5. The method according to any one of claims 1 to 3, further comprising, after the obtaining the number of error bits of the target memory page:

if the number of the error bits is larger than 0, caching corrected data in a preset cache region, wherein the corrected data is determined according to the data stored in the target storage page and the result of the verification of the error correction code corresponding to the data; otherwise, caching the data stored in the target storage page in the preset cache region.

6. The method of claim 5, further comprising, after the determining a target memory page where data to be read indicated by the read instruction is located:

and if the preset cache region is detected to cache the data of the target storage page, reading the data of the target storage page from the preset cache region and returning the data to the processor sending the reading instruction, otherwise, reading the data stored in the target storage page and an error correction code corresponding to the data from the phase change memory and executing a verification step.

7. The method of claim 1, applied to a memory controller including an ECC component;

the checking according to the data stored in the target storage page and the error correction code corresponding to the data to obtain the number of error bits of the target storage page includes:

inputting the data read from the target memory page and the error correcting codes corresponding to the data read from other memory pages into the ECC component, so that the ECC component obtains the error bit number of the target memory page by executing the following steps:

coding according to the data stored in the target storage page to obtain a new error correcting code; and obtaining the error bit number of the target storage page according to the difference between the new error correcting code and the error correcting code stored in the target storage page.

8. A memory system includes a phase change memory and a memory controller;

the phase change memory comprises one or more memory blocks, each memory block comprises one or more memory pages, at least one memory page is used for storing data, and the other memory page is used for storing an error correction code corresponding to the data;

the storage controller is configured to perform the method of any of claims 1 to 7.

9. An electronic device comprising the memory system of claim 8 and a processor;

the processor is configured to send a read instruction for a phase change memory to a memory controller in the memory system.

10. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, carry out the steps of the method according to any one of claims 1 to 7.

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