CN115169278A

CN115169278A - Layout processing method, server and storage medium

Info

Publication number: CN115169278A
Application number: CN202210725175.3A
Authority: CN
Inventors: 马琨; 余匡瀛; 白黎; 陈川江
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-23
Filing date: 2022-06-23
Publication date: 2022-10-11

Abstract

The embodiment of the disclosure discloses a layout processing method, a server and a storage medium; the method comprises the following steps: receiving an initial layout and a signal to be detected provided by a user side; determining a target window in the initial layout based on the signal to be detected; determining the position information of the target window in the initial layout; and converting the initial layout into a detection layout based on the position information of the target window. The method and the device can shorten the chip development time and improve the efficiency.

Description

Layout processing method, server and storage medium

Technical Field

The disclosure relates to, but is not limited to, a layout processing method, a server, and a storage medium.

Background

During the design and development of integrated circuits, the performance of the designed chip needs to be verified. The chip often has some defects at the early stage of development, and the defect elimination needs to be carried out by partially modifying and carrying out targeted test on the chip circuit. If the layout design (layout) is modified, tape out needs to be repeated, and therefore a large cost is needed.

The FIB (Focused Ion beam) system is adopted, so that a chip designer can conduct targeted test on chip problems so as to verify a design scheme more quickly and accurately. However, FIB processing of the chip requires providing information files of the tested area, and it is difficult to efficiently provide these information files in the related art.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a layout processing method, a server, and a storage medium, which can shorten chip development time and improve efficiency.

The technical scheme of the embodiment of the disclosure is realized as follows:

the embodiment of the disclosure provides a layout processing method, which is applied to a server and comprises the following steps:

receiving an initial layout and a signal to be detected provided by a user side;

determining a target window in the initial layout based on the signal to be detected;

determining the position information of the target window in the initial layout;

and converting the initial layout into a detection layout based on the position information of the target window.

In the above solution, the determining a target window in the initial layout based on the signal to be detected includes: determining a target signal line in the initial layout based on the signal to be detected; the target signal line transmits the signal to be detected; determining the target window based on the target signal line; the target window intercepts part of the target signal line.

In the above solution, the determining the target window based on the target signal line includes: in the initial layout, moving a window to be selected along the target signal line; and if the power rail is intercepted by the window to be selected, determining the window to be selected as the target window.

In the foregoing solution, moving the window to be selected along the target signal line in the initial layout includes: and if the target signal line passes through a plurality of wiring layers in the initial layout, moving the window to be selected along the target signal line in the plurality of wiring layers according to a sequence from layer to layer.

In the above solution, moving the window to be selected along the target signal line in the initial layout includes: and if the target signal line passes through a single-layer wiring layer in the initial layout, moving the window to be selected along the target signal line in the single-layer wiring layer.

In the above solution, after moving the window to be selected along the target signal line in the initial layout, the method further includes: and if the power rail is not intercepted all the time in the window to be selected, cutting off other signal lines in a chip circuit corresponding to the initial layout so as to enable a power supply to be in the window to be selected, and determining the window to be selected as the target window.

In the foregoing solution, the determining, in the initial layout, the position information of the target window includes: determining the position information of the chip to be detected to which the target window belongs in the initial layout; and determining the position information of the target window based on the position information of the chip to be detected.

In the above scheme, determining, in the initial layout, position information of a chip to be detected to which the target window belongs includes: determining at least one corner top layer pattern of the chip to be detected in the initial layout; and determining the position information of the chip to be detected based on at least one corner top layer pattern.

In the above scheme, determining at least one corner top layer pattern of the chip to be detected in the initial layout includes: determining a boundary line of the chip to be detected; and extending the boundary line inwards for a preset distance to obtain a corner window of the chip to be detected so as to intercept at least one corner top layer pattern.

In the above scheme, the method further comprises: receiving target level information provided by a user side; the target level information corresponds to the target window; and converting the initial layout into a detection layout based on the target level information.

The embodiment of the present disclosure further provides a layout processing method, applied to a user side, including:

sending an initial layout and a signal to be detected to a server;

receiving a detection layout; the detection layout is obtained by the server determining a target window based on the initial layout and the signal to be detected and converting the initial layout based on the position information of the target window.

In the above scheme, the method further comprises: and sending target level information to a server so that the server converts the initial layout into the detection layout based on the target level information.

An embodiment of the present disclosure further provides a server, including:

the receiving unit is used for receiving the initial layout and the signal to be detected provided by the user side;

the determining unit is used for determining a target window in the initial layout based on the signal to be detected; determining the position information of the target window in the initial layout;

and the conversion unit is used for converting the initial layout into a detection layout based on the position information of the target window.

An embodiment of the present disclosure further provides a server, including:

a memory for storing executable instructions;

and the processor is used for realizing the layout processing method in the scheme when executing the executable instructions stored in the memory.

The embodiment of the disclosure also provides a storage medium, which stores executable instructions and is used for causing a processor to execute, so as to implement the layout processing method in the above scheme.

Therefore, the embodiment of the disclosure provides a layout processing method, a server and a storage medium, which can receive an initial layout and a signal to be detected provided by a user side; then, based on the signal to be detected, determining a target window in the initial layout; then, determining the position information of the target window in the initial layout; and finally, converting the initial layout into a detection layout based on the position information of the target window. Therefore, the target window needing FIB detection is determined in the initial layout, the initial layout is converted into the detection layout corresponding to the target window for FIB detection, and a foundation is provided for FIB detection, so that the chip development time is shortened, and the efficiency is improved.

Drawings

Fig. 1 is a first schematic flow chart of a layout processing method according to an embodiment of the present disclosure;

fig. 2 is a first schematic diagram illustrating an effect of a layout processing method according to an embodiment of the present disclosure;

fig. 3 is a second effect schematic diagram of a layout processing method according to the embodiment of the present disclosure;

fig. 4A is a schematic diagram illustrating an effect of the layout processing method according to the embodiment of the present disclosure;

fig. 4B is a schematic diagram illustrating an effect of the layout processing method according to the embodiment of the present disclosure;

fig. 5A is a schematic diagram illustrating an effect of a layout processing method according to an embodiment of the present disclosure;

fig. 5B is a schematic diagram six illustrating an effect of the layout processing method according to the embodiment of the present disclosure;

fig. 6 is a seventh schematic diagram illustrating an effect of the layout processing method according to the embodiment of the present disclosure;

fig. 7 is an effect schematic diagram eight of a layout processing method according to the embodiment of the present disclosure;

fig. 8 is a second flowchart illustrating a layout processing method according to an embodiment of the present disclosure;

fig. 9 is a third schematic flow chart of a layout processing method according to the embodiment of the present disclosure;

fig. 10 is a fourth schematic flowchart of a layout processing method according to the embodiment of the present disclosure;

fig. 11 is a fifth flowchart illustrating a layout processing method according to an embodiment of the present disclosure;

fig. 12 is a sixth schematic flow chart of a layout processing method according to an embodiment of the present disclosure;

fig. 13 is a seventh schematic flow chart of a layout processing method according to an embodiment of the present disclosure;

fig. 14 is an eighth schematic flow chart of a layout processing method according to the embodiment of the present disclosure;

fig. 15 is a first schematic structural diagram of a server according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a server according to a second embodiment of the present disclosure.

Detailed Description

For the purpose of making the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated with reference to the drawings and the embodiments, the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by a person of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

To the extent that similar descriptions of "first/second" appear in this patent document, the description below is added, where the terms "first \ second \ third" are used merely to distinguish between similar objects and do not denote a particular order or importance to the objects, it is to be understood that "first \ second \ third" are interchangeable under the permissive circumstances, such that the embodiments of the disclosure described herein are capable of being practiced in other sequences than illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to be limiting of the disclosure.

The FIB system focuses an Ion beam into a micro-cutting instrument with a very small size by using an electric lens, wherein the Ion beam is a Liquid Metal Ion Source (LMIS) and the Metal material is Gallium (Ga), because the Gallium element has a low melting point, a low vapor pressure, and a good oxidation resistance. Applying an electric field to the liquid-phase metal ion source to make the liquid gallium form a fine tip, applying a negative electric field (Extractor) to pull the gallium at the tip to derive a gallium ion beam, wherein the tip current density is about 1 angstrom 10 under normal operating voltage ^-8 Amp/cm ² The size of the ion beam can be determined by a series of Variable Aperture (AVA) focusing by an electric lens, and then the ion beam is focused to the surface of the test piece for the second time, so as to achieve the purpose of cutting by physical collision.

In the field of integrated circuits, FIB systems can be used to etch, deposit, implant, etc. materials and devices.

By adopting the FIB system, a chip designer can conduct targeted test on chip problems so as to verify a design scheme more quickly and accurately. If there is a problem in some area of the chip, the FIB can be used to physically modify the circuit of the chip to isolate or correct the function of the area, and the designer can directly observe the chip signal through the probe, so as to quickly find the syndrome of the problem. By adopting the FIB system, partial sample wafers and engineering wafers can be provided before the mass production of final products, and meanwhile, the number of unsuccessful design scheme modification times can be reduced by using the FIB modification chip, so that the cost consumed by reflow is reduced, and the design time is shortened.

Fig. 1 is an optional flowchart of the layout processing method provided in the embodiment of the present disclosure, and the layout processing method is applied to a server, and will be described with reference to the steps shown in fig. 1.

S101, receiving an initial layout and a signal to be detected provided by a user side.

It should be noted that the integrated circuit layout is a plane geometry description of the physical situation of the real integrated circuit, and is the result of the physical design of the bottom layer step in the integrated circuit design. In the physical design, the result of logic synthesis is converted into a physical layout file by a layout and wiring technology, and the physical layout file comprises the information of the shape, the area and the position of each hardware unit on a chip.

In the embodiment of the present disclosure, the initial layout is a physical design pattern directly used for processing and producing the integrated circuit, and here, the physical design pattern includes a wiring pattern, a device pattern, and the like. The physical design pattern on the initial layout is printed on the wafer, and devices and wiring are formed on the wafer through the process steps of photoetching, etching, diffusion, ion implantation, deposition and the like.

It should be noted that, chips often have some defects at the early stage of development, and the elimination of defects requires partial modification and targeted testing of chip circuits. In the process of eliminating the chip defect, if the layout (layout) design scheme of the chip is modified, tape out (tape out) needs to be performed again to verify whether the defect is eliminated, which requires a large cost and takes too long time. The FIB is a focused ion beam technology, and can directly physically modify the circuit of the chip, so that a designer can directly observe the chip signal through a probe, thereby reducing the cost of reflow and shortening the time spent on chip design.

However, FIB processing of the chip requires providing a layout file (usually stored in gds format) of the region corresponding to the signal to be detected. The initial layout lacks position information of each region, and the region corresponding to the signal to be detected is difficult to locate. Therefore, the initial layout cannot be directly used for FIB processing.

In the embodiment of the present disclosure, FIB processing is performed on a chip around a certain signal, and thus, the detection layout is a layout file of a region corresponding to a signal to be detected. The detection personnel need to determine the signal to be detected in advance, and then input the initial layout and the signal to be detected into the server through the user side. After the server receives the initial layout and the signal to be detected, the initial layout can be processed to obtain a detection layout corresponding to the signal to be detected.

And S102, determining a target window in the initial layout based on the signal to be detected.

In the embodiment of the present disclosure, the server may determine, based on the signal to be detected, a target window corresponding to the signal to be detected in the initial layout. The target window intercepts part of the transmission path of the signal to be detected, so that the signal to be detected can be detected within the range of the target window.

In the embodiment of the present disclosure, the server may determine a target signal line in the initial layout based on the signal to be detected provided by the user side, where the target signal line transmits the signal to be detected. Fig. 2 illustrates a partial image in an initial layout, and referring to fig. 2, a path formed by a metal signal line M1 extending along a first direction X and a metal signal line M2 extending along a second direction Y (i.e., a portion with a thickened edge in fig. 2) transmits a signal to be detected, and both the signal line M1 and the signal line M2 may be determined as a target signal line, however, the signal line M1 is located on an upper layer of the signal line M2, and therefore, a layout layer region corresponding to the signal line M1 should be preferentially used for FIB processing.

It should be noted that the chip includes a plurality of layers of physical structures, the plurality of layers of physical structures are stacked up layer by layer, and accordingly, the initial layout includes a plurality of layers of physical design patterns, and each layer of physical design pattern corresponds to one layer of physical structure in the chip. In the FIB processing process, the physical structure in the chip needs to be directly operated (for example, cut or repaired), the difficulty of operating the physical structure on the upper layer is low, and the difficulty of operating the physical structure on the lower layer is high. In this way, the FIB processing is preferentially performed in the region corresponding to the signal line M1 on the upper layer, and the degree of difficulty of the FIB processing can be reduced.

In the embodiment of the present disclosure, after determining the target signal line, the server may determine a target window based on the target signal line, where the target window intercepts part of the target signal line. The server may move the window to be selected along the target signal line in the initial layout to determine a target window that meets the FIB processing conditions. Referring to fig. 3, the server may move the candidate window W1 along the target signal line M1. That is, the candidate window W1 is moved in the second direction Y, wherein a part of the target signal line M1 should be always included in the range of the candidate window W1, that is, a part of the target signal line M1 is cut out.

In the embodiment of the disclosure, in the process of moving the window to be selected, if the target signal line passes through the plurality of wiring layers in the initial layout, the window to be selected is moved along the target signal line in the plurality of wiring layers according to a sequence of downward layer by layer so as to determine the target window. Referring to fig. 3, the target signal lines M1 and M2 belong to two adjacent upper and lower physical structures, respectively, that is, the target signal lines M1 and M2 pass through two wiring layers (a wiring layer belongs to a part of the physical structure, and the physical structure further includes devices) in the initial layout, and the target signal line M1 is on the upper layer of the target signal line M2. The server can move the window W1 to be selected along the target signal line M1 according to the sequence from layer to layer downwards, and if the window W1 to be selected meets the FIB processing condition, the window W1 to be selected at the position is determined as the target window; and if the window W1 to be selected which meets the FIB processing condition does not exist along the target signal line M1, moving the window W1 to be selected along the target signal line M2 to determine the window W1 to be selected which meets the FIB processing condition.

It can be understood that, in the case that the target signal line passes through the multiple wiring layers in the initial layout, in the multiple wiring layers, the window to be selected is moved along the target signal line in the sequence of downward layer by layer to determine the target window, so that it can be ensured that the target window for FIB processing is preferentially determined in the wiring layer relatively above, and the operation difficulty of FIB processing can be reduced.

Correspondingly, in the process of moving the window to be selected, if the target signal line passes through the single-layer wiring layer in the initial layout, the server moves the window to be selected along the target signal line in the single-layer wiring layer so as to determine the target window.

In this embodiment of the present disclosure, the server may determine whether the window to be selected meets the FIB processing condition according to whether the window to be selected intercepts a power track (power track). The power rail may provide a power path to the circuit intercepted by the candidate window so that a change in voltage or current can be detected in the FIB process to locate a defect in the circuit. Therefore, in the process that the server moves the candidate window, if the candidate window intercepts the power rail, the server can determine the current candidate window as the target window.

In addition, in the process of moving the window to be selected, if the power rail is not intercepted all the time by the window to be selected, other signal lines can be cut off in a chip circuit corresponding to the initial layout, so that a power supply passage is formed in the window to be selected, and the window to be selected is determined as a target window. After FIB processing is completed, other signal lines cut off in the chip circuit need to be reconnected and restored.

S103, determining the position information of the target window in the initial layout.

In the embodiment of the disclosure, the initial layout lacks position information of each region, and the server may determine the position information of the to-be-detected chip to which the target window belongs in the initial layout.

It should be noted that each corner position of the chip has a specific corner top layer pattern, where the corner top layer pattern refers to a pattern of a physical structure on the top layer of the chip at the corner position. Therefore, the server can determine the position information of the chip to be detected by determining at least one corner top layer pattern of the chip to be detected.

Fig. 4A and 4B illustrate corner top layer patterns of a chip. As shown in fig. 4A, the corner top layer patterns P1, P2, and P3 are respectively located at 3 corner positions of the Chip1 to be detected. The enlarged shape of the corner-top layer patterns P1, P2, and P3 is shown in fig. 4B. It can be seen that the corner top layer patterns P1, P2 and P3 are different from each other, and therefore, the position of the Chip1 to be detected in the initial layout can be located according to the corner top layer patterns P1, P2 and P3; meanwhile, the placing direction of the Chip1 to be detected may be determined according to the corner top layer patterns P1, P2, and P3, for example, the connecting line direction of the corner top layer patterns P1 and P2 is the first direction X, and the connecting line direction of the corner top layer patterns P3 and P1 is the second direction Y. Thus, the position information of the Chip1 to be detected is determined.

In the embodiment of the disclosure, the server may determine at least one corner top layer pattern of the chip to be detected in the following manner.

First, the server can determine the boundary line of the chip to be detected. Referring to fig. 5A, the Chip1 to be tested is a rectangle surrounded by 4 boundary lines (gray filling area in fig. 5A). The server may respectively extend 4 external rectangles a1 (dashed frames in fig. 5A) outward through the rectangle surrounded by the boundary lines of the Chip1 to be detected, so that the parts of the 4 external rectangles a1 connected to the Chip1 to be detected may be determined as the 4 boundary lines of the Chip1 to be detected.

And then, the server can extend the boundary line of the chip to be detected by a preset distance inwards to obtain a corner window of the chip to be detected so as to intercept at least one corner top layer pattern. Referring to fig. 5B, the server may extend the boundary line of the Chip1 to be detected by a preset distance inward to obtain 4 inscribed rectangles a2, and an intersection part of the 4 inscribed rectangles a2 is the 4 corner windows c1 of the Chip1 to be detected. Here, the preset distance extending inward from the boundary line of the Chip1 to be detected may be adjusted (for example, the preset distance is adjusted to be 100 um), so that the 4 corner windows c1 intercept at least one corner top layer pattern of the Chip1 to be detected.

In the embodiment of the disclosure, after determining the position information of the chip to be detected, the server may determine the position information of the target window based on the position information of the chip to be detected. Referring to fig. 6, the server may determine the position information of the target window W2 according to the position information of the Chip1 to be detected. Here, the position information of the target window W2 is relative to the Chip1 to be detected, that is, the server determines the relative position information of the target window W2, which represents the position of the target window W2 in the Chip1 to be detected.

In the embodiment of the present disclosure, the position information of the target window may be represented by 4 numerical values, such as 3000/3000/6000/6000, which represent distances from 4 boundary lines of the target window to corresponding 4 boundary lines of the chip to be detected.

It can be understood that, because the FIB processing uses a single chip as a detection object, the relative position information of the target window in the chip to be detected is determined, and accordingly, a detection layout only including the chip to be detected and the target window can be converted, thereby providing conditions for subsequent FIB processing.

And S104, converting the initial layout into a detection layout based on the position information of the target window.

In the embodiment of the present disclosure, after the position information of the target window is obtained, the server may convert the initial layout into the detection layout based on the position information of the target window.

As shown in fig. 7, the server may provide the user terminal with the interface shown in fig. 7, and the position information of the target window may be filled in the Clip coordinate (Clip Coord) column, for example, 3000 6000 to 3000 Clip coordinate (Clip Coord) columns. The server may generate a gds-formatted file of the detected layout according to the location information of the target window filled in the Clip coordinate (Clip Coord) column, and store the gds-formatted file of the detected layout to the formulated path.

It should be noted that the interface shown in fig. 7 also includes other information. The Process (Process) column represents a Process type adopted by the chip to be detected, the Run path (Run Dir) column represents a processing script and a File storage path of the detection layout, the GDS File (GDS File) column represents a File storage path and a File name of the initial layout, the inside-extending distance (Comer Size) column represents a preset distance for determining a corner Top Layer pattern to extend the boundary line of the chip to be detected inwards, the Top Layer (Top Layer) column represents a physical structure Layer at the Top Layer of the chip to be detected, and the shear Layer (Clip Layer) column represents target level information corresponding to the detection layout to be generated.

In the embodiment of the present disclosure, the server may process the position information of the multiple target windows at the same time, and convert the initial layout into the detection layouts corresponding to the multiple target windows respectively. Referring to fig. 7, the position information of a plurality of target windows may be filled in the column of Clip coordinates (Clip Coord) at the same time, and the position information of different target windows may be filled in the column of Clip coordinates (Clip Coord) at the interval of semicolons, for example, the position information of the target Window Cut Window1 is 500 1000, and the position information of the target Window Cut Window2 is 3000 6000, and then 500 1000 may be filled in the column of Clip coordinates (Clip Coord); 3000 3000 6000 6000.

In the embodiment of the present disclosure, the server may further receive target level information corresponding to the target window from the user side, so that the initial layout is converted into the detection layout based on the target level information. Therein, referring to fig. 7, the target level information is filled in the shear bar.

It can be understood that, in the embodiment of the present disclosure, a target window that needs FIB detection is determined in the initial layout, and the initial layout is converted into a detection layout corresponding to the target window for FIB detection, so as to provide a basis for FIB detection, thereby shortening chip development time and improving efficiency.

In some embodiments of the present disclosure, S102 shown in fig. 1 may be implemented by S201 to S202 shown in fig. 8, which will be described in conjunction with the steps.

S201, determining a target signal line in an initial layout based on a signal to be detected; the target signal line transmits a signal to be detected.

In the embodiment of the disclosure, the server may determine a target signal line in the initial layout based on the signal to be detected, where the target signal line transmits the signal to be detected. Referring to fig. 2, a path formed by a signal line M1 extending in the first direction X and a signal line M2 (i.e., a portion with a thick edge in fig. 2) extending in the second direction Y transmits a signal to be detected, and both the signal line M1 and the signal line M2 can be determined as a target signal line, however, the signal line M1 is located at an upper layer of the signal line M2, and thus, an area corresponding to the signal line M1 should be used for FIB processing more preferentially.

In the FIB processing process, the operation difficulty of the upper physical structure is low, and the operation difficulty of the lower physical structure is high. In this way, the FIB processing is preferentially performed in the region corresponding to the signal line M1 on the upper layer, and the degree of difficulty of the FIB processing can be reduced.

S202, determining a target window based on a target signal line; the target window intercepts a portion of the target signal line.

In the embodiment of the present disclosure, after determining the target signal line, the server may determine a target window based on the target signal line, where the target window intercepts a part of the target signal line.

In some embodiments of the present disclosure, S202 shown in fig. 8 may be implemented by S203 to S204 shown in fig. 9, which will be described in conjunction with the steps.

And S203, moving the window to be selected along the target signal line in the initial layout.

In the embodiment of the present disclosure, the server may move the window to be selected along the target signal line in the initial layout, so as to determine the target window meeting the FIB processing condition. Referring to fig. 3, the server may move the candidate window W1 along the target signal line M1. That is, the candidate window W1 is moved in the second direction Y, wherein a part of the target signal line M1 should be always included in the range of the candidate window W1, that is, a part of the target signal line M1 is cut out.

And S204, if the power rail is intercepted by the window to be selected, determining the window to be selected as a target window.

In the embodiment of the present disclosure, the server may determine whether the window to be selected meets FIB processing conditions according to whether the window to be selected intercepts a power rail (power track). The power rail may provide a power path to the circuit intercepted by the candidate window so that a change in voltage or current can be detected in the FIB process to locate a defect in the circuit. Therefore, in the process that the server moves the candidate window, if the candidate window intercepts the power rail, the server can determine the current candidate window as the target window.

In some embodiments of the present disclosure, S203 shown in fig. 9 may be implemented by S205 shown in fig. 10, which will be described in conjunction with various steps.

S205, if the target signal line passes through the multiple wiring layers in the initial layout, moving the window to be selected along the target signal line in the multiple wiring layers according to the sequence of downward layer by layer.

In the embodiment of the disclosure, in the process of moving the window to be selected, if the target signal line passes through the plurality of wiring layers in the initial layout, the window to be selected is moved along the target signal line in the plurality of wiring layers according to a sequence of downward layer by layer so as to determine the target window. Referring to fig. 3, the target signal lines M1 and M2 belong to two adjacent upper and lower physical structures, respectively, that is, the target signal lines M1 and M2 pass through two wiring layers (a wiring layer belongs to a part of the physical structure, and the physical structure further includes devices) in the initial layout, and the target signal line M1 is on the upper layer of the target signal line M2. The server can move the window W1 to be selected along the target signal line M1 in a downward sequence layer by layer; and if the window W1 to be selected which meets the FIB processing condition does not exist along the target signal line M1, moving the window W1 to be selected along the target signal line M2.

It can be understood that, in the case where the target signal line passes through the plurality of wiring layers in the initial layout, in the plurality of wiring layers, the window to be selected is moved along the target signal line in the sequence of layer-by-layer downward to determine the target window, so that it can be ensured that the target window for FIB processing is preferentially determined in the wiring layer on the upper layer, and the operation difficulty of FIB processing can be reduced

In some embodiments of the present disclosure, S203 illustrated in fig. 9 may be implemented by S206 illustrated in fig. 10, which will be described in conjunction with the steps.

And S206, if the target signal line passes through the single-layer wiring layer in the initial layout, moving the window to be selected along the target signal line in the single-layer wiring layer.

In the embodiment of the disclosure, in the process of moving the window to be selected, if the target signal line passes through a single-layer wiring layer in the initial layout, the server moves the window to be selected along the target signal line in the single-layer wiring layer to determine the target window.

In some embodiments of the present disclosure, after S203 is shown in fig. 9, the layout processing method further includes S207, which will be described with reference to the steps.

And S207, if the power rail is not intercepted all the time in the window to be selected, cutting off other signal lines in a chip circuit corresponding to the initial layout, so that a power supply passage is arranged in the window to be selected, and determining the window to be selected as a target window.

In the embodiment of the disclosure, in the process of moving the window to be selected, if the power rail is not intercepted all the time by the window to be selected, other signal lines may be cut off in the chip circuit corresponding to the initial layout, so that a power supply path exists in the window to be selected, and the window to be selected is determined as the target window. After FIB processing is completed, other signal lines cut off in the chip circuit need to be reconnected and restored to the original state.

In some embodiments of the present disclosure, S103 shown in fig. 1 may be implemented by S301 to S302 shown in fig. 11, which will be described in conjunction with the respective steps.

S301, determining the position information of the chip to be detected to which the target window belongs in the initial layout.

In the embodiment of the disclosure, the initial layout lacks position information of each region, and the server may determine the position information of the chip to be detected to which the target window belongs in the initial layout.

S302, determining the position information of the target window based on the position information of the chip to be detected.

In the embodiment of the present disclosure, the position information of the target window may be represented by 4 values, such as 3000/3000/6000/6000, which represent distances from 4 boundary lines of the target window to 4 boundary lines of the chip to be detected.

It can be understood that, because the FIB processing uses a single chip as a detection object, the relative position information of the target window in the chip to be detected is determined, and a detection layout only including the chip to be detected and the target window can be converted accordingly, thereby providing conditions for subsequent FIB processing.

In some embodiments of the present disclosure, S301 illustrated in fig. 11 may be implemented by S303 to S304 illustrated in fig. 12, which will be described in conjunction with the respective steps.

S303, determining at least one corner top layer pattern of the chip to be detected in the initial layout.

In the embodiment of the disclosure, the server may first determine at least one corner top layer pattern of the chip to be detected.

S304, determining the position information of the chip to be detected based on at least one corner top layer pattern.

In the embodiment of the disclosure, after the server determines at least one corner top layer pattern of the chip to be detected, the server may determine the position information of the chip to be detected based on the at least one corner top layer pattern. As shown in fig. 4A, the corner top layer patterns P1, P2, and P3 are respectively located at 3 corner positions of the Chip1 to be detected. The enlarged shape of the corner-top layer patterns P1, P2, and P3 is shown in fig. 4B. It can be seen that the corner top layer patterns P1, P2 and P3 are different from each other, so that the position of the Chip1 to be detected in the initial layout can be located according to the corner top layer patterns P1, P2 and P3; meanwhile, the placing direction of the Chip1 to be detected may be determined according to the corner top layer patterns P1, P2, and P3, for example, a connection line direction of the corner top layer patterns P1 and P2 is a first direction X, and a connection line direction of the corner top layer patterns P3 and P1 is a second direction Y. Thus, the position information of the Chip1 to be detected is determined.

In some embodiments of the present disclosure, S303 shown in fig. 12 may be implemented by S305 to S306 shown in fig. 13, which will be described in conjunction with the respective steps.

S305, determining the boundary line of the chip to be detected.

In the embodiment of the disclosure, the server may determine the boundary line of the chip to be detected first. Referring to fig. 5A, the Chip1 to be tested is a rectangle surrounded by 4 boundary lines (gray filling area in fig. 5A). The server may respectively extend 4 external rectangles a1 (dashed frames in fig. 5A) outward through the rectangle surrounded by the boundary lines of the Chip1 to be detected, so that the parts of the 4 external rectangles a1 connected to the Chip1 to be detected may be determined as the 4 boundary lines of the Chip1 to be detected.

S306, extending the boundary line inwards for a preset distance to obtain a corner window of the chip to be detected so as to intercept at least one corner top layer pattern.

In the embodiment of the disclosure, after the server determines the boundary line of the chip to be detected, the server may extend the boundary line of the chip to be detected by a preset distance inward to obtain a corner window of the chip to be detected, so as to intercept at least one corner top layer pattern. Referring to fig. 5B, the server may extend the boundary line of the Chip1 to be detected by a preset distance inward to obtain 4 inscribed rectangles a2, and an intersection part of the 4 inscribed rectangles a2 is the 4 corner windows c1 of the Chip1 to be detected. Here, a preset distance extending inward from the boundary line of the Chip1 to be detected may be adjusted (e.g., the preset distance is adjusted to be 100 um) so that the 4 corner windows c1 intercept at least one corner top layer pattern of the Chip1 to be detected.

In some embodiments of the present disclosure, the layout processing method illustrated in fig. 1 further includes steps S105 to S106, which will be described in conjunction with the above steps.

S105, receiving target level information provided by a user side; the target level information corresponds to a target window.

In an embodiment of the present disclosure, a server may receive target level information corresponding to a target window from a user side. Referring to fig. 7, target level information may be filled into a clipboard for transmission to a server.

And S106, converting the initial layout into a detection layout based on the target level information.

In the embodiment of the present disclosure, the server may convert the layer corresponding to the initial layout based on the received target level information, so as to obtain the detection layout including the position information of the target window.

The embodiment of the present disclosure also provides a layout processing method, which is applied to a user side, and includes S401 to S402 shown in fig. 14, and the description will be made with reference to each step.

S401, sending the initial layout and the signal to be detected to a server.

In the embodiment of the disclosure, the layout processing client may send the initial layout stored locally and the to-be-detected signal corresponding to the FIB processing to the server. Referring to fig. 7, the layout processing client may fill in a local storage path of the initial layout in the operation path bar, and fill in other related information of the initial layout, so as to send the information to the server.

S402, receiving a detection layout; the detection layout is obtained by determining a target window based on an initial layout and a signal to be detected and converting the initial layout based on the position information of the target window by the server.

In the embodiment of the disclosure, the layout processing client may receive the detection layout converted from the initial layout from the server. Referring to fig. 7, the layout processing client may fill a storage path in the GDS file column, so as to store the received detection layout locally.

In some embodiments of the present disclosure, the layout processing method shown in fig. 14 further includes S403, which will be described with reference to each step.

And S403, sending the target level information to the server so that the server converts the initial layout into the detection layout based on the target level information.

In the embodiment of the present disclosure, the user side may send target level information corresponding to the target window to the server, so that the server converts the initial layout into the detection layout based on the target level information. Referring to fig. 7, target level information may be filled into a clipboard for transmission to a server.

Fig. 15 is an alternative structural schematic diagram of a server according to an embodiment of the present disclosure. As shown in fig. 15, an embodiment of the present disclosure further provides a server 800, including: a receiving unit 804, a determining unit 805, and a converting unit 806, wherein:

a receiving unit 804, configured to receive the initial layout and the signal to be detected;

a determining unit 805, configured to determine a target window in the initial layout based on the signal to be detected; determining the position information of the target window in the initial layout;

and a converting unit 806, configured to convert the initial layout into the detected layout based on the position information of the target window.

In some embodiments of the present disclosure, the determining unit 805 is further configured to determine a target signal line in the initial layout based on the signal to be detected; the target signal line transmits a signal to be detected; determining a target window based on the target signal line; the target window intercepts part of the target signal line.

In some embodiments of the present disclosure, the determining unit 805 is further configured to move the window to be selected along the target signal line in the initial layout; and if the power rail is intercepted by the window to be selected, determining the window to be selected as a target window.

In some embodiments of the present disclosure, the determining unit 805 is further configured to, if the target signal line passes through multiple wiring layers in the initial layout, move the window to be selected along the target signal line in the multiple wiring layers in a layer-by-layer downward order.

In some embodiments of the present disclosure, the determining unit 805 is further configured to move the candidate window along the target signal line in a single-layer wiring layer in the initial layout if the target signal line passes through the single-layer wiring layer in the initial layout.

In some embodiments of the present disclosure, the determining unit 805 is further configured to, if the power rail is not intercepted all the time in the window to be selected, cut off other signal lines in the chip circuit corresponding to the initial layout, so that a power supply path exists in the window to be selected, and determine the window to be selected as the target window.

In some embodiments of the present disclosure, the determining unit 805 is further configured to determine, in the initial layout, position information of a chip to be detected to which the target window belongs; and determining the position information of the target window based on the position information of the chip to be detected.

In some embodiments of the present disclosure, the determining unit 805 is further configured to determine at least one corner top layer pattern of the chip to be detected in the initial layout; and determining the position information of the chip to be detected based on at least one corner top layer pattern.

In some embodiments of the present disclosure, the determining unit 805 is further configured to determine a boundary line of the chip to be detected; and extending the boundary line inwards for a preset distance to obtain a corner window of the chip to be detected so as to intercept at least one corner top layer pattern.

It should be noted that fig. 16 is an optional schematic structural diagram of the server provided in the embodiment of the present disclosure, and as shown in fig. 16, the hardware entities of the server 800 include: a processor 801, a communication interface 802, and a memory 803, wherein:

the processor 801 generally controls the overall operation of the server 800.

The communication interface 802 may enable the server 800 to communicate with other devices or apparatuses via a network.

The Memory 803 is configured to store instructions and applications executable by the processor 801, and may also buffer data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or already processed by the respective modules in the processor 801 and the server 800, and may be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM).

It should be noted that, in the embodiment of the present disclosure, if the method for executing the timing task is implemented in the form of a software functional module, and is sold or used as a standalone product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a server 800 (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware and software.

Correspondingly, the embodiment of the disclosure provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps in the method corresponding to the server described above.

Here, it should be noted that: the above description of the storage medium and device embodiments is similar to the description of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the storage medium and apparatus of the present disclosure, reference is made to the description of the embodiments of the method of the present disclosure.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all the functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A layout processing method is applied to a server, and the method comprises the following steps:

2. The layout processing method according to claim 1, wherein the determining a target window in the initial layout based on the signal to be detected comprises:

determining a target signal line in the initial layout based on the signal to be detected; the target signal line transmits the signal to be detected;

determining the target window based on the target signal line; the target window intercepts part of the target signal line.

3. The layout processing method according to claim 2, wherein the determining the target window based on the target signal line includes:

in the initial layout, moving a window to be selected along the target signal line;

and if the power rail is intercepted by the window to be selected, determining the window to be selected as the target window.

4. The layout processing method according to claim 3, wherein moving the window to be selected along the target signal line in the initial layout comprises:

and if the target signal line passes through a plurality of wiring layers in the initial layout, moving the window to be selected along the target signal line in the plurality of wiring layers according to a downward sequence layer by layer.

5. The layout processing method according to claim 3, wherein moving the window to be selected along the target signal line in the initial layout comprises:

and if the target signal line passes through a single-layer wiring layer in the initial layout, moving the window to be selected along the target signal line in the single-layer wiring layer.

6. The layout processing method according to claim 3, wherein after moving a window to be selected along the target signal line in the initial layout, the method further comprises:

if the power rail is not intercepted all the time in the window to be selected, other signal lines are cut off in a chip circuit corresponding to the initial layout, so that a power supply passage is arranged in the window to be selected, and the window to be selected is determined as the target window.

7. The layout processing method according to claim 1, wherein the determining the position information of the target window in the initial layout comprises:

determining the position information of the chip to be detected to which the target window belongs in the initial layout;

and determining the position information of the target window based on the position information of the chip to be detected.

8. The layout processing method according to claim 7, wherein the determining the position information of the chip to be detected to which the target window belongs in the initial layout comprises:

determining at least one corner top layer pattern of the chip to be detected in the initial layout;

and determining the position information of the chip to be detected based on at least one corner top layer pattern.

9. The layout processing method according to claim 8, wherein the determining at least one corner top layer pattern of the chip to be detected in the initial layout comprises:

determining a boundary line of the chip to be detected;

and extending the boundary line inwards for a preset distance to obtain a corner window of the chip to be detected so as to intercept at least one corner top layer pattern.

10. The layout processing method according to claim 1, characterized in that the method further comprises:

receiving target level information provided by a user side; the target level information corresponds to the target window;

and converting the initial layout into a detection layout based on the target level information.

11. A layout processing method is characterized by being applied to a user side, and comprises the following steps:

sending an initial layout and a signal to be detected to a server;

12. The layout processing method according to claim 11, wherein the method further comprises:

and sending target level information to a server so that the server converts the initial layout into the detection layout based on the target level information.

13. A server, comprising:

14. A server, comprising:

a memory for storing executable instructions;

a processor for performing the method of any one of claims 1 to 10 when executing executable instructions stored in the memory.

15. A storage medium having stored thereon executable instructions for causing a processor to perform the method of any one of claims 1 to 10 when executed.