CN115167232B - double-MOS load protection alarm circuit - Google Patents
double-MOS load protection alarm circuit Download PDFInfo
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- CN115167232B CN115167232B CN202210895501.5A CN202210895501A CN115167232B CN 115167232 B CN115167232 B CN 115167232B CN 202210895501 A CN202210895501 A CN 202210895501A CN 115167232 B CN115167232 B CN 115167232B
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000001514 detection method Methods 0.000 claims description 34
- 230000009977 dual effect Effects 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000011389 fruit/vegetable juice Nutrition 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention provides a double-MOS load protection alarm circuit which is characterized by comprising an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor); the load power supply, the load, the PMOS and the NMOS are sequentially connected in series, and the NMOS and the PMOS are controlled by different levels of different control ends of the MCU singlechip. The invention can accurately detect the product faults, and prevents the risk and hidden trouble in the aspect of safety to users under the non-working state of the load by triple protection alarm.
Description
Technical Field
The present invention relates to a load protection alarm circuit, and more particularly, to a double MOS load protection alarm circuit suitable for home appliances.
Background
At present, household appliances (handheld juice cups, intelligent bowls, electric rice cookers and the like) are provided with a load which is a resistive heating load or an inductive rotating load, and the load is controlled to be turned on or off through a triode or an MOS tube. Under normal conditions, the load of the household appliance products is controlled by only one triode or MOS tube, if the triode or MOS tube is invalid or damaged, the triode or MOS tube is always conducted and is not controlled, and the load always works, so that potential safety hazards and risks can be generated.
Disclosure of Invention
The invention aims to overcome the defects of the prior art in controlling the load of household appliances, and provides a double-MOS load protection alarm circuit.
The invention solves the technical problems through the following technical scheme:
the double-MOS load protection alarm circuit comprises an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor);
the load power supply, the load, the PMOS and the NMOS are sequentially connected in series, and the NMOS and the PMOS are controlled by different levels of different control ends of the MCU singlechip.
Preferably, the PMOS is turned on when the first control end of the MCU singlechip is at a low level, the NMOS is turned on when the second control end of the MCU singlechip is at a high level, and the load is turned on when the NMOS and the PMOS are turned on simultaneously.
Preferably, the load control circuit further comprises a first resistor and a third resistor;
the grid electrode of the PMOS is connected with the first control end through a sixth resistor and is also connected with VCC through the first resistor;
and the grid electrode of the NMOS is connected with the second control end through a seventh resistor, and is also connected with the source electrode of the NMOS through the third resistor.
Preferably, the MCU singlechip also detects whether the NMOS fails to be conducted or not and whether the PMOS fails to be conducted or not in the non-working state of the load through a level detection end.
Preferably, the load control circuit further includes a fifth resistor, a drain of the PMOS is connected to a drain of the NMOS, and a source of the NMOS is grounded through the fifth resistor;
the drain electrode of the PMOS is connected with the level detection end through an eighth resistor and is also connected with the detection control end of the MCU singlechip through a ninth resistor, and the detection control end is set to output high level, output low level or input.
Preferably, the MCU singlechip also detects whether the load is conducted or not through a voltage detection end.
Preferably, the load control circuit further includes a fourth resistor, wherein the non-grounded end of the fifth resistor is connected to the voltage detection end through the fourth resistor, and the voltage detection end is grounded through a capacitor.
Preferably, the third control end of the MCU singlechip is connected with the alarm through a tenth resistor.
Preferably, the third control end controls the alarm to send out an alarm when any one of the following conditions occurs:
under the non-working state of the load, the NMOS fails to be conducted;
under the non-working state of the load, the PMOS fails to be conducted;
and in the non-working state of the load, the voltage detection end of the MCU singlechip detects voltage.
Preferably, the load is a resistive heating load or an inductive rotating load.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that: the NMOS and the PMOS are connected in series and controlled by different levels of different control ends; for the NMOS and the PMOS which are connected in series, level detection is added to detect whether the NMOS and the PMOS are in failure conduction or not; for a load, voltage detection is increased to detect whether the load is on. The invention can accurately detect the product faults, and prevents the risk and hidden trouble in the aspect of safety to users under the non-working state of the load by triple protection alarm.
Drawings
Fig. 1 is a circuit diagram of a dual MOS load protection alarm circuit according to embodiment 1 of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments are shown.
Example 1
Fig. 1 shows a load protection alarm circuit of a dual MOS of the present embodiment. The load protection alarm circuit comprises an MCU singlechip U1 and a load control circuit, wherein the load control circuit comprises a load power supply VLOAD, a load L1, an NMOS Q1 and a PMOS Q2; the load power supply VLOAD, the load L1, the PMOS Q2 and the NMOS Q1 are sequentially connected in series, and the NMOS Q1 and the PMOS Q2 are controlled by different levels of different control ends of the MCU singlechip U1.
The control end can be an I/O port of the MCU singlechip U1. The load L1 may be a resistive heating load or an inductive rotating load.
In an optional implementation manner, the PMOS Q2 is turned on when the first control end of the MCU single chip microcomputer U1 is at a low level, the NMOS Q1 is turned on when the second control end of the MCU single chip microcomputer U1 is at a high level, and the load L1 is turned on when the NMOS Q1 and the PMOS Q2 are turned on simultaneously. The first control end and the second control end may be different I/O ports, for example, 3 pins and 4 pins of the MCU single-chip microcomputer U1, respectively.
Further, the load control circuit further comprises a first resistor R1 and a third resistor R3; the grid electrode of the PMOS Q2 is connected with the first control end through a sixth resistor R6 and is also connected with VCC through the first resistor R1; the grid electrode of the NMOS Q1 is connected with the second control end through a seventh resistor R7, and is also connected with the source electrode of the NMOS Q1 through a third resistor R3.
In this embodiment, the NMOS Q1 and the PMOS Q2 are connected in series, and the NMOS Q1 and the PMOS Q2 are controlled by different levels of different control terminals: the NMOS Q1 is connected with the PMOS Q2 in series, one MOS tube fails to be conducted, the other MOS tube can control the load L1 to be switched on, the NMOS Q1 and the PMOS Q2 are respectively controlled by two different levels of different control ends, and if the MCU is dead or out of control (for example, the levels of the two control ends are the same), the load L1 cannot be conducted.
In an optional implementation manner, the MCU single chip microcomputer U1 further detects, through a level detection terminal, whether the NMOS Q1 fails to be turned on or not and whether the PMOS Q2 fails to be turned on or not in the non-working state of the load L1. The level detection end may be another I/O port, for example, 5 pins of the MCU single chip microcomputer U1.
Further, the load control circuit further includes a fifth resistor R5, a drain of the PMOS Q2 is connected to a drain of the NMOS Q1, and a source of the NMOS Q1 is grounded through the fifth resistor R5; the drain electrode of the PMOS Q2 is connected with the level detection end through an eighth resistor R8 and is also connected with the detection control end of the MCU singlechip U1 through a ninth resistor R9, and the detection control end is set to output high level, output low level or input.
The fifth resistor R5 may be a resistor with a high precision and a small resistance value. The detection control end can be another I/O port, for example, 6 pins of the MCU singlechip U1.
In this embodiment, if the NMOS Q1 fails to turn on, the level detection terminal detects a low level, and if the PMOS Q2 fails to turn on, the level detection terminal detects a high level.
In an optional implementation manner, the MCU single chip microcomputer U1 further detects whether the load L1 is turned on or not through a voltage detection end. The voltage detection end can be an A/D port, for example, 7 pins of the MCU singlechip U1.
Further, the load control circuit further includes a fourth resistor R4, the non-grounded end of the fifth resistor R5 is connected to the voltage detection end through the fourth resistor R4, and the voltage detection end is further grounded to GND through a capacitor C5.
In this embodiment, by detecting whether the voltage detection terminal has a voltage, it can be determined whether the load L1 is turned on.
In an optional implementation manner, the third control end of the MCU singlechip U1 is connected with the alarm B1 through a tenth resistor R10. The third control end may be another I/O port, for example, 8 pins of the MCU single chip microcomputer U1.
Further, the third control end controls the alarm to send out an alarm when any one of the following conditions occurs:
under the non-working state of the load L1, the NMOS Q1 is in failure conduction;
under the non-working state of the load L1, the PMOS Q2 is in failure conduction;
and in the non-working state of the load L1, the voltage detection end of the MCU singlechip U1 detects voltage.
Wherein, the alarm B1 may be an acousto-optic device. One end of the acousto-optic device is connected with VCC, and the other end of the acousto-optic device is connected with the third control end through the tenth resistor.
In this embodiment, the circuit has triple protection alarm, and under the non-operating condition, the load L1 can be more effectively avoided from working out of control, and the risk and hidden danger in the aspect of safety to the user are prevented.
The principle of a load protection alarm circuit of a dual MOS of the present embodiment is described in detail below with reference to fig. 1:
1. when driver_p is at a low level, the grid electrode of the PMOS Q2 is at a low level, and the PMOS Q2 is conducted; when driver_n is at a high level, the gate of the NMOS Q1 is at a high level, and the NMOS Q1 is turned on, so that the load L1 is turned on. When any one of the NMOS Q1 or the PMOS Q2 fails to be conducted, the other MOS tube can control the load L1 to be switched on and off. When driver_p is at low level and driver_n is at high level, the load L1 is conducted, and if the MCU singlechip U1 is dead or out of control to enable the levels of two IO ports of the 3-pin and the 4-pin to be the same, the load L1 is not conducted.
2. In the non-working state of the load L1, if the NMOS Q1 fails to be turned on, the 5 pin of the MCU singlechip U1 detects the short_chk level, and at this time, the short_chk port sets a pull-up resistor (such as a pull-up resistor connected to the outside of the drawing or a pull-up resistor in the chip pin), that is, in the drawing, the 6 pin of the MCU singlechip U1 outputs a high level, vshort_chk= (r5/(r5+r9)) is VLOAD, and because the resistor R5> R9, vshort_chk is a low level. And when the 5 pins of the MCU singlechip U1 do not detect the short_chk level, no pull-up resistor is arranged, namely the 6 pins are used as input.
In the non-working state of the load L1, if the PMOS Q2 fails to be turned on, the 5 pin of the MCU singlechip U1 detects the short_chk level, and at this time, the short_chk port sets a pull-down resistor (such as a pull-down resistor externally connected to a drawing or a pull-down resistor in a chip pin), that is, in the drawing, the 6 pin of the MCU singlechip U1 outputs a low level, vshort_chk= (r9/(lr1+r9)) =vload, and because the load resistor LR1> > R9, vshort_chk is a high level. And when the 5 pins of the MCU singlechip U1 do not detect the short_chk level, no pull-down resistor is arranged, namely 6 pins are used as input. At this time, the user is alerted to the product failure by the audible and visual annunciator B1.
3. If the load L1 is on, vsense= (R5/(r5+lr1)) ×vload, so that it can be determined whether the load L1 is on by detecting the voltage value of Vsense. If the voltage is detected at the load L1 in the non-working state, the audible and visual device B1 alarms the user of the product failure.
In the embodiment, the NMOS and the PMOS are connected in series and controlled by different levels of different control ends; for the NMOS and the PMOS which are connected in series, level detection is added to detect whether the NMOS and the PMOS are in failure conduction or not; for a load, voltage detection is increased to detect whether the load is on. According to the embodiment, the product faults can be accurately detected, and risks and hidden dangers in safety caused to users under the load non-working state are prevented through triple protection alarms.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (5)
1. The double-MOS load protection alarm circuit is characterized by comprising an MCU (micro control unit) singlechip and a load control circuit, wherein the load control circuit comprises a load power supply, a load, an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor);
the load power supply, the load, the PMOS and the NMOS are sequentially connected in series, and the NMOS and the PMOS are controlled by different levels of different control ends of the MCU singlechip;
the MCU singlechip also detects whether the NMOS fails to be conducted or not and whether the PMOS fails to be conducted or not under the non-working state of the load through a level detection end;
the load control circuit further comprises a fifth resistor, the drain electrode of the PMOS is connected with the drain electrode of the NMOS, and the source electrode of the NMOS is grounded through the fifth resistor;
the drain electrode of the PMOS is connected with the level detection end through an eighth resistor and is also connected with the detection control end of the MCU singlechip through a ninth resistor, and the detection control end is set to output high level, output low level or input;
the MCU singlechip also detects whether the load is conducted or not through a voltage detection end;
the load control circuit further comprises a fourth resistor, wherein the non-grounding end of the fifth resistor is connected with the voltage detection end through the fourth resistor, and the voltage detection end is grounded through a capacitor;
the PMOS is conducted when the first control end of the MCU singlechip is at a low level, the NMOS is conducted when the second control end of the MCU singlechip is at a high level, and the load is conducted when the NMOS and the PMOS are conducted simultaneously.
2. The dual MOS load protection alarm circuit of claim 1, wherein the load control circuit further comprises a first resistor and a third resistor;
the grid electrode of the PMOS is connected with the first control end through a sixth resistor and is also connected with VCC through the first resistor;
and the grid electrode of the NMOS is connected with the second control end through a seventh resistor, and is also connected with the source electrode of the NMOS through the third resistor.
3. The dual MOS load protection alarm circuit of claim 1 wherein the third control terminal of the MCU singlechip is connected to the alarm through a tenth resistor.
4. A dual MOS load protection alarm circuit according to claim 3, wherein said third control terminal controls said alarm to sound an alarm when any one of the following occurs:
under the non-working state of the load, the NMOS fails to be conducted;
under the non-working state of the load, the PMOS fails to be conducted;
and in the non-working state of the load, the voltage detection end of the MCU singlechip detects voltage.
5. The dual MOS load protection alarm circuit of claim 1 wherein the load is a resistive heating load or an inductive rotating load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210895501.5A CN115167232B (en) | 2022-07-27 | 2022-07-27 | double-MOS load protection alarm circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210895501.5A CN115167232B (en) | 2022-07-27 | 2022-07-27 | double-MOS load protection alarm circuit |
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| Publication Number | Publication Date |
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| CN115167232A CN115167232A (en) | 2022-10-11 |
| CN115167232B true CN115167232B (en) | 2023-10-31 |
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| CN202210895501.5A Active CN115167232B (en) | 2022-07-27 | 2022-07-27 | double-MOS load protection alarm circuit |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4132865A (en) * | 1976-10-01 | 1979-01-02 | International Standard Electric Corporation | Electronic switch |
| CN211630111U (en) * | 2020-02-24 | 2020-10-02 | 九阳股份有限公司 | Food processing machine with multiple semiconductor switches and motor |
| CN112491027A (en) * | 2020-12-07 | 2021-03-12 | 佛山市顺德区美的电子科技有限公司 | Direct-current power supply error-proofing control circuit and method and household appliance |
| CN112701663A (en) * | 2020-12-25 | 2021-04-23 | 上海东软载波微电子有限公司 | Overcurrent detection and protection circuit for power MOS (metal oxide semiconductor) tube and power MOS tube assembly |
| CN214153992U (en) * | 2020-12-15 | 2021-09-07 | 自贡兴川光电有限公司 | Control circuit for realizing load switch control and detection protection of single-chip microcomputer IO port |
| CN216625708U (en) * | 2021-08-05 | 2022-05-27 | 博泰车联网科技(上海)股份有限公司 | Load switch circuit |
-
2022
- 2022-07-27 CN CN202210895501.5A patent/CN115167232B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4132865A (en) * | 1976-10-01 | 1979-01-02 | International Standard Electric Corporation | Electronic switch |
| CN211630111U (en) * | 2020-02-24 | 2020-10-02 | 九阳股份有限公司 | Food processing machine with multiple semiconductor switches and motor |
| CN112491027A (en) * | 2020-12-07 | 2021-03-12 | 佛山市顺德区美的电子科技有限公司 | Direct-current power supply error-proofing control circuit and method and household appliance |
| CN214153992U (en) * | 2020-12-15 | 2021-09-07 | 自贡兴川光电有限公司 | Control circuit for realizing load switch control and detection protection of single-chip microcomputer IO port |
| CN112701663A (en) * | 2020-12-25 | 2021-04-23 | 上海东软载波微电子有限公司 | Overcurrent detection and protection circuit for power MOS (metal oxide semiconductor) tube and power MOS tube assembly |
| CN216625708U (en) * | 2021-08-05 | 2022-05-27 | 博泰车联网科技(上海)股份有限公司 | Load switch circuit |
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| CN115167232A (en) | 2022-10-11 |
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