CN1151633C - Gigabit charge system - Google Patents
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- CN1151633C CN1151633C CNB021293120A CN02129312A CN1151633C CN 1151633 C CN1151633 C CN 1151633C CN B021293120 A CNB021293120 A CN B021293120A CN 02129312 A CN02129312 A CN 02129312A CN 1151633 C CN1151633 C CN 1151633C
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Abstract
The present invention relates to a gigabit charging system which belongs to the technical field of counting and charging. The present invention is characterized in that the present invention comprises an interface unit of an internal network, an interface unit of an external network, a core data processing unit, an authority searching unit, a forwarding control unit, a message buffering unit, a PCI bus interface unit, an SRAM interface unit, a CAM interface unit, an SRAM and a CAM, wherein the interface unit of the internal network comprises a photoelectric converter and a serial-to-parallel converter which are orderly interconnected; the interface unit of the external network comprises a photoelectric converter and a serial-to-parallel converter which are orderly interconnected; the core data processing unit comprises a frame extracting unit and the authority searching unit which are respectively and orderly connected in series with the output end of the serial-to-parallel converter of the interface unit of the internal network and the output end of the serial-to-parallel converter of the interface unit of the external network; the authority searching unit and the forwarding control unit are respectively and orderly connected in series with the input end of the serial-to-parallel converter of the interface unit of the internal network and the output end of the serial-to-parallel converter of the interface unit of the external network; the message buffering unit is connected in series between the frame extracting unit and the forwarding control unit; the SRAM interface unit, the CAM interface unit, the SRAM and the CAM are connected. The forwarding control unit can be used for sending the essential information of a message to a PCI unit according to the requirement of a control word; then, the essential information is transmitted to a host by a PCI bus. The present invention has the advantages that host load can be greatly reduced, and simultaneously, the normal.
Description
Technical field
Gigabit charge system belongs to counting messages billing technology field, relates in particular to the PCI Mezzanine Card that is used for carrying out under the giga-bit network environment packet filtering, analysis, sampling.
Background technology
Nearly all charge system all adopts computer motherboard to add that two network interface cards compositions carry out counting messages based on IA32 (32bit IntelArchitecture, 32 Intel architectures) structure now.
Fig. 1 is the operation principle of this system.At first, NIC1 (Network Interface Card, network interface unit) Frame is received (A), then this Frame is passed through PCI (Peripheral Component Interfaces, the external equipment bus) bus and bridge device (Bridge) are transferred in the internal memory (Memory) (B), accounting routine reads Frame and uses buffering area (C) from the buffering area of network interface card, CPU analyzes this Frame decision and whether transmits (D), when transmitting, needs carry out suitable statistics earlier, again Frame is forwarded to network interface card buffering area (E), be transferred to NIC2 (F) by pci bus, last NIC2 sends (G) with this Frame.
This type systematic can be worked in low-end applications well, but just becomes the bottleneck of restriction network efficiency under high bandwidth environments.This mainly shows following several aspect:
1) because equipment such as network interface card need carry out the buffering of message, and the processing of waiting for CPU, this will consume the more time, can cause TCP (Transfer Control Protocol, transmission control protocol) connection speed descends, according to specific implementation, and may be to the influence of connection speed up to 30%.This influence is more remarkable in the gigabit charge system.
2) when the network bandwidth is increased to 1Gbps, in order to carry out bidirectional traffics control, require bus can receive and send bi-directional data, just reach 4Gbps.32 common pci buss only can provide the bandwidth of 1Gbps, may not satisfy this requirement; And the pci bus of 66MHz-64 position also only can be carried out the transmission of data, does not have to carry out to CPU remaining time the processing of message.The way that solves is to adopt either-way operation, just only utilizes 50% the network bandwidth; Or adopt two supervisory control systems to carry out the filtration of inside and outside net respectively, but this will bring unfavorable factors such as cost increases doubly, system complexity increase, reliability reduction; And even so, system also needs to waste time of 50% and carries out the transmission of message between network interface card and internal memory.
3) common 100,000,000, PCI-Express is not an equipment that customizes at charge system, a large amount of receive and send message in can frequently produce and interrupt, system will consume a lot of times when carrying out process switching.If interrupt not response in time, will directly cause losing of message, the network performance rapid deterioration.
4) because CPU need carry out message analysis, analyzing the time that is consumed not is a fixed value, but depends on specific rule.In order to satisfy the requirement of using, the charge system of a practicality need be carried out dozens or even hundreds of different analysis, judgement to same message, consumes the more time most probably, also may cause losing in flakes of follow-up message because can not in time handle.
Because previous reasons, under the network high bandwidth environments, traditional charge system can not meet the demands far away.Fig. 2 is the data of one group of actual measurement.In order to test the optimum efficiency of traditional billing scheme, be equipped with two PCI-Express (66MHz-64 position pci card) by a microcomputer server that runs on the Linux and finish message forwarding, therebetween without any rule process in kernel level.Even so, its result can not satisfy commercial requirement of using.As can be seen, for the average length (200～300 byte) of general networking message, traditional charge system reaches more than 60% the influence of the network bandwidth.
Summary of the invention
The object of the present invention is to provide a kind of gigabit charge system,, overcome the bottleneck of software processes, realize carrying out under the Gigabit Ethernet environment high-performance and charge so that utilize the mode of devices at full hardware to carry out the authority judgement of message.
The invention is characterized in: it contains: the Intranet interface unit comprises the optical-electrical converter (1 that links to each other with Intranet
I) and with this optical-electrical converter (1
I) interconnection deserializer (2
I); The outer net interface unit comprises the optical-electrical converter (1 that links to each other with outer net
E) and with this optical-electrical converter (1
E) interconnection deserializer (2
E); (FieldProgrammable Gate Array, the core data processing unit of FPGA) making comprise respectively successively and above-mentioned deserializer (2 field programmable gate array
I), (2
E) the frame extraction unit (3 of output serial connection
I), (3
E) and authority search unit (4
I) (4
E), respectively successively with above-mentioned deserializer (2
I), (2
E) the above-mentioned authority search unit (4 of input serial connection
E) (4
I) and transmit control unit (5
E) (5
I), be serially connected with above-mentioned frame extraction unit (3 respectively in turn
I), (3
E) and transmit control unit (5
I) (5
E) between message buffering unit (6
I), (6
E), pci interface unit (7), respectively successively simultaneously through internal bus P1, P2 and above-mentioned PCI unit (7), authority search unit (4
I) (4
E) link to each other, be connected with the SRAM interface unit (8) of static random access memory SRAM (10) alternately and be connected with the CAM interface unit (9) of content adressable memory CAM (11) alternately; Authority search unit (4 wherein
I) (4
E) respectively contain: input and frame extraction unit (3
I), (3
E) message parameter output link to each other, but output separately respectively with the SRAM query unit and the CAM query unit of SRAM interface unit (8) and CAM interface unit (9) interconnection, and input all links to each other with SRAM query unit, CAM query unit output, but output with transmit control unit (5
I) (5
E) the control word arithmetic element that links to each other of control word input; SRAM (10) and CAM (11).Described frame extraction unit (3
I), (3
E) contain: input and deserializer (2
I), (2
E) the frame synchronization unit that links to each other of data output end; Input links to each other with the output of above-mentioned frame synchronization unit, and the output and the above-mentioned message buffering unit (6 of output complete data frame
I), (6
E) the decoding unit that links to each other of input; Input links to each other with the output of above-mentioned decoding unit, and the output of outgoing message parameter and above-mentioned authority search unit (4
I) (4
E) the parameter extraction unit that links to each other of input.Described message buffering unit (6
I), (6
E) be the big capacity pushup storage FIFO of the complete data frame that receives in order to temporary transient preservation.Described forwarding control unit (5
I) (5
E) contain: input and message buffering unit (6
I), (6
E) frame data read the frame reading unit that end links to each other; Input respectively with the output and the authority search unit (4 of above-mentioned frame sensing element
I) (4
E) the retransmission unit that links to each other of output, encapsulation unit that input links to each other with the output of above-mentioned retransmission unit and input link to each other and output and deserializer (2 with above-mentioned encapsulation unit output
I), (2
E) the coding unit that links to each other of data input pin.
Use proof, it has reached intended purposes.
Description of drawings
The schematic diagram of the existing charge system of Fig. 1.
The graph of a relation of the existing charge system averaging network frame length of Fig. 2 and the network bandwidth.
The theory diagram of the gigabit charge system that Fig. 3 the present invention proposes.
Authority search unit (4 in the core data processing unit of the gigabit charge system that Fig. 4 the present invention proposes
I) (4
E) block diagram.
Frame extraction unit (3 in the core data processing unit of the gigabit charge system that Fig. 5 the present invention proposes
I), (3
E) block diagram.
Transmit control unit (5 in the core data processing unit of the gigabit charge system that Fig. 6 the present invention proposes
I) (5
E) block diagram.
Embodiment
In the gigabit charge system, authority search unit (4
I) (4
E) be used for obtaining the control word of this message according to the message basic parameter.As shown in Figure 4, it comprises the SRAM query unit, CAM query unit and control word arithmetic element.The SRAM query unit can obtain the access rights of this Intranet IP by the low location partial query SRAM interface unit of current message Intranet IP address.The CAM query unit can output to current message outer net IP address CAM and inquire about the network segment under this IP.The result of these two query unit is output to the control word arithmetic element.The control word arithmetic element judges whether this Intranet IP has authority to visit this outer net IP then as requested, obtains control word, and obtains its rate according to the affiliated network segment of outer net IP.
Frame extraction unit (3
I), (3
E) as shown in Figure 5, comprise frame synchronization unit, decoding unit, parameter extraction unit.
According to the requirement of IEEE std.802.3 (Electronic Engineering Association's 802.3 standards), the frame synchronization unit need be according to start of message (SOM) delimiter/S/ and the ENMES delimiter/T/ whole story of determining message of input in the data, and it is outputed to decoding unit.Decoding unit then carries out the decoding work of 8B/10B according to the requirement of IEEE std.802.3, obtain intelligible message data.These data are output to message buffering unit (6
I), (6
E), be sent to parameter extraction unit simultaneously.Parameter extraction unit need obtain basic message parameters such as the source IP address, target ip address of message, and these information are stored the fixed address place at message, can obtain by the input data are carried out simple count.
Wherein, frame synchronization unit and decoding unit position can exchange.
Message buffering unit (6
I), (6
E) form by big Capacity FIFO (First In First Out, pushup storage).Be used for the temporary transient complete data frame that receives of preserving.
Transmit control unit (5
I) (5
E) structure as shown in Figure 6, comprise frame reading unit, retransmission unit, encapsulation unit, coding unit.The frame reading unit is used for complete Frame from message buffering unit (6
I), (6
E) in read.Control unit receives the message control word, and determines that current message is to transmit or abandon.If message needs to transmit, then be delivered to encapsulation unit, encapsulate according to the requirement of IEEE std.802.3, carry out the coding of 8B/10B then by coding unit, send at last.
The function basically identical of SRAM interface unit (8) and CAM interface unit (9).The core data processing module is carried out reading and writing data by SRAM interface unit (8) to SRAM (10), by CAM interface unit (9) CAM (11) is carried out operations such as data reading and writing, search.In the inside of core data processing unit, they accept the data transfer request of different units, change according to fixing priority or wheel, realize the function of a multi-channel gating device.
The communication of core data processing module and host computer system has been realized in the pci interface unit.Its function has concrete description in PCI Local BusSpecification 2.1 (PCI local bus specification 2.1 editions).This pci interface unit has been realized the requirement of defined PCI main equipment in this standard substantially.
Optical-electrical converter (1 among Fig. 3
I) (1
E) function be that light signal is converted into the signal of telecommunication, perhaps opposite process.The signal of telecommunication that light signal is converted into PECL (Positive Emitter Coupled Logic, positive voltage ECL) is sent to deserializer (2
I), (2
E) handle; From deserializer (2
I), (2
E) the PECL signal that sends over is converted into light signal and sends.
Deserializer (2 among Fig. 3
I), (2
E) be with from optical-electrical converter (1
I) (1
E) high-speed serial data that sends is converted to parallel data, and opposite process.
Optical-electrical converter (1 among Fig. 3
I) (1
E) and deserializer (2
I), (2
E) be collectively referred to as network interface unit.
The major function of core data processing unit is to carry out the identification of message data, processing and forwarding among Fig. 3, and it comprises frame extraction unit (3
I) (3
E), message buffering unit (6
I) (6
E), transmit control unit (5
E) (5
I), authority search unit (4
E) (4
I), SRAM interface unit (8), CAM interface unit (9), pci interface unit (7) etc.The core data processing unit can be realized with programming device.
Content adressable memory CAM is used to preserve the IP address field among Fig. 3.When the IP address of incoming message, can obtain scope under this IP address by inquiry CAM, can realize control and multiple rate statistics to visiting different addresses.
Static random access memory SRAM is used to preserve the information such as authority of Intranet IP address among Fig. 3.
Pci bus is used for charge system and main frame carries out communication among Fig. 3.Software can send to charge system with control information by pci bus, and the while charge system also can send to main frame with message source, target, length etc. and add up.
Above optical-electrical converter (1 with chip HFBR-53D5 system
I), (1
E), the deserializer (2 of chip HDMP-1646A system
I), (2
E), the core data processing unit, the SRAM (10) of chip 71016 systems and the CAM (11) of chip 75T43100 system have constituted native system, and its course of work is as follows:
1. the physical signalling in the network is through optical-electrical converter (1
I), (1
E), deserializer (2
I), (2
E) become 10 parallel data, and give frame extraction unit (3
I), (3
E);
2. the frame extraction unit (3
I), (3
E) to the operation such as decode of data stream, obtain Frame, Frame is delivered to message buffering unit (6
I), (6
E), and its relevant information sent to authority search unit (4
I) (4
E);
3. the message buffering unit (6
I), (6
E) preserve the mac frame data temporarily;
4. the authority search unit (4
I) (4
E) obtain message information, by CAM interface (9) inquiry CAM (11),, calculate the authority of corresponding message, i.e. control code by SRAM interface (8) inquiry SRAM (10);
5. the authority search unit (4
I) (4
E) control code of this message is delivered to forwarding control unit (5
I) (5
E);
6. transmit control unit (5
I) (5
E) with Frame from message buffering unit (6
I), (6
E) in read, with this packet loss, send to deserializer (2 after perhaps requiring to encapsulate, encode according to control code decision according to Ethernet
I), (2
E);
7. deserializer (2
I), (2
E) parallel data is converted to serial data, then by optical-electrical converter (1
I), (1
E) become light signal and send.
Inquiry CAM and SRAM obtain control code can adopt following method:
1. CAM is divided into a plurality of data segments, in same data segment, preserve the IP address range of identical authority, identical rate, which data segment the outer net IP address of discerning in the current message by the high address among the output result belongs to, i.e. the affiliated data segment of current message;
2. by the low order address inquiry SRAM of current message source IP address, obtain the access rights word of corresponding Intranet IP address;
3. judge whether to allow this Intranet IP to visit network in this data segment according to this authority word, obtain control code.
The main application of CAM is to preserve the IP address range of different rates at diverse location, and this IP address range can be revised dynamically by main frame.If do not adopt CAM, then can only realize single control of authority by inquiry SRAM, promptly whether allow the control of Intranet IP visit outer net.Perhaps directly be cured to the requirement that realizes many rate accountings in the authority search unit logic of core data processing unit by the network address with different rates, its shortcoming is the network address range that can not dynamically update various rates.
Because main frame needs the accounting message flow, therefore, transmit control unit (5
E) (5
I) can with the essential information of message, comprise source IP address, target ip address, source port address, target port address, message length etc. according to the requirement of control word, send to the pci interface unit, be delivered to main frame by pci bus then.Make sampling in this way, rather than whole message is delivered to main frame, can reduce the load of main frame greatly, do not influence normal charging demand simultaneously again.
Claims (4)
1, gigabit charge system contains network interface unit and data processing unit, it is characterized in that it contains: the Intranet interface unit comprises the optical-electrical converter (1 that links to each other with Intranet
I) and with this optical-electrical converter (1
I) interconnection deserializer (2
I); The outer net interface unit comprises the optical-electrical converter (1 that links to each other with outer net
E) and with this optical-electrical converter (1
E) interconnection deserializer (2
E); The core data processing unit that on-site programmable gate array FPGA is made comprises respectively successively and above-mentioned deserializer (2
I), (2
E) the frame extraction unit (3 of output serial connection
I), (3
E) and authority search unit (4
I) (4
E), respectively successively with above-mentioned deserializer (2
I), (2
E) the above-mentioned authority search unit (4 of input serial connection
E) (4
I) and transmit control unit (5
E) (5
I), be serially connected with above-mentioned frame extraction unit (3 respectively in turn
I), (3
E) and transmit control unit (5
I) (5
E) between message buffering unit (6
I), (6
E), pci interface unit (7), respectively successively simultaneously through internal bus P1, P2 and above-mentioned PCI unit (7), authority search unit (4
I) (4
E) link to each other, be connected with the SRAM interface unit (8) of static random access memory SRAM (10) alternately and be connected with the CAM interface unit (9) of content adressable memory CAM (11) alternately; Authority search unit (4 wherein
I) (4
E) respectively contain: input and frame extraction unit (3
I), (3
E) message parameter output link to each other, but output separately respectively with the SRAM query unit and the CAM query unit of SRAM interface unit (8) and CAM interface unit (9) interconnection, and input all links to each other with SRAM query unit, CAM query unit output, but output with transmit control unit (5
I) (5
E) the control word arithmetic element that links to each other of control word input; SRAM (10) and CAM (11).
2, gigabit charge system according to claim 1 is characterized in that: described frame extraction unit (3
I), (3
E) contain: input and deserializer (2
I), (2
E) the frame synchronization unit that links to each other of data output end; Input links to each other with the output of above-mentioned frame synchronization unit, and the output and the above-mentioned message buffering unit (6 of output complete data frame
I), (6
E) the decoding unit that links to each other of input; Input links to each other with the output of above-mentioned decoding unit, and the output of outgoing message parameter and above-mentioned authority search unit (4
I) (4
E) the parameter extraction unit that links to each other of input.
3, gigabit charge system according to claim 1 is characterized in that: described message buffering unit (6
I), (6
E) be the big capacity pushup storage FIFO of the complete data frame that receives in order to temporary transient preservation.
4, gigabit charge system according to claim 1 is characterized in that: described forwarding control unit (5
I) (5
E) contain: input and message buffering unit (6
I), (6
E) frame data read the frame reading unit that end links to each other; Input respectively with the output and the authority search unit (4 of above-mentioned frame sensing element
I) (4
E) the retransmission unit that links to each other of output, encapsulation unit that input links to each other with the output of above-mentioned retransmission unit and input link to each other and output and deserializer (2 with above-mentioned encapsulation unit output
I), (2
E) the coding unit that links to each other of data input pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021293120A CN1151633C (en) | 2002-08-30 | 2002-08-30 | Gigabit charge system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021293120A CN1151633C (en) | 2002-08-30 | 2002-08-30 | Gigabit charge system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1398085A CN1398085A (en) | 2003-02-19 |
| CN1151633C true CN1151633C (en) | 2004-05-26 |
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|---|---|---|---|
| CNB021293120A Expired - Fee Related CN1151633C (en) | 2002-08-30 | 2002-08-30 | Gigabit charge system |
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| Country | Link |
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| CN (1) | CN1151633C (en) |
Families Citing this family (1)
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| CN100466525C (en) * | 2007-05-30 | 2009-03-04 | 南京联创科技股份有限公司 | Buffer-based magnitude charging middle message processing method |
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