CN115150658A - EDID detection method, chip, VGA signal source and electronic equipment - Google Patents

EDID detection method, chip, VGA signal source and electronic equipment Download PDF

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Publication number
CN115150658A
CN115150658A CN202211061274.2A CN202211061274A CN115150658A CN 115150658 A CN115150658 A CN 115150658A CN 202211061274 A CN202211061274 A CN 202211061274A CN 115150658 A CN115150658 A CN 115150658A
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China
Prior art keywords
conversion chip
video conversion
edid
hdmi
signal source
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CN202211061274.2A
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Chinese (zh)
Inventor
周文浩
刘伟
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Hongjing Microelectronics Technology Co ltd
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Hongjing Microelectronics Technology Co ltd
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Priority to CN202211061274.2A priority Critical patent/CN115150658A/en
Publication of CN115150658A publication Critical patent/CN115150658A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H04N21/43635—HDMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

The present disclosure provides a detection method, a chip, a VGA signal source and an electronic device for EDID, wherein the detection method is applied to a video conversion chip, the video conversion chip is used for performing interface conversion between a video graphics array VGA interface and a high definition multimedia interface HDMI, and the detection method comprises the following steps: reading EDID information of HDMI equipment connected with the video conversion chip through an HDMI output end of the video conversion chip; caching EDID information of the HDMI equipment to a pre-configured EDID module; and outputting the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip. According to this disclosed technical scheme, the VGA signal source can read the EDID information of the HDMI equipment of buffer memory from predetermined EDID module to be favorable to improving the image adaptation degree between VGA signal source and the HDMI equipment, improve image display quality.

Description

EDID detection method, chip, VGA signal source and electronic equipment
Technical Field
The disclosure relates to the technical field of video interface conversion, and in particular to an EDID detection method, a video conversion chip, a VGA signal source, and an electronic device.
Background
At present, in an Interface conversion scheme from a Video Graphics Array (VGA) Interface to a High Definition Multimedia Interface (HDMI) Interface, a problem of Extended Display Identification Data (EDID) communication interruption is usually encountered, that is, a VGA signal source can only read the EDID of the VGA signal source but cannot access the EDID of an HDMI device, which causes that the VGA signal source may not obtain device information of the HDMI device, thereby affecting information Display, image quality, and the like.
Disclosure of Invention
The disclosure provides an EDID detection method, a video conversion chip, a VGA signal source and an electronic device.
In a first aspect, the present disclosure provides a detection method for EDID, where the detection method is applied to a video conversion chip, and the video conversion chip is used to perform interface conversion between a video graphics array VGA interface and a high definition multimedia interface HDMI, and the detection method includes:
reading EDID information of HDMI equipment connected with the video conversion chip through an HDMI output end of the video conversion chip;
caching the EDID information of the HDMI equipment to a pre-configured EDID module;
and outputting the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip.
In a second aspect, the present disclosure provides a method for detecting EDID, where the method is applied to a VGA signal source, and the method includes:
detecting the connection state between a video conversion chip and the VGA signal source;
and in response to the detection that the video conversion chip and the VGA signal source are in a connection state, reading EDID information of HDMI equipment connected with the video conversion chip, which is cached in advance by the EDID module, from the EDID module of the video conversion chip.
In a third aspect, the present disclosure provides a video conversion chip, including:
the first reading module is configured to read EDID information of HDMI equipment connected with the video conversion chip through an HDMI output end of the video conversion chip;
the cache module is configured to cache the EDID information of the HDMI equipment to a preconfigured EDID module;
and the output module is configured to output the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip.
In a fourth aspect, the present disclosure provides a VGA signal source comprising:
the second detection module is configured to detect the connection state between the video conversion chip and the VGA signal source;
and the second reading module is configured to read EDID information, cached in advance by the EDID module, of the HDMI device connected with the video conversion chip from the EDID module of the video conversion chip in response to the second detection module detecting that the video conversion chip and the VGA signal source are in a connected state.
In a fifth aspect, the present disclosure provides an electronic device comprising: the device comprises a VGA signal source, a video conversion chip and HDMI equipment;
wherein the video conversion chip includes the video conversion chip of the third aspect, and/or the VGA signal source includes the VGA signal source of the fourth aspect.
According to the technical scheme of the EDID detection method, the video conversion chip, the VGA signal source and the electronic device, the video conversion chip is used for converting an interface signal between a Video Graphic Array (VGA) interface and a high-definition multimedia interface (HDMI), EDID information detection is carried out through the detection method provided by the embodiment of the disclosure before the video conversion chip carries out interface conversion, EDID information of the HDMI device connected with the video conversion chip is detected and cached to a preset EDID module, so that the VGA signal source connected with the video conversion chip can conveniently read the EDID information of the HDMI device from the preset EDID module, and the EDID information of the HDMI device usually comprises manufacturer information, display parameters, optimal resolution and the like of the device, so that the VGA signal source can conveniently configure and output corresponding image signals according to the EDID information of the HDMI device, the problems of image color loss, image display distortion caused by stretching or zooming of a display picture and the like in the interface conversion process can be improved, the image adaptation degree between the VGA signal source and the HDMI device can be effectively improved, and the image display quality can be improved. In addition, according to the technical scheme, the EDID information is copied, the carrying process is completely and automatically carried out, and in the copying and carrying processes, the requirements on a VGA signal source, a video conversion chip and HDMI equipment on special power-on time sequence and interface plugging and unplugging time sequence are avoided.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic flow chart of an EDID detection method according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a connection relationship among a VGA signal source, a video conversion chip, and an HDMI device;
fig. 3 is a schematic flow chart of another EDID detection method according to an embodiment of the present disclosure;
fig. 4 is a block diagram of a video conversion chip according to an embodiment of the disclosure;
fig. 5 is a block diagram of another video conversion chip according to an embodiment of the disclosure;
fig. 6 is a block diagram of a VGA signal source according to an embodiment of the present disclosure;
fig. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, … … specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic flowchart of an EDID detection method according to an embodiment of the present disclosure.
In a first aspect, an embodiment of the present disclosure provides a method for detecting EDID, where the method is applied to a video conversion chip, and the video conversion chip is used to perform interface conversion between a video graphics array VGA interface and a high definition multimedia interface HDMI. Referring to fig. 1, the detection method may include: step S11 to step S13.
And S11, reading EDID information of the HDMI equipment connected with the video conversion chip through the HDMI output end of the video conversion chip.
And S12, caching the EDID information of the HDMI equipment to a pre-configured EDID module.
And S13, outputting the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip.
In the embodiment of the disclosure, the video conversion chip is used for performing interface signal conversion between a Video Graphics Array (VGA) interface and a high-definition multimedia interface (HDMI), and before the video conversion chip performs interface conversion, EDID information detection is performed by using the detection method provided by the embodiment of the disclosure to detect EDID information of HDMI equipment connected with the video conversion chip and cache the EDID information to a preset EDID module, so that a VGA signal source connected with the video conversion chip can read the EDID information of the HDMI equipment from the preset EDID module, and the EDID information of the HDMI equipment usually contains manufacturer information, display parameters, optimal resolution and the like of the equipment, so that the VGA signal source can configure and output corresponding image signals according to the EDID information of the HDMI equipment, and further, the problems of image color loss, image display distortion caused by stretching or zooming of a display picture and the like in the interface conversion process can be improved and solved, the image adaptation degree between the VGA signal source and the HDMI equipment can be effectively improved, and the image display quality can be improved. In addition, according to the technical scheme, the EDID information is copied, the carrying process is completely and automatically carried out, and in the copying and carrying processes, the requirements on a VGA signal source, a video conversion chip and HDMI equipment on special power-on time sequence and interface plugging and unplugging time sequence are avoided.
In the embodiment of the present disclosure, the video conversion chip adopts a VGA2HDMI chip, and the VGA2HDMI is a video conversion standard.
In the embodiment of the present disclosure, the HDMI device may be any display device having an HDMI interface, and the specific implementation form of the display device is not particularly limited in the embodiment of the present disclosure. The VGA signal source can be any signal source end with VGA interface, for example, the VGA signal source is a set-top box or a computer host.
Fig. 2 is a schematic diagram of a connection relationship between a VGA signal source, a video conversion chip, and an HDMI device, and referring to fig. 1 and fig. 2, as an example, when an HDMI output end of the video conversion chip is connected to the HDMI device, the HDMI output end of the video conversion chip receives EDID information of the HDMI device through a Display Data Channel (DDC) between the HDMI device and the HDMI device, specifically, the Display Data Channel (DDC) includes a bidirectional Data line DDC _ SDA and a clock control line DDC _ SCL, and is mainly used for exchanging EDID information and a High-bandwidth Digital Content Protection technology (HDCP) key between an HDMI source device (i.e., the video conversion chip) and a sink device (i.e., the HDMI DDC device), and in step S11, the EDID information of the HDMI device transmitted through the DDC Channel is read through the HDMI output end of the video conversion chip.
In the embodiment of the present disclosure, as shown in fig. 2, the EDID module is a virtual storage module configured in advance in the video conversion chip, and is configured to store the read EDID information of the HDMI device, and in step S12, after the EDID information of the HDMI device is read, the EDID information of the HDMI device is cached in the preconfigured EDID module. Further, in order to improve the caching efficiency and save the caching space, the first 128 bytes (Byte) of the EDID information of the HDMI device may be carried to the EDID module for caching.
As an example, after the VGA signal source is connected to the video conversion chip, the VGA signal source can read the EDID information of the HDMI device, which is buffered in advance, from the EDID module of the video conversion chip through the DDC channel (including the DDC _ SDA and the DDC _ SCL) between the VGA signal source and the video conversion chip, and thus, in step S13, the EDID information of the HDMI device, which is buffered by the EDID module, is output to the VGA signal source connected to the video conversion chip through the DDC channel.
In some embodiments, before reading, through the HDMI output terminal of the video conversion chip, the EDID information of the HDMI device connected to the video conversion chip, the detection method further includes: and detecting the connection state between the video conversion chip and the HDMI equipment according to a Hot Plug Detect (HPD) pin signal.
For example, when the signal of the hot plug HPD pin is detected to be at a high level, it indicates that the HDMI device is connected to the video conversion chip, and when the signal of the hot plug HPD pin is detected to be at a low level, it indicates that the HDMI device is disconnected from the video conversion chip.
Further, the step of reading, through the HDMI output terminal of the video conversion chip, the EDID information of the HDMI device connected to the video conversion chip, that is, step S11, includes: when the video conversion chip is detected to be in a connection state with the HDMI device, the EDID information of the HDMI device is read through the HDMI output end of the video conversion chip.
Further, when the video conversion chip and the HDMI device are detected to be in a disconnected state, the connection state between the video conversion chip and the HDMI device is detected according to a Hot Plug Detect (HPD) pin signal, so as to continue monitoring the state of the HPD pin signal.
In some embodiments, after the step of buffering the EDID information of the HDMI device to the preconfigured EDID module, i.e., after step S12, the detection method further includes: and responding to the completion of the EDID information caching of the HDMI equipment, and controlling the conduction of an analog image signal channel between the video conversion chip and the VGA signal source.
Illustratively, when the EDID information of the HDMI device is conveyed to the EDID module to be cached, an EDID conveyance completion status signal is generated, and when the EDID conveyance completion status signal exists, the EDID information of the HDMI device is completely cached, at this time, the analog image signal channel between the video conversion chip and the VGA signal source is controlled to be conducted, so that the VGA signal source reads the required EDID information from the EDID module when monitoring that the analog image signal channel is conducted.
In some embodiments, as shown in fig. 2, the analog image signal channel between the video conversion chip and the VGA signal source includes three analog switch circuits, namely a first analog switch circuit R, a second analog switch circuit G, and a third analog switch circuit B, which are respectively configured to transmit the image signals of the respective corresponding color channels in the on state.
Each analog switch circuit is provided with a control switch, each analog switch circuit is in a disconnection state by default, when an EDID carrying completion state signal exists, the EDID information caching of the HDMI equipment is completed, at the moment, a switch enabling signal is generated and a switch enabling signal Data _ EN is respectively output to the control switches of the three analog switch circuits, so that the control switches of the three analog switch circuits are in a conduction state, namely the three analog switch circuits are conducted.
In some embodiments, each analog switch circuit has a termination resistor (75 ohms) at the VGA signal source end side and a termination resistor (75 ohms) at the video conversion chip end side, when the analog switch circuit is turned on, the resistor at the VGA signal source end side is connected in parallel with the termination resistor at the video conversion chip end side, so that the level of the analog switch circuit changes, and when the VGA signal source detects that the levels of the three analog switch circuits all change, it indicates that the VGA signal source and the video conversion chip are in a connection state, at which time the VGA signal source can obtain the required EDID information through the EDID module.
As shown in fig. 2, after the three analog switch circuits between the video conversion chip and the VGA signal source are controlled to be turned on, a synchronization signal of the VGA signal source is detected by a Synchronization (SYNC) detection module, where the synchronization signal includes a horizontal synchronization signal (HSYNC) and a vertical synchronization signal (VSYNC), and a signal parameter (e.g., a signal parameter such as a resolution) of the VGA signal source is obtained by analyzing the detected synchronization signal, so as to determine an input mode of the VGA signal source.
After the input mode of the VGA signal source is determined, HDMI output configuration is carried out, and after input mode detection and output configuration are completed, the video conversion chip can carry out interface signal conversion based on the input mode of the VGA signal source and the HDMI output configuration, so that interface conversion between the VGA interface and the HDMI interface is completed.
Fig. 3 is a schematic flowchart of another EDID detection method according to an embodiment of the present disclosure.
In a second aspect, referring to fig. 3, an embodiment of the present disclosure provides a method for detecting EDID, where the method is applied to a VGA signal source, and the method includes: step S31-step S32.
And S31, detecting the connection state between the video conversion chip and the VGA signal source.
And step S32, in response to the detection that the video conversion chip and the VGA signal source are in a connection state, reading EDID information of the HDMI equipment which is cached in advance by the EDID module and connected with the video conversion chip from the EDID module of the video conversion chip.
In some embodiments, the step of detecting the connection state between the video conversion chip and the VGA signal source, namely step S31, may further include: detecting the conduction state of an analog image signal channel between a video conversion chip and a VGA signal source; and determining that the video conversion chip and the VGA signal source are in a connection state in response to detecting that the analog image signal channel is in a conduction state.
Illustratively, in conjunction with fig. 2, the analog image signal channel includes three analog switch circuits (R, G, B), and when it is detected that the levels corresponding to the three analog switch circuits all change, the three analog switch circuits are all in a conducting state.
And when the video conversion chip is detected to be in a disconnected state with the VGA signal source, the detection step of the conduction state of the analog image signal channel is continued.
In conjunction with fig. 2, in step S32, in response to detecting that the video conversion chip and the VGA signal source are in a connected state, the pre-buffered EDID information of the HDMI device is read from the EDID module of the video conversion chip through the DDC channel (including DDC _ SDA and DDC _ SCL) between the video conversion chip and the video conversion chip.
In the embodiment of the disclosure, the video conversion chip is used for performing interface signal conversion between a Video Graphics Array (VGA) interface and a high-definition multimedia interface (HDMI), before the video conversion chip performs interface conversion, the video conversion chip detects EDID information of HDMI equipment connected with the video conversion chip on the video conversion chip side and caches the EDID information to a preset EDID module; at the VGA signal source side, after a VGA signal source connected with a video conversion chip detects that the VGA signal source is in a connection state with the video conversion chip, EDID information of HDMI equipment which is cached in advance is read from an EDID module preset by the video conversion chip, and the EDID information of the HDMI equipment usually contains manufacturer information, display parameters, optimal resolution and the like of the equipment, so that the VGA signal source can conveniently configure and output corresponding image signals according to the EDID information of the HDMI equipment, and further the problems of image color loss in the interface conversion process, image display distortion caused by stretching or zooming of a display picture and the like can be improved and solved, the image adaptation degree between the VGA signal source and the HDMI equipment is effectively improved, and the image display quality is improved.
It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above methods of the specific embodiments, the specific order of execution of the steps should be determined by their function and possibly their inherent logic.
In addition, the present disclosure also provides a video conversion chip, a VGA signal source, an electronic device, and a computer readable storage medium, where the video conversion chip is used to implement the detection method provided in the first aspect, the VGA signal source is used to implement the detection method provided in the second aspect, and both the electronic device and the computer readable storage medium can be used to implement the detection method provided in the present disclosure, and corresponding technical solutions and descriptions are referred to corresponding descriptions of the method portions, and are not repeated here.
Fig. 4 is a block diagram of a video conversion chip according to an embodiment of the present disclosure.
In a third aspect, referring to fig. 4, an embodiment of the present disclosure provides a video conversion chip 400, where the video conversion chip 400 is configured to perform interface conversion between a VGA interface and a HDMI, and the video conversion chip 400 includes: a first reading module 401, a buffer module 402 and an output module 403.
The first reading module 401 is configured to read, through the HDMI output end of the video conversion chip, the EDID information of the HDMI device connected to the video conversion chip;
the buffer module 402 is configured to buffer the EDID information of the HDMI device to a preconfigured EDID module;
and the output module 403 is configured to output the EDID information of the HDMI device buffered by the EDID module to the VGA signal source connected to the video conversion chip.
Fig. 5 is a block diagram of another video conversion chip provided in an embodiment of the present disclosure, and referring to fig. 5, in some embodiments, the video conversion chip 400 further includes a first detection module 404; the first detection module 404 is configured to detect a connection state of a video conversion chip and the HDMI device according to a hot plug HPD pin signal; the first reading module 401 is configured to read the EDID information of the HDMI device through the HDMI output terminal of the video conversion chip when the first detecting module 404 detects that the video conversion chip is in a connection state with the HDMI device.
In some embodiments, the video conversion chip 400 further includes: a control module 405; the control module 405 is configured to control the conduction of the analog image signal channel between the video conversion chip and the VGA signal source in response to the completion of the buffering of the EDID information of the HDMI device.
In some embodiments, with reference to fig. 2, fig. 4 and fig. 5, the video conversion chip 400 has a processor (CPU), and some or all of the above functional modules may be integrated in the processor CPU of the video conversion chip 400.
For specific description, reference may be made to relevant description in the detection method in the embodiment of the first aspect, and details are not described herein again.
Fig. 6 is a block diagram of a VGA signal source according to an embodiment of the present disclosure.
In a fourth aspect, referring to fig. 6, an embodiment of the present disclosure provides a VGA signal source 600, where the VGA signal source 600 includes: a second detection module 601 and a second read module 602.
The second detection module 601 is configured to detect a connection state between the video conversion chip and the VGA signal source.
And the second reading module 602 is configured to, in response to the second detection module 601 detecting that the video conversion chip and the VGA signal source are in a connected state, read, from the EDID module of the video conversion chip, EDID information of the HDMI device connected to the video conversion chip, which is cached in advance by the EDID module.
In some embodiments, the second detection module 601 is configured to: detecting the conduction state of an analog image signal channel between a video conversion chip and a VGA signal source; and determining that the video conversion chip and the VGA signal source are in a connection state in response to detecting that the analog image signal channel is in a conduction state.
The VGA signal source provided in the embodiment of the present disclosure is used to implement the detection method provided in the embodiment of the second aspect, and specific description may refer to related description in the detection method in the embodiment of the second aspect, and is not repeated here.
In a fifth aspect, an embodiment of the present disclosure provides an electronic device, and fig. 2 illustrates a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure, and referring to fig. 2, the electronic device includes: the device comprises a VGA signal source, a video conversion chip and HDMI equipment;
wherein, the video conversion chip comprises the video conversion chip of the third aspect, and/or the VGA signal source comprises the VGA signal source of the fourth aspect. For specific description of the video conversion chip and the VGA signal source, reference may be made to the description of the video conversion chip and the VGA signal source in the foregoing embodiment, and details are not repeated here.
Fig. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure, and referring to fig. 7, an embodiment of the present disclosure provides an electronic device including: at least one processor 71; at least one memory 72, and one or more I/O interfaces 73 coupled between the processor 71 and the memory 72; wherein the memory 72 stores one or more computer programs executable by the at least one processor 71, the one or more computer programs being executable by the at least one processor 71 to enable the at least one processor 71 to perform the detection method provided by the embodiments of any of the above aspects.
The present disclosure also provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the detection method provided by the embodiment of any aspect. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium, among others.
Embodiments of the present disclosure also provide a computer program product, which includes computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code runs in a processor of an electronic device, the processor in the electronic device executes the detection method provided by an embodiment of any one of the above aspects.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data, as is well known to those skilled in the art. Computer storage media includes, but is not limited to, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), static Random Access Memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer. In addition, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (11)

1. The EDID detection method is applied to a video conversion chip, wherein the video conversion chip is used for performing interface conversion between a Video Graphics Array (VGA) interface and a high-definition multimedia interface (HDMI), and the method comprises the following steps:
reading EDID information of HDMI equipment connected with the video conversion chip through an HDMI output end of the video conversion chip;
caching the EDID information of the HDMI equipment to a pre-configured EDID module;
and outputting the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip.
2. The method according to claim 1, wherein before the reading of the EDID information of the HDMI device connected to the video conversion chip through the HDMI output terminal of the video conversion chip, the method further comprises: detecting the connection state between the video conversion chip and the HDMI equipment according to a hot plug HPD pin signal;
through the HDMI output of video conversion chip read with the EDID information of the HDMI equipment that the video conversion chip is connected includes: and when the video conversion chip is detected to be in a connection state with the HDMI equipment, reading the EDID information of the HDMI equipment through the HDMI output end of the video conversion chip.
3. The method according to claim 1, wherein after buffering the EDID information of the HDMI device to a preconfigured EDID module, the method further comprises:
and responding to the completion of the EDID information caching of the HDMI equipment, and controlling the conduction of an analog image signal channel between the video conversion chip and the VGA signal source.
4. The EDID detection method is applied to a VGA signal source and comprises the following steps:
detecting the connection state between a video conversion chip and the VGA signal source;
and reading EDID information of the HDMI equipment connected with the video conversion chip, which is cached in advance by the EDID module, from the EDID module of the video conversion chip in response to the fact that the video conversion chip and the VGA signal source are detected to be in a connection state.
5. The method according to claim 4, wherein the detecting the connection status between the video conversion chip and the VGA signal source comprises:
detecting the conduction state of an analog image signal channel between the video conversion chip and the VGA signal source;
and determining that the video conversion chip and the VGA signal source are in a connection state in response to detecting that the analog image signal channel is in a conduction state.
6. A video conversion chip, comprising:
the first reading module is configured to read EDID information of HDMI equipment connected with the video conversion chip through an HDMI output end of the video conversion chip;
the cache module is configured to cache the EDID information of the HDMI equipment to a preconfigured EDID module;
and the output module is configured to output the EDID information of the HDMI equipment cached by the EDID module to a VGA signal source connected with the video conversion chip.
7. The video conversion chip of claim 6, wherein the video conversion chip further comprises: a first detection module;
the first detection module is configured to detect a connection state of the video conversion chip and the HDMI device according to a hot plug HPD pin signal;
the first reading module is configured to read the EDID information of the HDMI device through the HDMI output end of the video conversion chip when the first detection module detects that the video conversion chip and the HDMI device are in a connection state.
8. The video conversion chip of claim 6, wherein the video conversion chip further comprises: a control module; the control module is configured to respond to the completion of the EDID information caching of the HDMI equipment and control the conduction of an analog image signal channel between the video conversion chip and the VGA signal source.
9. A VGA signal source, comprising:
the second detection module is configured to detect the connection state between the video conversion chip and the VGA signal source;
the second reading module is configured to read, in response to the second detection module detecting that the video conversion chip and the VGA signal source are in a connection state, EDID information of the HDMI device, which is cached in advance by the EDID module and connected to the video conversion chip, from the EDID module of the video conversion chip.
10. The VGA signal source of claim 9, wherein the second detection module is configured to:
detecting the conduction state of an analog image signal channel between the video conversion chip and the VGA signal source;
and determining that the video conversion chip and the VGA signal source are in a connection state in response to detecting that the analog image signal channel is in a conduction state.
11. An electronic device, comprising: the device comprises a VGA signal source, a video conversion chip and HDMI equipment;
wherein the video conversion chip comprises a video conversion chip according to any one of claims 6 to 8, and/or the VGA signal source comprises a VGA signal source according to claim 9 or 10.
CN202211061274.2A 2022-09-01 2022-09-01 EDID detection method, chip, VGA signal source and electronic equipment Pending CN115150658A (en)

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