CN115150006A - Phase simulation method, phase simulation device, storage medium and network analyzer - Google Patents

Phase simulation method, phase simulation device, storage medium and network analyzer Download PDF

Info

Publication number
CN115150006A
CN115150006A CN202110284393.3A CN202110284393A CN115150006A CN 115150006 A CN115150006 A CN 115150006A CN 202110284393 A CN202110284393 A CN 202110284393A CN 115150006 A CN115150006 A CN 115150006A
Authority
CN
China
Prior art keywords
loss
phase delay
phase
target
receiving port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110284393.3A
Other languages
Chinese (zh)
Inventor
张磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Oppo Mobile Telecommunications Corp Ltd
Original Assignee
Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Oppo Mobile Telecommunications Corp Ltd filed Critical Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority to CN202110284393.3A priority Critical patent/CN115150006A/en
Publication of CN115150006A publication Critical patent/CN115150006A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/30Monitoring; Testing of propagation channels
    • H04B17/309Measuring or estimating channel quality parameters
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/30Monitoring; Testing of propagation channels
    • H04B17/391Modelling the propagation channel
    • H04B17/3912Simulation models, e.g. distribution of spectral power density or received signal strength indicator [RSSI] for a given geographic region
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/08Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823Errors, e.g. transmission errors
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/50Testing arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Environmental & Geological Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Quality & Reliability (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

The application discloses a phase simulation method, which relates to the technical field of electronic device testing, and comprises the steps of firstly obtaining a first phase delay and a first loss of a receiving port extending to a port of a device to be tested, and obtaining a second phase delay and a second loss of the receiving port extending to a matching device; then determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss; and finally, respectively setting the phase adjuster and the attenuator based on the target phase delay and the target loss, so that phase simulation is realized, and phase transformation of impedance at different positions is also realized through the phase simulation. The phase-adjusting device and the attenuator can be set according to the phase delay data and the loss data of the receiving port extending to different positions, so that the positions of the impedances at different positions can be obtained through phase simulation, and matching and debugging at different positions are facilitated.

Description

Phase simulation method, phase simulation device, storage medium and network analyzer
Technical Field
The present disclosure relates to the field of electronic device testing technologies, and in particular, to a phase simulation method and apparatus, a storage medium, and a network analyzer.
Background
Along with the development of science and technology, more and more electronic equipment is used in people's life, and electronic equipment generally needs to be debugged when designing, and how to conveniently debug electronic equipment also becomes one of the key points of research of technical personnel in the field.
In the related art, radio frequency debugging can be performed on electronic equipment through a network analyzer, and a certain phase difference exists between impedance at a matching device and impedance at a port of a power amplifier in the debugging process of the power amplifier, so that difficulty is brought to final debugging.
Disclosure of Invention
The application provides a phase simulation method, a phase simulation device, a storage medium and a network analyzer, which can solve the technical problem that in the related technology, the impedance of a component matching device and the impedance of a port of a power amplifier have a certain phase difference, so that the final debugging is difficult.
In a first aspect, an embodiment of the present application provides a phase simulation method applied to a network analyzer, where the network analyzer at least includes a phase modulator and an attenuator that are arranged in series between a receiving port and a measurement receiver, and the method includes:
acquiring a first phase delay and a first loss of the receiving port extending to a port of a device to be tested, and acquiring a second phase delay and a second loss of the receiving port extending to a matching device;
determining a target phase delay from the first phase delay and the second phase delay, and a target loss from the first loss and the second loss;
setting the phase modulator and the attenuator based on the target phase delay and the target loss, respectively.
Optionally, a connection device with impedance is connected in series between the port of the device under test and the matching device.
Optionally, obtaining a second phase delay and a second loss of the receiving port extending to the matching device includes: and acquiring a second phase delay and a second loss when the receiving port extends to a matching device, wherein the port of the device to be tested and the matching device are in a disconnected state.
Optionally, the setting the phase modulator and the attenuator based on the target phase delay and the target loss respectively includes: respectively determining corresponding phase adjustment parameters and loss adjustment parameters based on the target phase delay and the target loss; and inputting the phase adjusting parameter and the loss adjusting parameter into the phase modulator and the attenuator respectively, so that a first theoretical impedance of the receiving port extending to a matching device is measured through the measuring receiver, and the first theoretical impedance of the receiving port extending to a port of a device to be tested is the same as a second theoretical impedance of the receiving port extending to the port of the device to be tested.
Optionally, the determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss comprises: a difference between the first phase delay and the second phase delay is taken as a target phase delay, and a difference between the first loss and the second loss is taken as a target loss.
Optionally, after the setting the phase modulator and the attenuator based on the target phase delay and the target loss respectively, the setting includes: and after the matching device corresponding to the extension position of the receiving port is replaced, displaying a corresponding matching debugging result.
Optionally, the network analyzer includes at least two receiving ports and at least two measuring receivers, one receiving port corresponds to one measuring receiver, and a corresponding phase modulator and an attenuator are respectively disposed between each receiving port and the corresponding measuring receiver.
In a second aspect, an embodiment of the present application provides a phase simulation apparatus applied to a network analyzer, where the network analyzer includes at least a phase modulator and an attenuator that are arranged in series between a receiving port and a measurement receiver, and the apparatus includes:
the data acquisition module is used for acquiring first phase delay and first loss of the receiving port extending to a port of a device to be tested, and acquiring second phase delay and second loss of the receiving port extending to a matching device;
a data calculation module for determining a target phase delay from the first phase delay and the second phase delay, and a target loss from the first loss and the second loss;
a setting module, configured to set the phase modulator and the attenuator based on the target phase delay and the target loss, respectively.
In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and execute the steps of the above-mentioned method.
In a fourth aspect, embodiments of the present application provide a terminal, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor executes the computer program to implement the steps of the method described above.
The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:
the application provides a phase simulation method, which comprises the steps of firstly obtaining first phase delay and first loss of a receiving port extending to a port of a device to be tested, and obtaining second phase delay and second loss of the receiving port extending to a matching device; then determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss; and finally, respectively setting a phase adjuster and an attenuator based on target phase delay and target loss, so that phase simulation is realized, and phase transformation of impedance at different positions is also realized through the phase simulation. The phase-adjusting device and the attenuator can be set according to phase delay data and loss data of the receiving port extending to different positions, so that impedance positions of different positions can be obtained through phase simulation after the port extending position of the network analyzer is changed, and matching and debugging can be conveniently carried out at different positions.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a system interaction diagram of a phase simulation method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a phase simulation method according to another embodiment of the present application;
fig. 2A is a schematic structural diagram of a network analyzer according to another embodiment of the present application;
fig. 3 is a schematic structural diagram of a dut and a matching device according to another embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a noise figure circle and a gain circle provided in another embodiment of the present application;
fig. 5 is a schematic structural diagram of a phase simulation apparatus according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a network analyzer according to another embodiment of the present application.
Detailed Description
In order to make the features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a system interaction diagram of a phase simulation method according to an embodiment of the present disclosure.
It should be noted that the execution main body in the embodiment of the present application may be, for example, a Central Processing Unit (CPU) or other integrated circuit chip in a network analyzer in terms of hardware, and may be, for example, a service related to a phase simulation method in the network analyzer in terms of software, which is not limited to this. In the embodiment of the present application, the network analyzer at least includes a phase modulator and an attenuator arranged in series between the receiving port and the measurement receiver, and the system interaction process in the phase simulation method is described below by taking the implementation subject as a processor in the network analyzer as an example.
As shown in fig. 1, the system interaction in the embodiment of the present application includes:
s101, a user extends a receiving port of the network analyzer to a port of the device to be tested.
S102, the processor obtains a first phase delay and a first loss of the receiving port extending to the port of the device to be tested.
S103, the user extends the receiving port of the network analyzer to the matching device.
Wherein a connecting device with impedance is connected in series between the port of the device to be tested and the matching device.
And S104, the processor acquires a second phase delay and a second loss of the receiving port extending to the matching device.
Optionally obtaining a second phase delay and a second loss at the receive port extending to the matching device, comprising: and acquiring a second phase delay and a second loss when the receiving port extends to the matching device, wherein the port of the device to be tested and the matching device are in a disconnected state.
And S105, determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss.
Optionally, determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss, comprises: the difference between the first phase delay and the second phase delay is taken as a target phase delay, and the difference between the first loss and the second loss is taken as a target loss.
And S106, setting the phase adjuster and the attenuator respectively based on the target phase delay and the target loss.
Optionally, the setting the phase adjuster and the attenuator based on the target phase delay and the target loss respectively includes: respectively determining corresponding phase adjustment parameters and loss adjustment parameters based on the target phase delay and the target loss; and respectively inputting the phase adjustment parameter and the loss adjustment parameter into the phase modulator and the attenuator so that a first theoretical impedance extending from the receiving port to the matching device is measured by the measuring receiver and is the same as a second theoretical impedance extending from the receiving port to the device to be measured by the measuring receiver.
Optionally, the number of the matching devices is at least two, and after the phase adjuster and the attenuator are respectively set based on the target phase delay and the target loss, the method includes: and after the matching device corresponding to the extension position of the receiving port is replaced, displaying a corresponding matching debugging result.
Optionally, the network analyzer includes at least two receiving ports and at least two measuring receivers, one receiving port corresponds to one measuring receiver, and a corresponding phase modulator and an attenuator are respectively disposed between each receiving port and the corresponding measuring receiver.
In the embodiment of the application, first phase delay and first loss of a receiving port extending to a port of a device to be tested are obtained, and second phase delay and second loss of the receiving port extending to a matching device are obtained; then determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss; and finally, respectively setting a phase adjuster and an attenuator based on target phase delay and target loss, so that phase simulation is realized, and phase transformation of impedance at different positions is also realized through the phase simulation. The phase-adjusting device and the attenuator can be set according to the phase delay data and the loss data of the receiving port extending to different positions, so that after the port extending position of the network analyzer is changed, the positions of the impedances at different positions can be obtained through phase simulation, and matching debugging at different positions is facilitated.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a phase simulation method according to another embodiment of the present application.
As shown in fig. 2, the method includes:
s201, obtaining a first phase delay and a first loss of a receiving port extending to a port of a device to be tested, and obtaining a second phase delay and a second loss of the receiving port extending to a matching device.
In an embodiment of the present application, the phase simulation method is mainly applied to a network analyzer, wherein the network analyzer can be used for characterizing a Radio Frequency (RF) device. Since rf circuits require unique testing methods and it is difficult to measure voltage and current directly at high frequencies, high frequency devices must be characterized by their response to rf signals when they are measured. The network analyzer may perform characterization of the device by sending a known signal to the device and then ratioing the input signal and the output signal. Early network analyzers measured only amplitude. These scalar network analyzers can measure return loss, gain, standing wave ratio, and perform some other amplitude-based measurement. Today, most network analyzers are vector network analyzers — both amplitude and phase can be measured simultaneously. The vector network analyzer is a very widely used instrument, and can represent S parameters, match complex impedance, perform time domain measurement and the like.
Referring to fig. 2A, fig. 2A is a schematic structural diagram of a network analyzer according to another embodiment of the present application.
As shown in fig. 2A, the network analyzer 200 includes at least a phase modulator 230 and an attenuator 240 disposed in series between the receiving port 210 and the measurement receiver 220. Further, to ensure that the network analyzer can work properly, the network analyzer can further include a signal source 250, a power divider/switch 260, a reference receiver 270, a source attenuator 280, and a coupling circuit module 290. One end of the signal source 250 is connected to the power distribution/switch 260, the signal source 250 is used to provide a test signal, since the network analyzer can perform a ratio measurement on an input signal and an output signal input to a device to be tested, the reference receiver 270 in the network analyzer at least includes a first reference receiver 2701 and a second reference receiver 2702, the source attenuator 280 at least includes a first attenuator 2801 and a second source attenuator 2802, the coupling circuit module 290 at least includes a first coupling circuit module 2901 and a second coupling circuit module 2902, the power distribution/switch 260 is respectively connected to the first reference receiver 2701, the second reference receiver 2702, the first attenuator 2801 and the second source attenuator 2802, the first attenuator 2801 is connected to the first coupling circuit module 2901, and the second source attenuator 2802 is connected to the second coupling circuit module 2902.
Further, the receiving port 210 also includes at least a first receiving port 2101 and a second receiving port 2102, the phase modulator 230 also includes at least a first phase modulator 2301 and a second phase modulator 2302, the attenuator 240 also includes at least a first attenuator 2401 and a second attenuator 2402, and the measurement receiver 220 also includes at least a first measurement receiver 2201 and a second measurement receiver 2202. First coupling circuit module 2901 is connected to first receiving port 2101, first receiving port 2101 is further connected to first phase modulator 2301, first phase modulator 2301 is connected to first attenuator 2401, and first attenuator 2401 is connected to first measurement receiver 2201. Second coupling circuit module 2902 is connected to a second receiving port 2202, second receiving port 2202 being further connected to a second phase modulator 2302, second phase modulator 2302 being connected to a second attenuator 2402, second attenuator 2402 being connected to second measurement receiver 2202.
After a signal is sent by a signal source, the power distribution/switch selects the power and selectively distributes the power to a test line, the first test line introduces a test process by way of example, the first test line comprises a first attenuator, a first coupling circuit module, a first receiving port, a first phase modulator, a second attenuator and a second measurement receiver, the first test line can send a test signal debugged by the first source attenuator to a device to be tested through the first coupling circuit module and the first receiving port, and receive a signal reflected by the device to be tested through the first coupling circuit module and the first receiving port, the signal is transmitted to the first measurement receiver through the first phase modulator and the first attenuator, and the signal received by the first measurement receiver is a signal reflected by the device to be tested and debugged by the first phase modulator and the first attenuator, and can be compared with an original signal received by a first reference receiver.
Optionally, a second test line is formed by a second attenuator, a second coupling circuit module, a second receiving port, a second phase modulator, a second attenuator, and a second measurement receiver, and the test principle of the second test line is the same as that of the first test line, which is not described herein again.
In the related art, in order to match and debug the device to be tested, that is, to adjust the external impedance of the device to be tested to the theoretical impedance, a plurality of matching devices need to be disposed near the device to be tested, wherein a connecting device having impedance is connected in series between the device to be tested and the matching devices.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a device under test and a matching device according to another embodiment of the present application.
As shown in fig. 3, a plurality of matching devices 320 are disposed near the device under test 310, and the device under test 310 may be various amplifiers, such as a power amplifier, or a low noise amplifier. The connector 330 with impedance may be a length of impedance line 3301 and a straight-through blocking capacitor 3302. When matching and debugging the amplifier, it is desirable to adjust the impedance to a corresponding position where the Loadpull performance of the power amplifier is better, or a position of a minimum noise coefficient circle of the low noise amplifier. As shown in fig. 4, fig. 4 is a schematic diagram of a noise figure circle and a gain circle according to another embodiment of the present application, when we want to adjust the impedance of the port of the low noise amplifier to a dashed line region between the minimum noise figure circle and the gain circle, the impedance of the dashed line region is also the theoretical impedance of the device under test.
In order to facilitate debugging, the matching devices connected in series with the device to be tested can be disconnected, the network analyzer is subjected to port extension (port extension), the receiving port extends to the first serial matching bit bonding pad across the connecting device with impedance, different matching devices can be tested conveniently, at the moment, the matching devices are close to the receiving port during debugging, and when the matching devices are changed, the position trend of the impedance position on a Smith chart is consistent with theory. It is known that the theoretical impedance of the low noise amplifier at the port is in the dashed line region of fig. 4, and the theoretical impedance includes the connection device with impedance, but the receiving port is located at the matching bit pad across the connection device with impedance after extension, and due to the impedance influence of the connection device, the position of the theoretical impedance at this position is unclear, and the approximate phase can only be determined by looking at the difference between the impedance of the port of the low noise amplifier after fixed matching and the impedance of the port extension position, and the theoretical impedance at the extension cannot be accurately determined.
Therefore, in the embodiment of the present application, a first phase delay and a first loss of the receiving port extending to the port of the device under test may be obtained, and a second phase delay and a second loss of the receiving port extending to the matching device may be obtained. The method includes the steps that a phase delay measurement function and a loss measurement function of a network analyzer can be used for respectively measuring first phase delay and first loss of a receiving port extending to a port of a device to be measured, the first phase delay and the first loss of the receiving port extending to the port of the device to be measured are obtained, then the port of the device to be measured can be disconnected with a matching device, namely the port of the device to be measured and the matching device are in a disconnected state, the receiving port of the network analyzer can also extend to any one matching device across a connecting device with impedance, namely the receiving port does not measure the impedance of the connecting device, and at the moment, the phase delay measurement function and the loss measurement function of the network analyzer can also be used for obtaining second phase delay and second loss of the receiving port extending to the matching device.
S202, determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss.
Optionally, since the receiving port of the network analyzer is located at the port of the device to be tested and then at the matching device, the difference between the two extensions of the receiving port is that after the receiving port is located at the matching device, the receiving port does not measure the impedance of the connection device, so that the phase delay and the loss corresponding to the impedance of the connection device can be determined according to the phase delay data and the loss data after the two extensions of the receiving port, that is, the target phase delay is determined according to the first phase delay and the second phase delay, and the target loss is determined according to the first loss and the second loss, including: the difference between the first phase delay and the second phase delay is taken as a target phase delay, and the difference between the first loss and the second loss is taken as a target loss.
And S203, setting the phase adjuster and the attenuator respectively based on the target phase delay and the target loss.
Specifically, after determining that the impedance of the connecting device corresponds to the target phase delay and the target loss, the signal received by the measuring receiver at the position where the receiving port extends to the matching device can be adjusted through the phase modulator and the attenuator which are connected in series between the receiving port and the measuring receiver, so that the adjusted external impedance (theoretical impedance) of the device to be measured is the same as the theoretical impedance of the position where the receiving port of the network analyzer extends to the device to be measured, and the effect of simulating the connecting device with the impedance through the phase modulator and the attenuator which are connected in series between the receiving port and the measuring receiver is realized.
Specifically, the phase adjusting parameters and the loss adjusting parameters corresponding to the phase modulator and the attenuator can be respectively determined based on the target phase delay and the target loss, and then the phase adjusting parameters and the loss adjusting parameters are respectively input into the phase modulator and the attenuator, and the phase modulator and the attenuator operate according to the phase adjusting parameters and the loss adjusting parameters, so that the first theoretical impedance of the receiving port extending to the matching device is measured through the measuring receiver, and the first theoretical impedance of the receiving port extending to the port of the device to be tested is the same as the second theoretical impedance of the receiving port extending to the port of the device to be tested, namely, the phase simulation in the testing process of the device to be tested is realized through the adjustment of the phase modulator and the attenuator, wherein the phase modulator and the attenuator can be considered as actions corresponding to the phase simulation.
Optionally, the number of the matching devices is at least two, so that the user can replace the matching devices of the device to be tested, perform matching debugging on the device to be tested after replacing the matching devices corresponding to the extension positions of the receiving ports, and also can obtain matching debugging results and display the corresponding matching debugging results.
In the application, first phase delay and first loss of a receiving port extending to a port of a device to be tested are obtained, and second phase delay and second loss of the receiving port extending to a matching device are obtained; then determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss; and finally, respectively setting a phase adjuster and an attenuator based on target phase delay and target loss, so that phase simulation is realized, and phase transformation of impedance at different positions is also realized through the phase simulation. The phase-adjusting device and the attenuator can be set according to phase delay data and loss data of the receiving port extending to different positions, so that impedance positions of different positions can be obtained through phase simulation after the port extending position of the network analyzer is changed, and matching and debugging can be conveniently carried out at different positions.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a phase simulation device according to another embodiment of the present application.
As shown in fig. 5, the phase simulation apparatus 500 is applied to a network analyzer, the network analyzer at least includes a phase modulator and an attenuator which are arranged in series between a receiving port and a measurement receiver, and the phase simulation apparatus 500 includes:
the data obtaining module 510 is configured to obtain a first phase delay and a first loss of the receiving port extending to the port of the device under test, and obtain a second phase delay and a second loss of the receiving port extending to the matching device.
And a connecting device with impedance is connected in series between the port of the device to be tested and the matching device. The network analyzer at least comprises two receiving ports and at least two measuring receivers, wherein one receiving port corresponds to one measuring receiver, and a corresponding phase modulator and an attenuator are respectively arranged between each receiving port and the corresponding measuring receiver.
The data obtaining module 510 is further configured to obtain a second phase delay and a second loss when the receiving port extends to the matching device, where the port of the device under test and the matching device are in an off state.
A data calculation module 520 for determining a target phase delay based on the first phase delay and the second phase delay, and determining a target loss based on the first loss and the second loss.
The data calculation block 520 is further configured to use a difference between the first phase delay and the second phase delay as a target phase delay and a difference between the first loss and the second loss as a target loss.
A setting module 530, configured to set the phase adjuster and the attenuator based on the target phase delay and the target loss, respectively.
The setting module 530 is further configured to determine corresponding phase adjustment parameters and loss adjustment parameters based on the target phase delay and the target loss, respectively; and respectively inputting the phase adjusting parameter and the loss adjusting parameter into the phase modulator and the attenuator so that a first theoretical impedance of the receiving port extending to the matching device measured by the measuring receiver is the same as a second theoretical impedance of the receiving port extending to the port of the device to be measured by the measuring receiver.
The setting module 530 is further configured to display a corresponding matching debugging result after replacing the matching device corresponding to the extended position of the receiving port.
In an embodiment of the present application, a phase simulation apparatus includes: the data acquisition module is used for acquiring first phase delay and first loss of a receiving port extending to a port of a device to be tested, and acquiring second phase delay and second loss of the receiving port extending to a matching device; the data calculation module is used for determining a target phase delay according to the first phase delay and the second phase delay and determining a target loss according to the first loss and the second loss; and the setting module is used for respectively setting the phase adjuster and the attenuator based on the target phase delay and the target loss, so that phase simulation is realized, and phase transformation of impedance at different positions is also realized through the phase simulation. The phase-adjusting device and the attenuator can be set according to phase delay data and loss data of the receiving port extending to different positions, so that impedance positions of different positions can be obtained through phase simulation after the port extending position of the network analyzer is changed, and matching and debugging can be conveniently carried out at different positions.
Embodiments of the present application further provide a computer storage medium, which stores a plurality of instructions adapted to be loaded by a processor and execute the steps of the pop-up method in the foregoing embodiments.
Further, please refer to fig. 6, where fig. 6 is a schematic structural diagram of a network analyzer according to another embodiment of the present application. As shown in fig. 6, the network analyzer 600 may include: at least one central processor 601, at least one network interface 604, a user interface 603, a memory 605, sensors 606, at least one communication bus 602.
Network analyzer 600 may also include a phase modulator and an attenuator disposed in series between the receive port and the measurement receiver.
Wherein a communication bus 602 is used to enable the connection communication between these components.
The user interface 603 may include a screen (Display) and a Camera (Camera), and the optional user interface 603 may also include a standard wired interface and a wireless interface.
The network interface 604 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface).
Central processor 601 may include one or more processing cores, among others. The central processor 601 connects various parts within the overall network analyzer 600 using various interfaces and lines, and performs various functions of the network analyzer 600 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 605, and calling data stored in the memory 605. Alternatively, the central Processing unit 601 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The Central Processing Unit 601 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the central processor 601, but may be implemented by a single chip.
The Memory 605 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 605 includes a non-transitory computer-readable medium. The memory 605 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 605 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 605 may alternatively be at least one storage device located remotely from the central processor 601. As shown in fig. 6, the memory 605, which is a type of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a phase simulation program.
In the network analyzer 600 shown in fig. 6, the user interface 603 is mainly used as an interface for providing input for a user to obtain data input by the user; the central processing unit 601 may be configured to call the phase simulation program stored in the memory 605, and specifically perform the following operations:
acquiring a first phase delay and a first loss of a receiving port extending to a port of a device to be tested, and acquiring a second phase delay and a second loss of the receiving port extending to a matching device;
determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss;
the phase adjuster and the attenuator are set based on the target phase delay and the target loss, respectively.
And a connecting device with impedance is connected in series between the port of the device to be tested and the matching device.
Optionally, obtaining a second phase delay and a second loss at the receive port extending to the matching device comprises: and acquiring a second phase delay and a second loss when the receiving port extends to the matching device, wherein the port of the device to be tested and the matching device are in a disconnected state.
Optionally, the setting the phase adjuster and the attenuator based on the target phase delay and the target loss respectively includes: respectively determining corresponding phase adjustment parameters and loss adjustment parameters based on the target phase delay and the target loss; and respectively inputting the phase adjusting parameter and the loss adjusting parameter into the phase modulator and the attenuator so that a first theoretical impedance of the receiving port extending to the matching device measured by the measuring receiver is the same as a second theoretical impedance of the receiving port extending to the port of the device to be measured by the measuring receiver.
Optionally, determining a target phase delay according to the first phase delay and the second phase delay, and determining a target loss according to the first loss and the second loss comprises: the difference between the first phase delay and the second phase delay is taken as a target phase delay, and the difference between the first loss and the second loss is taken as a target loss.
Optionally, the number of the matching devices is at least two, and after the phase adjuster and the attenuator are respectively set based on the target phase delay and the target loss, the method includes: and after the matching device corresponding to the extension position of the receiving port is replaced, displaying a corresponding matching debugging result.
Optionally, the network analyzer includes at least two receiving ports and at least two measuring receivers, one receiving port corresponds to one measuring receiver, and a corresponding phase modulator and an attenuator are respectively disposed between each receiving port and the corresponding measuring receiver.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In view of the above description of the phase simulation method, apparatus, storage medium and network analyzer provided by the present application, those skilled in the art will recognize that there may be variations in the embodiments and applications of the method and apparatus according to the teachings of the present application.

Claims (10)

1. A phase simulation method applied to a network analyzer, the network analyzer including at least a phase modulator and an attenuator arranged in series between a receiving port and a measurement receiver, the method comprising:
acquiring a first phase delay and a first loss of the receiving port extending to a port of a device to be tested, and acquiring a second phase delay and a second loss of the receiving port extending to a matching device;
determining a target phase delay from the first phase delay and the second phase delay, and determining a target loss from the first loss and the second loss;
setting the phase modulator and the attenuator based on the target phase delay and the target loss, respectively.
2. The method according to claim 1, characterized in that a connecting device with impedance is connected in series between the device under test port and the matching device.
3. The method of claim 2, wherein obtaining a second phase delay and a second loss for the receive port extending to a matching device comprises:
and acquiring a second phase delay and a second loss of the receiving port extending to a matching device, wherein the port of the device to be tested and the matching device are in a disconnected state.
4. The method of claim 3, wherein the setting the phase modulator and the attenuator based on the target phase delay and the target loss, respectively, comprises:
respectively determining corresponding phase adjustment parameters and loss adjustment parameters based on the target phase delay and the target loss;
and inputting the phase adjusting parameter and the loss adjusting parameter into the phase modulator and the attenuator respectively, so that a first theoretical impedance of the receiving port extending to a matching device is measured through the measuring receiver, and the first theoretical impedance of the receiving port extending to a port of a device to be tested is the same as a second theoretical impedance of the receiving port extending to the port of the device to be tested.
5. The method of claim 1, wherein determining a target phase delay based on the first phase delay and the second phase delay and a target loss based on the first loss and the second loss comprises:
a difference between the first phase delay and the second phase delay is taken as a target phase delay, and a difference between the first loss and the second loss is taken as a target loss.
6. The method of claim 1, wherein the number of matching devices is at least two, and wherein the setting the phase modulator and the attenuator based on the target phase delay and the target loss, respectively, comprises:
and after the matching device corresponding to the extension position of the receiving port is replaced, displaying a corresponding matching debugging result.
7. The method of claim 1, wherein the network analyzer comprises at least two receiving ports and at least two measuring receivers, one receiving port corresponds to one measuring receiver, and a phase modulator and an attenuator are respectively disposed between each receiving port and the corresponding measuring receiver.
8. A phase simulation apparatus applied to a network analyzer, the network analyzer including at least a phase modulator and an attenuator arranged in series between a receiving port and a measurement receiver, the apparatus comprising:
the data acquisition module is used for acquiring first phase delay and first loss of the receiving port extending to a port of a device to be tested, and acquiring second phase delay and second loss of the receiving port extending to a matching device;
a data calculation module for determining a target phase delay from the first phase delay and the second phase delay, and a target loss from the first loss and the second loss;
a setting module, configured to set the phase modulator and the attenuator based on the target phase delay and the target loss, respectively.
9. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method according to any of claims 1 to 7.
10. A network analyser comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor when executing the program performing the steps of the method of any one of claims 1 to 7.
CN202110284393.3A 2021-03-16 2021-03-16 Phase simulation method, phase simulation device, storage medium and network analyzer Pending CN115150006A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110284393.3A CN115150006A (en) 2021-03-16 2021-03-16 Phase simulation method, phase simulation device, storage medium and network analyzer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110284393.3A CN115150006A (en) 2021-03-16 2021-03-16 Phase simulation method, phase simulation device, storage medium and network analyzer

Publications (1)

Publication Number Publication Date
CN115150006A true CN115150006A (en) 2022-10-04

Family

ID=83404193

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110284393.3A Pending CN115150006A (en) 2021-03-16 2021-03-16 Phase simulation method, phase simulation device, storage medium and network analyzer

Country Status (1)

Country Link
CN (1) CN115150006A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060074582A1 (en) * 2004-09-13 2006-04-06 Joel Dunsmore Network analyzer applying loss compensation using port extensions and method of operation
CN101464482A (en) * 2009-01-23 2009-06-24 青岛海信移动通信技术股份有限公司 Method for confirming electromagnetic delay of network analyser and measuring high frequency circuit impedance
TW201132992A (en) * 2009-10-21 2011-10-01 Verigy Pte Ltd Singapore Test device and test method for measuring a phase noise of a test signal
CN104375011A (en) * 2014-11-04 2015-02-25 中国电子科技集团公司第四十一研究所 Random impedance testing circuit and method for vector network analyzer material testing
CN110398678A (en) * 2019-06-11 2019-11-01 西安电子科技大学 A kind of wide impedance ranges test method of large power semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060074582A1 (en) * 2004-09-13 2006-04-06 Joel Dunsmore Network analyzer applying loss compensation using port extensions and method of operation
CN101464482A (en) * 2009-01-23 2009-06-24 青岛海信移动通信技术股份有限公司 Method for confirming electromagnetic delay of network analyser and measuring high frequency circuit impedance
TW201132992A (en) * 2009-10-21 2011-10-01 Verigy Pte Ltd Singapore Test device and test method for measuring a phase noise of a test signal
CN104375011A (en) * 2014-11-04 2015-02-25 中国电子科技集团公司第四十一研究所 Random impedance testing circuit and method for vector network analyzer material testing
CN110398678A (en) * 2019-06-11 2019-11-01 西安电子科技大学 A kind of wide impedance ranges test method of large power semiconductor device

Similar Documents

Publication Publication Date Title
CN107566053B (en) Method and system for testing radio frequency index and computer readable storage medium
CN109582525B (en) Test code verification method, verification device, equipment and storage medium
US9031523B2 (en) Systems and methods for determining antenna impedance
US20170163358A1 (en) Front end module for automatic test equipment
US9176174B1 (en) Systems and methods for simultaneously measuring forward and reverse scattering parameters
JP2015064357A (en) De-embed probe and, test and measurement system
CN110174633B (en) Device parameter measuring method and system and terminal equipment
CN109324248A (en) Integrated vector network analyzer and its test method for data domain analysis
CN210112015U (en) Radio frequency switch chip test system
CN106998232B (en) Method for acquiring load pull parameter of radio frequency power amplifier
US10591522B2 (en) Measurement apparatus
CN110174634B (en) Load traction measurement system and measurement method
Zetterberg Wireless development laboratory (WIDELAB) equipment base
CN105187135B (en) Test the method and system of wireless device
US10469333B2 (en) Network analyzer systems and methods for operating a network analyzer
CN110441621B (en) Method, device, equipment and storage medium for measuring noise coefficient
CN115150006A (en) Phase simulation method, phase simulation device, storage medium and network analyzer
CN107276693B (en) Method, equipment and system for testing radio frequency front end of terminal
US9116187B1 (en) System and method for measuring signal distortion
CN115038978B (en) Noise-independent loss characterization of a network
JP2023547606A (en) System and method for compensating for power loss due to radio frequency (RF) signal probe mismatch in conducted signal testing
CN212723133U (en) Radiation stray testing device and electronic equipment
CN114325312A (en) Chip testing device, chip testing system and data acquisition method
TW201428303A (en) RF probe
JP2021067539A (en) Vector network analyzer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination