CN115148898A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115148898A
CN115148898A CN202110332090.4A CN202110332090A CN115148898A CN 115148898 A CN115148898 A CN 115148898A CN 202110332090 A CN202110332090 A CN 202110332090A CN 115148898 A CN115148898 A CN 115148898A
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layer
electrode
vacancy
barrier layer
oxygen storage
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许博砚
吴伯伦
郭泽绵
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices

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Abstract

The invention relates to a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: the device comprises a substrate, a first electrode, a vacancy supply layer, a side wall barrier layer, an oxygen storage layer, a resistance conversion layer and a second electrode; the first electrode is arranged on the substrate; the vacancy supplying layer is arranged on the first electrode; the side wall barrier layer is arranged on the first electrode; the oxygen storage layer is arranged on the first electrode, and the side wall barrier layer is arranged between the oxygen storage layer and the vacancy supply layer; the resistance conversion layer is arranged on the vacancy supply layer; the second electrode is arranged on the resistance conversion layer. So that the semiconductor structure has both an oxygen ion conduction path and a vacancy conduction path to obtain better electrical characteristics.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to semiconductor structures and methods for forming the same, and more particularly, to a semiconductor structure providing two current paths simultaneously and a method for forming the same.
Background
Generally, electronic memories can be divided into volatile memories and nonvolatile memories. Among non-volatile memories, resistive Random Access Memory (RRAM) has advantages of being capable of performing resistance switching in a very short time, having small operation current and operation voltage, having excellent repetition operation frequency (end) and Memory retention capability (retention), and having a simple structure, and thus has attracted attention.
The behavior of the RRAM in a transition state includes resistive filament shaping (forming) in which current is conducted substantially through a resistive filament path; reset (reset) from a Low Resistance State (LRS) to a high resistance state (HRL); and a setting (set) from a high resistance state to a low resistance state. However, during filament-resistance forming, the low resistance state is easily affected by high temperature to be deteriorated, and not only, the filament-resistance path is easily broken.
Thus, while existing semiconductor structures and methods of forming them have been developed to meet their intended purpose, they have not been completely satisfactory in every aspect. Accordingly, there are still some problems to be overcome in the semiconductor structure and the method for forming the same, which can be used as the RRAM after further processing.
Disclosure of Invention
In view of the above problems, the present invention discloses that an oxygen storage layer (oxygen storage layer) is disposed under a resistance switching layer (resistive switching layer), and a vacancy supplying layer (vacancy supported layer) surrounded by a barrier layer as an oxygen diffusion barrier layer is disposed under the resistance switching layer, so that the semiconductor structure has both an oxygen ion conduction path and a vacancy conduction path to obtain more excellent electrical characteristics.
According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: the structure comprises a substrate, a first electrode, a vacancy supply layer, a side wall barrier layer, an oxygen storage layer, a resistance conversion layer and a second electrode; the first electrode is arranged on the substrate; the vacancy supply layer is arranged on the first electrode; the side wall barrier layer is arranged on the first electrode; the oxygen storage layer is arranged on the first electrode, and the side wall barrier layer is arranged between the oxygen storage layer and the vacancy supply layer; the resistance conversion layer is arranged on the vacancy supply layer; the second electrode is arranged on the resistance conversion layer.
According to some embodiments, a method of forming a semiconductor structure is provided. The method for forming the semiconductor structure comprises forming a first electrode on a substrate; forming a vacancy-supplying layer on the first electrode; forming a sidewall barrier layer on the first electrode; forming an oxygen storage layer over the first electrode such that the sidewall barrier layer is between the oxygen storage layer and the vacancy-supplying layer; forming a resistance conversion layer on the vacancy-supplying layer; and forming a second electrode on the resistance conversion layer.
In an environment of applying a reverse voltage, the semiconductor device disclosed by the invention forms an oxygen ion conduction path through the oxygen storage layer arranged below the resistance conversion layer, and forms a vacancy conduction path through the vacancy supply layer arranged below the resistance conversion layer and surrounded by the oxygen diffusion barrier layer, so that the semiconductor structure simultaneously has the oxygen ion conduction path and the vacancy conduction path, and further improves conduction current to obtain better electrical characteristics. In addition, because two conduction paths exist in the semiconductor structure of the invention at the same time, the reliability of the semiconductor structure and the forming method thereof can be improved.
The present disclosure may be embodied in many different forms of semiconductor devices, and the features and advantages of the present disclosure will be apparent from the following detailed description, which, taken in conjunction with the annexed drawings, discloses preferred embodiments.
Drawings
The drawings are only for purposes of illustrating and explaining the present invention and are not to be construed as limiting the scope of the present invention. Wherein:
FIGS. 1-8 are schematic cross-sectional views illustrating the formation of a semiconductor structure at various stages according to some embodiments of the present disclosure; and
fig. 9 is a cross-sectional view of a semiconductor structure during wire-stopping (forming) in operation, according to some embodiments of the present disclosure.
The reference numbers indicate:
1: semiconductor structure
100: substrate board
102: a first dielectric layer
110: first contact plug
200: a first electrode
300: bottom barrier layer
400: vacancy-providing layer
410: sidewall barrier layer
500: oxygen storage layer
600: resistance conversion layer
700: a second electrode
800: a second dielectric layer
810: second contact plug
AA': normal line
CT: through hole
Detailed Description
In order to clearly understand the technical solution, the purpose and the effect of the present invention, a detailed description of the present invention will be described with reference to the accompanying drawings.
Fig. 1-8 are schematic cross-sectional views illustrating a semiconductor structure 1 formed at various stages according to some embodiments of the present disclosure.
Referring to fig. 1, in some embodiments, a first dielectric layer 102 is formed on a substrate 100, and a first contact plug 110 is formed in the first dielectric layer 102. Generally, semiconductor-on-insulator substrates include a layer of semiconductor material formed on an insulating layer. In some embodiments, the substrate 100 may be an elemental semiconductor comprising silicon (silicon), germanium (germanium); the substrate 100 may also be a compound semiconductor, which includes: for example, but not limited to, silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide); the substrate 100 may also be an alloy semiconductor, which includes: for example, but not limited to, silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or any combination thereof. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate. In some embodiments, the first dielectric layer 102 may comprise or may be silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a combination thereof, or any other suitable dielectric material, but the disclosure is not limited thereto.
In some embodiments, the first dielectric layer 102 may be formed on the substrate 100 by a deposition process.
In some embodiments, the first dielectric layer 102 is patterned after forming the first dielectric layer 102 on the substrate 100 and before forming other layers on the first dielectric layer 102 to form a first via in the first dielectric layer 102. The patterning process may be performed by a hard mask and/or a photoresist layer comprising an oxide, a nitride, or a combination thereof, in conjunction with an etching process, but the disclosure is not limited thereto. In addition, in some embodiments, the photoresist layer may be further removed by performing an ashing (ashing) process and/or a wet strip (wet strip) process.
Then, the first conductive material is filled in the first via hole, and a planarization process is further performed to remove the first conductive material on the first dielectric layer 102, so that the top surface of the first conductive material filled in the first via hole is coplanar with the top surface of the first dielectric layer 102, thereby forming a first contact plug 110 in the first dielectric layer 102. In some embodiments, the first via hole has a gradually increasing width along a direction away from the first dielectric layer 102, in other words, the first via hole may have a structure with a wide top and a narrow bottom. In some embodiments, the first conductive material may include or may be a metal material, a conductive material, a combination thereof, or other suitable materials, but the disclosure is not limited thereto.
As shown in fig. 1, in some embodiments, a first electrode 200 is formed on the substrate 10, specifically, on the first dielectric layer 102. In some embodiments, the first electrode 200 is formed on the first dielectric layer 102 and the first contact plug 110 disposed in the first dielectric layer 102, such that the first electrode 200 is in contact with and electrically connected to the first contact plug 110. In some embodiments, the first electrode 200 may include or may be a conductive material, which may include polysilicon (polycrystalline silicon), amorphous silicon (amorphous silicon), a metal nitride, a conductive metal oxide, a combination thereof, or other suitable materials, but the disclosure is not limited thereto. In some embodiments, the first electrode 200 may be formed on the first dielectric layer 102 by the aforementioned deposition process or other suitable process.
As shown in fig. 1, in some embodiments, the bottom barrier layer 300 is formed on the first electrode 200 such that the first electrode 200 is between the substrate 100 and the bottom barrier layer 300. In some embodiments, the first dielectric layer 102 is disposed on the first electrode 200, and the first electrode 200 is disposed between the first dielectric layer 102 and the bottom barrier layer 300. In some embodiments, the bottom barrier layer 300 is located between the first electrode 200 and a subsequently formed vacancy-donating layer and between the first electrode 200 and a subsequently formed oxygen-storage layer. In some embodiments, the bottom barrier layer 300 may comprise an oxide, a nitride, a combination thereof, or other suitable material capable of blocking oxygen ion diffusion. In some embodiments, the bottom barrier layer 300 may comprise or may be aluminum oxide (Al) 2 O 3 ) And/or zirconium oxide (ZrO).
In some embodiments, the bottom barrier layer 300 may act as an oxygen diffusion barrier (oxygen diffusion barrier layer) that blocks the diffusion of oxygen ions (oxygen ions), and thus, the bottom barrier layer 300 may prevent oxygen ions from crossing the bottom barrier layer 300. In some embodiments, since the subsequently formed oxygen storage layer and the subsequently formed resistance conversion layer are in contact with each other, oxygen ions from the resistance conversion layer can diffuse to the oxygen storage layer. For example, the resistance conversion layer is disposed on one side of the bottom barrier layer 300 disposed on the oxygen storage layer, but the disclosure is not limited thereto. Therefore, after the oxygen ions from the resistance conversion layer diffuse into the oxygen storage layer, the bottom barrier layer 300 can prevent the oxygen ions from further diffusing from the oxygen storage layer into the bottom barrier layer 300.
As shown in fig. 1, in some embodiments, a vacancy-supplying layer (vacancy-supplied layer) 400 is formed on the first electrode 200, specifically, on the bottom barrier layer 300. In some embodiments, the vacancy-supplying layer 400 may be formed on the bottom barrier layer 300 by the aforementioned deposition process or other suitable method. In some embodiments, the vacancy-supplying layer 400 may comprise or may be an oxide. In some embodiments, the vacancy supplying layer 400 may be tantalum oxide (TaO) and/or hafnium oxide (HfO). In some embodiments, the vacancy-providing layer 400 is used to provide vacancies (vacancies) capable of establishing conductive paths.
Referring to fig. 2, in some embodiments, the vacancy-supplying layer 400 is patterned correspondingly according to the position where the first contact plug 110 is disposed in the first dielectric layer 102, so as to define a memory cell (memory cell) of a subsequently formed resistive random access memory. In some embodiments, a patterning process is performed to remove the vacancy supplying layer 400 that does not correspond to the first contact plug 110 and to leave the vacancy supplying layer that corresponds to the first contact plug 110. Accordingly, the vacancy supplying layer 400 may be disposed corresponding to the first contact plug 110, and the subsequently formed second contact plug 810 may be disposed corresponding to the vacancy supplying layer 400 and the first contact plug 110, such that the vacancy supplying layer 400 is disposed between the first contact plug 110 and the subsequently formed second contact plug to obtain the maximum electric field. In some embodiments, the vacancy supplying layer 400 may be disposed on the first contact plug 110, and particularly, the vacancy supplying layer 400 may be disposed above the first contact plug 110. In some embodiments, the projected area of the vacancy-supplying layer 400 covers the top surface of the first contact plug 110. In some embodiments, the projected area of the vacancy-supplying layer 400 is greater than or equal to the area of the top surface of the first contact plug 110.
In some embodiments, as shown in fig. 2, a sidewall barrier layer 410 is formed on the first electrode 200, specifically, on the bottom barrier layer 300. In some embodiments, the sidewall barrier layer 410 is conformally formed on the top surface of the bottom barrier layer 300 and on the top and side surfaces of the vacancy supplying layer 400, such that the bottom barrier layer 300 and sidewall barrier layer 410 surround the vacancy supplying layer 400. In some embodiments, the vacancy-providing layer 400 is received in the space formed by the bottom barrier layer 300 and the sidewall barrier layer 410. In some embodiments, optionally, the sidewall barrier layer 410 on the top surface of the bottom barrier layer 300 is further removed by performing an etching process, and the sidewall barrier layer 410 on the top surface and side surfaces of the vacancy-providing layer 400 remains.
In some embodiments, the sidewall barrier layer 410 may also act as an oxygen diffusion barrier to oxygen ion diffusion, and thus, the sidewall barrier layer 410 may also prevent oxygen ions from crossing the sidewall barrier layer 410. In some embodiments, the sidewall barrier layer 410 is disposed between the bottom barrier layer 300 and the resistance transforming layer 600 formed subsequently; the bottom surface of sidewall barrier layer 410 contacts bottom barrier layer 300; and the top surface of the sidewall barrier layer 410 contacts the resistance transforming layer 600 formed subsequently, so the sidewall barrier layer 410 effectively divides the space between the bottom barrier layer 300 and the resistance transforming layer 600 formed subsequently. In some embodiments, the sidewall barrier layer 410 may comprise the same or different material as the bottom barrier layer 300. In some embodiments, the sidewall barrier layer 410 may comprise an oxide, nitride, combinations thereof, or other materials capable of blocking the diffusion of oxygen ions. In some embodiments, the sidewall barrier layer 410 may comprise or may be aluminum oxide and/or zirconium oxide.
Referring to fig. 3 and 4, in some embodiments, an oxygen storage layer (oxygen reservoir layer) 500 is formed on the first electrode 200, specifically, on the bottom barrier layer 300, such that the sidewall barrier layer 410 is between the oxygen storage layer 500 and the vacancy supplying layer 400. In some embodiments, the step of forming the oxygen storage layer 500 on the first electrode 200 may include: an oxygen storage layer 500 is formed on the sidewall barrier layer 410 and a planarization process is performed to remove a portion of the oxygen storage layer 500 and a portion of the sidewall barrier layer 410, as shown in figure 4, such that the top surfaces of the sidewall barrier layer 410, the vacancy-supplying layer 400, and the oxygen storage layer 500 are coplanar. In other words, the planarization process further includes removing the sidewall barrier layer 410 on the top surface of the vacancy supplying layer 400, in addition to removing a portion of the oxygen storage layer 500, to expose the upper surface of the vacancy supplying layer 400, and to interpose the sidewall barrier layer 410 between the oxygen storage layer 500 and the vacancy supplying layer 400. In some embodiments, the oxygen storage layer 500 is located under a subsequently formed resistance switching layer, and the oxygen storage layer 500 may surround the vacancy supplying layer 400. In some embodiments, the vacancy-supplying layer 400 may also surround the oxygen storage layer 500. In some embodiments, the vacancy-supplying layer 400 and the oxygen storage layer 500 are arranged to be staggered with respect to each other.
In some embodiments, the oxygen storage layer 500 may comprise or may be a material capable of storing and/or capturing oxygen ions. In some embodiments, the oxygen storage layer 500 may also serve as an oxygen diffusion barrier (oxygen diffusion barrier layer). In some embodiments, the oxygen storage layer 500 may comprise or may be a metal material, such as, for example, titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), combinations thereof, or other suitable materials, although the disclosure is not limited thereto.
In some embodiments, the bottom barrier layer 300, the sidewall barrier layer 410, and the oxygen storage layer 500 are all disposed on the first electrode 200, and thus a barrier layer for blocking oxygen ion diffusion and a barrier layer for blocking vacancy diffusion may be simultaneously disposed on the first electrode 200. Wherein, the oxygen storage layer 500 and the bottom barrier layer 300 and the sidewall barrier layer 410 under the oxygen storage layer 500 can be used to block the diffusion of oxygen ions; the bottom barrier layer 300 under the vacancy-supplying layer 400 can be used to block vacancy diffusion; and the sidewall barrier layer 410 between the vacancy supplying layer 400 and the oxygen storage layer 500 may block oxygen ion and/or vacancy diffusion. In other words, in some embodiments, the present invention discloses that the diffusion direction of oxygen ions and/or vacancies is limited by the specific arrangement of the bottom barrier layer 300, the vacancy-supplying layer 400, the sidewall barrier layer 410 and the oxygen storage layer 500 to form a semiconductor structure having two current paths.
Referring to fig. 5, a resistance conversion layer 600 is formed on the vacancy-supplying layer 400 such that the resistance conversion layer 600 covers the top surface of the vacancy-supplying layer 400. In some embodiments, the resistive switching layer 600 further covers the top surface of the oxygen storage layer 500 in addition to covering the top surface of the vacancy-supplying layer 400. In some embodiments, the resistance transition layer 600 is disposed between the subsequently formed second electrode and the oxygen storage layer 500, so as to separate the oxygen storage layer 500 from the subsequently formed second electrode. In some embodiments, the resistance transforming layer 600 is formed on the vacancy supplying layer 400, the sidewall barrier layer 410 and the oxygen storage layer 500, that is, the vacancy supplying layer 400 is located below the resistance transforming layer 600, and the bottom barrier layer 300 and the sidewall barrier layer 410 may surround the vacancy supplying layer 400. In some embodiments, the material of the resistive switching layer 600 includes a transitionMetal oxides (transition metal oxides) enable the resistance random access memory to be operated by utilizing the property that the resistance of the transition metal oxide changes with the applied bias voltage to generate different resistances. In some embodiments, the oxygen storage layer 300 is closer to the substrate 100 than the resistance switching layer 600. In some embodiments, the resistance conversion layer 600 may include or may be a metal oxide, for example, hafnium oxide (HfO) 2 ) Zirconium oxide (ZrO) 2 ) Titanium oxide (TiO) 2 ) Tantalum oxide (Ta) 2 O 5 ) However, the present disclosure is not limited thereto.
In some embodiments, the bottom barrier layer 300 is aluminum oxide (Al) 2 O 3 ) (ii) a The vacancy-supplying layer 400 is tantalum oxide (TaO) x ) (ii) a The sidewall barrier layer 410 is aluminum oxide (Al) 2 O 3 ) (ii) a The oxygen storage layer 500 is titanium (Ti); and the resistance conversion layer 600 is hafnium oxide (HfO) 2 ) With alumina (Al) 2 O 3 ) The combination of (2) can produce excellent data preservation effect. In some embodiments, the bottom barrier layer 300 is aluminum oxide (Al) 2 O 3 ) (ii) a Vacancy supplying layer 400 is tantalum oxide (TaO) x ) (ii) a The sidewall barrier layer 410 is aluminum oxide (Al) 2 O 3 ) (ii) a The oxygen storage layer 500 is tantalum oxide (Ta) 2 O 5 ) (ii) a And the resistance conversion layer 600 is hafnium oxide (HfO) 2) The effect of high conversion times can be generated.
As shown in fig. 5, in some embodiments, a second electrode 700 is formed on the resistance conversion layer 600. In some embodiments, the material of the second electrode 700 may be the same as or different from the material of the first electrode 200. In some embodiments, the second electrode 700 may be formed by the aforementioned deposition process or other suitable process.
Referring to fig. 6, in some embodiments, a second dielectric layer 800 is formed on the second electrode 700, and the second electrode 700 is disposed between the second dielectric layer 800 and the resistance value conversion layer 600. In some embodiments, the material of the second dielectric layer 800 may be the same as or different from the material of the first dielectric layer 102. In some embodiments, the second dielectric layer 800 may be formed by the aforementioned deposition process or other suitable process. In some embodiments, after the resistance conversion layer 700 and the second dielectric layer 800 are formed, the range of the memory cell in the resistive random access memory to be formed is defined, and the second via hole CT is formed corresponding to the range of the memory cell to be formed.
Referring to fig. 7, in some embodiments, a second via hole CT is formed in the second dielectric layer 800 to expose a portion of the second electrode 700. In some embodiments, the second via CT penetrates through the second dielectric layer 800 and does not penetrate through the second electrode 700 to expose a portion of the second electrode 700. In some embodiments, the second via CT penetrates through the second dielectric layer 800, further removing a portion of the second electrode 700, and exposing the top surface of the remaining second electrode 700. In some embodiments, the second via hole CT has a width gradually increasing in a direction away from the resistance conversion layer 600, in other words, the second via hole CT may have a structure with a wide top and a narrow bottom. In some embodiments, the second via hole CT may have the same or different shape as the first via hole. In some embodiments, the method of forming the second via CT may be the same as or different from the method of forming the first via CT. In some embodiments, the second via hole CT is formed corresponding to a disposition position of the first contact plug 110.
Referring to fig. 8, in some embodiments, a second conductive material is filled in the second via hole CT to form a second contact plug 810, and a semiconductor structure 1 is obtained. In some embodiments, the second contact plug 810 is disposed in the second dielectric layer 800, and the second contact plug 810 and the second electrode 700 contact each other to be electrically connected. In some embodiments, a planarization process may be further performed after the second conductive material is filled in the second via hole CT.
Referring to fig. 9, a cross-sectional view of a semiconductor structure during filament forming (forming) during operation is shown, in accordance with some embodiments of the present disclosure.
It is noted that, in some embodiments, the vacancy-supplying layer 400 is disposed between the first contact plug 110 and the second contact plug 810. In some embodiments, the vacancy-supplying layer 400, the first contact plug 110, and the second contact plug 810 are aligned in a normal direction with respect to the substrate 100. In some embodiments, as shown in fig. 9, the vacancy-supplying layer 400, the first contact plug 110, and the second contact plug 810 are aligned on the normal line AA'. In some embodiments, the vacancy-supplying layer 400 is located below the first contact plug 110 and above the second contact plug 810. In some embodiments, the vacancy supply layer 400 is located directly below the first contact plug 110 (direct under) and directly above the second contact plug 810 (direct above). In some embodiments, since the vacancy supplying layer 400 is disposed between the first contact plug 110 and the second contact plug 810 and aligned with each other, a maximum electric field can be generated in the semiconductor structure 1, thereby facilitating to rapidly drive vacancies in the vacancy supplying layer 400 into the resistance conversion layer 600.
It is further noted that in some embodiments, the bottom barrier layer 300, the sidewall barrier layer 410 and the resistivity transformation layer 600 effectively isolate the vacancy-accommodating layer 400. In some embodiments, the oxygen ion conduction path allows oxygen ions in the resistive switching layer 600 to move from the second electrode 700 toward the first electrode 200, so as to transmit the oxygen ions in the resistive switching layer 600 to the oxygen storage layer 500. In some embodiments, the vacancy conduction path is formed by allowing the vacancy in the vacancy supplying layer 400 to move from the first electrode 200 toward the second electrode 700, while transferring the vacancy of the vacancy supplying layer 400 into the resistance conversion layer 600.
In some embodiments, when a forward voltage is applied to the semiconductor structure 1, a breakdown path (breakdown path) between the first contact plug 110 and the second contact plug 810 is formed. In some embodiments, when a reverse bias (reverse bias) is applied to the semiconductor structure 1, the vacancy of the vacancy-supplying layer 400 is transferred into the resistance conversion layer 600 to form a vacancy conduction path between the first contact plug 110 and the second contact plug 810, and particularly, a vacancy conduction path is formed at positions corresponding to the first contact plug 110, the vacancy-supplying layer 400 and the second contact plug 810 at the same time. In some embodiments, a conduction path is formed at the interface of the vacancy-providing layer 400 and the resistive switching layer 600. In addition, in addition to the formation of the vacancy conduction path corresponding to the first contact plug 110, the vacancy-supplying layer 400 and the second contact plug 810 at the same time, since a reverse voltage is applied to the semiconductor structure 1, the vacancies in the vacancy-supplying layer 400 are instead driven to move upward, that is, from the first electrode 200 toward the second electrode 700, and thus the oxygen ion conduction path is formed at the interface of the oxygen storage layer 500 and the resistance conversion layer 600, which does not correspond to the first contact plug 110, the vacancy-supplying layer 400 and the second contact plug 810 at the same time. Therefore, in the case where both a vacancy conduction path and an oxygen ion conduction path are included in the semiconductor structure 1 according to some embodiments of the present disclosure, the current in the low resistance state can be increased.
In summary, according to some embodiments of the present disclosure, in an environment where a reverse voltage is applied, the semiconductor device forms an oxygen ion conduction path through the oxygen storage layer disposed below the resistance conversion layer, and forms a vacancy conduction path through the vacancy supply layer disposed below the resistance conversion layer and surrounded by the oxygen diffusion barrier layer, so that the semiconductor structure has both an oxygen ion conduction path and a vacancy conduction path, thereby increasing conduction current and obtaining better electrical characteristics. In addition, since two conduction paths exist in the semiconductor structure according to some embodiments of the present disclosure, the reliability of the semiconductor structure and the method for forming the same can be improved.
The above description is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. Any equivalent changes and modifications that can be made by one skilled in the art without departing from the spirit and principles of the invention should fall within the protection scope of the invention. It should be noted that the components of the present invention are not limited to the above-mentioned whole application, and the technical features described in the present specification can be selected individually or in combination according to actual needs, so that the present invention naturally covers other combinations and specific applications related to the invention.

Claims (10)

1. A semiconductor structure, comprising:
a substrate;
a first electrode disposed on the substrate;
a vacancy supply layer disposed on the first electrode;
a sidewall barrier layer disposed on the first electrode;
an oxygen storage layer disposed on the first electrode, and the sidewall barrier layer disposed between the oxygen storage layer and the vacancy-supplying layer;
a resistance conversion layer disposed on the vacancy-supplying layer; and
a second electrode disposed on the resistance conversion layer.
2. The semiconductor structure of claim 1, wherein the resistivity transforming layer covers the vacancy supplying layer and the oxygen storage layer.
3. The semiconductor structure of claim 1, further comprising:
a bottom barrier layer disposed on the first electrode, and the first electrode is between the substrate and the bottom barrier layer.
4. The semiconductor structure of claim 3, wherein the bottom barrier layer is between the first electrode and the vacancy-supplying layer and between the first electrode and the oxygen-storage layer.
5. The semiconductor structure of claim 1, further comprising:
a first dielectric layer disposed between the substrate and the first electrode;
a first contact plug disposed in the first dielectric layer and contacting the first electrode;
a second dielectric layer disposed on the second electrode, and the second electrode is disposed between the second dielectric layer and the resistance conversion layer; and
and a second contact plug disposed in the second dielectric layer and contacting the second electrode, wherein the vacancy-supplying layer is disposed between the first contact plug and the second contact plug, and the vacancy-supplying layer, the first contact plug and the second contact plug are aligned in a normal direction of the substrate.
6. The semiconductor structure of claim 1, wherein the oxygen storage layer is closer to the substrate than the resistivity switching layer.
7. A method of forming a semiconductor structure, the method comprising:
forming a first electrode on a substrate;
forming a vacancy-supplying layer on the first electrode;
forming a sidewall barrier layer on the first electrode;
forming an oxygen storage layer over the first electrode such that the sidewall barrier layer is between the oxygen storage layer and the vacancy supplying layer;
forming a resistance conversion layer on the vacancy providing layer; and
forming a second electrode on the resistance conversion layer.
8. The method of claim 7, wherein forming the vacancy-supplying layer over the first electrode further comprises:
a bottom barrier layer is formed over the first electrode such that the first electrode is between the substrate and the bottom barrier layer.
9. The method of claim 8, wherein forming the sidewall barrier layer on the first electrode comprises:
the sidewall barrier layer is conformally formed on the top surface of the bottom barrier layer and on the top surface and side surfaces of the vacancy-supplying layer.
10. The method of claim 7, wherein forming the oxygen storage layer over the first electrode comprises:
forming the oxygen storage layer on the barrier layer; and
removing a portion of the oxygen storage layer and a portion of the sidewall barrier layer such that a top surface of the sidewall barrier layer, the vacancy-supplying layer, and the oxygen storage layer are coplanar.
CN202110332090.4A 2021-03-29 2021-03-29 Semiconductor structure and forming method thereof Pending CN115148898A (en)

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Application Number Priority Date Filing Date Title
CN202110332090.4A CN115148898A (en) 2021-03-29 2021-03-29 Semiconductor structure and forming method thereof

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CN115148898A true CN115148898A (en) 2022-10-04

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