CN115148154A - Method and device for compensating phase offset of display panel driving signal and display panel - Google Patents

Method and device for compensating phase offset of display panel driving signal and display panel Download PDF

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Publication number
CN115148154A
CN115148154A CN202210933197.9A CN202210933197A CN115148154A CN 115148154 A CN115148154 A CN 115148154A CN 202210933197 A CN202210933197 A CN 202210933197A CN 115148154 A CN115148154 A CN 115148154A
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display panel
driving signal
pixel row
pixel
compensation value
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景伟航
谭仲齐
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Chipone Technology Beijing Co Ltd
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Chipone Technology Beijing Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a method and a device for compensating phase deviation of a display panel driving signal and a display panel, wherein the method comprises the following steps: acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating in advance based on the phase offset of the original driving signal and the actual driving signal of each pixel row of the display panel obtained by simulation; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. By means of the method for acquiring and storing the clock counting compensation value corresponding to each pixel row of the display panel in advance, when the driving chip outputs the driving signal of the display panel, the time sequence of the driving signal corresponding to each pixel row is adjusted according to the clock counting compensation value, so that the delay phenomenon that some pixel rows receive the driving signal is relieved, and the problem of poor display uniformity of the OLED display panel is solved.

Description

Method and device for compensating phase offset of display panel driving signal and display panel
Technical Field
The present invention relates to the field of display panel driving, and in particular, to a method and an apparatus for compensating phase shift of a display panel driving signal, and a display panel.
Background
Each component in a module pixel circuit of an OLED (Organic Light-Emitting Diode) has an RC-loading (resistance-capacitance load), and when a chip of a display panel sends a driving signal, because the IR-Drop makes a timing sequence actually reaching each pixel point not reach an ideal state, a timing sequence actually reaching a far chip end of the display panel is delayed. In the abnormal timing, the delay of the driving signal timing may cause the display effect of the far chip end of the display panel to change, such as the brightness becomes low, thereby affecting the display effect.
Although the uniformity of the display panel can be optimized by external compensation methods such as Demura (sub-pixel level optical imaging technology and software algorithm), the complexity of the peripheral driving circuit is high and the actual nature of Demura is that only the areas that it considers to be darker are lightened, or the areas that are lightened are darkened, or the areas that are colored are eliminated, and the ultimate goal is to make the different areas of the panel have approximately the same color, and the problem is not solved fundamentally.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method and an apparatus for compensating a phase shift of a driving signal of a display panel, and a display panel, in which a clock count compensation value corresponding to each pixel row of the display panel is obtained and stored in advance, and when a driving chip outputs a driving signal of the display panel, a timing sequence of the driving signal corresponding to each pixel row is adjusted according to the clock count compensation value, so as to alleviate a delay phenomenon (for example, a driving signal received by a far-end pixel row may be delayed) that some pixel rows receive the driving signal, so that different pixel rows receive the driving signal at the same time for displaying, thereby improving a problem of poor display uniformity of an OLED display panel.
In a first aspect, an embodiment of the present invention provides a method for compensating a phase offset of a driving signal of a display panel, including: acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating the phase offset between the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel, wherein the theoretical phase of the original driving signal in each pixel row of the display panel is obtained in advance; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal.
Further, the clock count compensation value is calculated by the following method: acquiring theoretical phases of original driving signals in all pixel rows of a display panel; constructing a simulation circuit according to the impedance model of the display panel; inputting the original driving signal into a simulation circuit, and simulating to obtain the actual phase of each pixel row of the display panel; determining a phase offset corresponding to each pixel row of the display panel based on a theoretical timing diagram of an original driving signal and a timing diagram of the original driving signal; and determining a clock counting compensation value corresponding to each pixel line according to the phase offset corresponding to each pixel line of the display panel.
Further, the step of determining the clock count compensation value corresponding to each pixel row according to the phase shift amount corresponding to each pixel row of the display panel includes: dividing the phase offset corresponding to each pixel row of the display panel by a preset clock period to obtain a ratio corresponding to each pixel row; and rounding the ratio upwards to obtain a clock counting compensation value corresponding to each pixel row.
Further, for each pixel row of the display panel, the step of adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row to obtain the target driving signal corresponding to the pixel row includes: for each pixel row of the display panel, determining a clock counting compensation value corresponding to the pixel row as a clock lead of a rising edge and a falling edge of a driving signal corresponding to the pixel row; and carrying out forward processing on the rising edge and the falling edge of the original driving signal according to the clock advance to obtain a target driving signal corresponding to the pixel row.
Further, the step of obtaining the clock count compensation value corresponding to each pixel row of the display panel includes: grouping each pixel line of the display panel in advance to obtain a plurality of pixel units; the clock counting compensation values corresponding to all pixel rows in each pixel unit are the same; and acquiring a clock counting compensation value corresponding to each pixel unit.
Further, the active level time of each pixel unit is the same.
Furthermore, each pixel unit in the plurality of pixel units comprises the same number of pixel lines.
In a second aspect, an embodiment of the present invention provides an apparatus for compensating a driving signal of a display panel, including: the device comprises an acquisition unit, a calculation unit and a control unit, wherein the acquisition unit is used for acquiring clock counting compensation values corresponding to pixel rows of a display panel; the clock counting compensation value is obtained by calculating the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation in advance; the adjusting unit is used for adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to each pixel row of the display panel to obtain a target driving signal corresponding to the pixel row; and the driving unit is used for driving the display panel to display according to the target driving signal.
In a third aspect, an embodiment of the present invention provides a display panel, which includes the compensation apparatus for the display panel driving signal.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processing device to perform the steps of the image rectification method according to any one of the embodiments of the first aspect.
The embodiment of the invention provides a method and a device for compensating phase deviation of a display panel driving signal and a display panel, wherein the method comprises the following steps: acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation in advance; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. In the method, the theoretical phase of each pixel row of the display panel is compared with the actual phase of each pixel row of the display panel through pre-simulation to obtain the actual phase of each pixel row of the display panel, the phase offset between the theoretical phase and the actual phase is calculated to obtain the delay condition of the driving signal of each pixel row of the display panel, the delay condition is stored in a clock counting compensation mode in advance, when the driving chip outputs the driving signal of the display panel, the clock counting compensation value corresponding to each pixel row is directly obtained, and further the timing sequence of the driving signal corresponding to each pixel row is adjusted, so that the delay phenomenon that some pixel rows receive the driving signal (for example, the driving signal received by a pixel row at the far end of a chip can be delayed) can be relieved, different pixel rows receive the driving signal at the same time for display, and the problem of poor display uniformity of the OLED display panel is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram illustrating a display effect of a display panel when a phase offset exists in a driving signal according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for compensating phase shift of a driving signal of a display panel according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for calculating a clock count compensation value of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a theoretical timing diagram of an original driving signal of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic diagram of phase offsets of a theoretical phase and an actual phase of an original driving signal of a display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of phase offset data of a simulation circuit according to a second embodiment of the present invention;
fig. 7 is a schematic diagram of a phase offset compensation scheme according to a second embodiment of the present invention;
fig. 8 is a schematic diagram of a compensation apparatus for driving signals of a display panel according to a third embodiment of the present invention.
An icon: 1-an acquisition unit; 2-an adjustment unit; 3-a drive unit.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the field of OLED driver chip development, a chip needs to input a driving signal to an input port of a display panel according to a customized timing sequence, so that each pixel point in the display panel normally emits light according to the timing sequence. In an ideal state, the driving signal output by the chip can be directly transmitted to the input port of the display panel according to the original driving signal, and the time sequence reaching each pixel point also meets the requirement of the original driving signal.
However, because each component in the module pixel circuit has internal resistance, the ID-Drop generated by the internal resistance makes the timing actually reaching each pixel point not reach an ideal state, and the timing actually reaching the far chip end of the display panel is delayed. In the abnormal timing, the delay of the driving signal timing may cause the display effect of the far chip end of the display panel to change, such as the brightness becomes low, and refer to fig. 1, in which the DDIC is a driving chip.
For the understanding of the present embodiment, the following detailed description will be given of the embodiment of the present invention.
The first embodiment is as follows:
fig. 2 is a flowchart of a method for compensating phase offset of a driving signal of a display panel according to an embodiment of the present invention.
Referring to fig. 2, the method for compensating for a phase shift of a driving signal of a display panel includes:
step S101, acquiring clock counting compensation values corresponding to pixel rows of a display panel; the clock count compensation value is calculated in advance based on a phase offset between a theoretical phase of the original driving signal in each pixel row of the display panel and an actual phase of the original driving signal in each pixel row of the display panel obtained through simulation.
Here, when the OLED display panel is in operation, the driving signals of different pixel rows are delayed to different degrees due to different RC-loading.
In one embodiment, referring to fig. 3, the clock count compensation value in step S101 is calculated by:
in step S201, a theoretical phase of the original driving signal in each pixel row of the display panel is obtained.
Here, the theoretical phase of the original driving signal is the phase of the driving signal of the display panel in an ideal operating state of the display panel, i.e., without considering RC-loading.
Step S202, a simulation circuit is constructed according to the impedance model of the display panel.
Here, the RC-loading impedance model of the display panel is preset at the time of factory shipment, and the closer the RC-loading is to the driving chip, the smaller the RC-loading is, the farther the RC-loading is from the driving chip, the larger the RC-loading is. The display panel may include at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, a micro light emitting diode display panel, and the like. The driving chip can be a general driving chip and can be suitable for display panels with different sub-pixel arrangements, so that the design cost and the manufacturing cost can be reduced.
Step S203, inputting the original driving signal into the simulation circuit, and obtaining the actual phase of each pixel row of the display panel through simulation.
In step S204, a phase shift amount corresponding to each pixel row of the display panel is determined based on the theoretical timing diagram of the original driving signal and the actual timing diagram of the original driving signal.
Here, referring to fig. 4, a theoretical timing diagram of an original driving signal of the display panel without considering RC-loading and an actual timing diagram of the display panel with considering RC-loading, a phase shift diagram of a theoretical phase and an actual phase of the original driving signal of fig. 5 is obtained, where a solid line part is the theoretical phase and a dotted line part is the actual phase in fig. 5. The phase shift amount of the theoretical phase and the actual phase of the original driving signal is the phase difference between the rising edge of the theoretical phase and the rising edge of the actual phase or the phase difference between the falling edge of the theoretical phase and the falling edge of the actual phase.
In step S205, a clock count compensation value corresponding to each pixel row of the display panel is determined according to the phase shift amount corresponding to each pixel row.
In one embodiment, step S205 includes:
dividing the phase offset corresponding to each pixel row of the display panel by a preset clock period to obtain a ratio corresponding to each pixel row; and rounding the ratio upwards to obtain a clock counting compensation value corresponding to each pixel row.
Here, the preset clock period may be set according to practical situations, and may be 15.75ns (nanoseconds), which corresponds to a reference clock of 63.5MHz.
Step S102, for each pixel row of the display panel, adjusting a timing of the original driving signal according to the clock count compensation value corresponding to the pixel row, to obtain a target driving signal corresponding to the pixel row.
Here, the target driving signal corresponding to each pixel row is subjected to a shift-in process compared to the original driving signal.
In one embodiment, the step S102 of adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row for each pixel row of the display panel to obtain the target driving signal corresponding to the pixel row includes:
for each pixel row of the display panel, determining a clock counting compensation value corresponding to the pixel row as a clock lead of a rising edge and a falling edge of a driving signal corresponding to the pixel row; and carrying out forward processing on the rising edge and the falling edge of the original driving signal according to the clock advance to obtain a target driving signal corresponding to the pixel row.
Here, since the actual driving signal is delayed compared to the original driving signal, the actual driving signal is advanced according to the clock count compensation value to obtain the corresponding target driving signal.
And step S103, driving the display panel to display according to the target driving signal.
Here, the display panel is driven according to the target driving signal so that the driving signal output from the driving chip can reach each pixel row at the same time, thereby causing each pixel row of the display panel to normally emit light in time sequence.
The embodiment of the invention provides a method for compensating phase deviation of a display panel driving signal, which comprises the following steps: acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating the phase offset between the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel, wherein the theoretical phase of the original driving signal in each pixel row of the display panel is obtained in advance; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. In the method, the clock counting compensation value corresponding to each pixel row is obtained to adjust the time sequence of the driving signal corresponding to each pixel row, so that the delay of the driving signal between different pixel rows is eliminated, the different pixel rows drive the display panel at the same time, and the display uniformity of the display panel is improved.
The second embodiment:
in practical applications, for the GCK/GCB/ECK/ECB driving signal, since the number of oscillations in each frame is too many (refer to a resolution of 1080 × 2340, and 1000-2000 oscillations in each frame is largely summarized), accurate compensation is performed on each falling edge and rising edge, which wastes too much area of a driving chip, and the phase difference does not require very high compensation accuracy, so this embodiment provides another method for compensating the phase offset of the driving signal for the display panel, and the step of obtaining the clock count compensation value corresponding to each pixel row of the display panel in this embodiment includes:
grouping each pixel line of the display panel in advance to obtain a plurality of pixel units; the clock counting compensation values corresponding to all pixel rows in each pixel unit are the same; and acquiring a clock counting compensation value corresponding to each pixel unit. Wherein, the number of pixel lines contained in each pixel unit in the plurality of pixel units is the same.
Here, each pixel line of the display panel is grouped in advance according to the resolution of the display panel to obtain a plurality of pixel units containing the same number of pixel lines; and acquiring the clock counting compensation value corresponding to each pixel unit as the clock counting compensation value corresponding to each pixel row.
Specifically, referring to fig. 6, the pixel rows of the display panel are grouped in advance according to the resolution of the display panel, and in this embodiment, the display panel is divided into 8 pixel units by taking 300 pixel rows as an example. The first pixel unit comprises 1 st to 300 th pixel rows, the second pixel unit comprises 300 th to 600 th pixel rows, the third pixel unit comprises 600 th to 900 th pixel rows, the fourth pixel unit comprises 900 th to 1200 th pixel rows, the fifth pixel unit comprises 1200 th to 1500 th pixel rows, the sixth pixel unit comprises 1500 th to 1800 th pixel rows, the seventh pixel unit comprises 1800 th to 2100 th pixel rows, and the eighth pixel unit comprises 2100 th to 2340 th pixel rows. The first pixel unit is close to the driving chip, the RC-loading of the first pixel unit is smaller than that of the second pixel unit, and the like.
Furthermore, a simulation circuit is constructed according to the RC-loading model of the display panel and the driving chip, an original driving signal of the display panel in an ideal state is input into the simulation circuit, and the actual phase of each pixel unit of the display panel is obtained through simulation. Based on the actual phase timing chart and the theoretical phase timing chart of the original driving signal, the phase shift amount corresponding to each pixel unit shown in fig. 6 is obtained. The phase shift amount of the first pixel unit is 0 μ s (microsecond), the phase shift amount of the second pixel unit is 0.02 μ s, the phase shift amount of the third pixel unit is 0.05 μ s, the phase shift amount of the fourth pixel unit is 0.08 μ s, the phase shift amount of the fifth pixel unit is 0.1 μ s, the phase shift amount of the sixth pixel unit is 0.14 μ s, the phase shift amount of the seventh pixel unit is 0.17 μ s, and the phase shift amount of the eighth pixel unit is 0.2 μ s.
Further, referring to fig. 7, according to a preset clock period of 15.75ns and a reference clock of 63.5MHz, a clock count compensation value is calculated, and a phase offset corresponding to each pixel unit of the display panel is divided by the preset clock period to obtain a ratio corresponding to each pixel unit; and rounding the ratio upwards to obtain the clock counting compensation value corresponding to each pixel unit. The clock count compensation value of the first pixel unit is 0, the clock count compensation value of the second pixel unit is 1, the clock count compensation value of the third pixel unit is 3, the clock count compensation value of the fourth pixel unit is 5, the clock count compensation value of the fifth pixel unit is 6, the clock count compensation value of the sixth pixel unit is 9, the clock count compensation value of the seventh pixel unit is 11, and the clock count compensation value of the eighth pixel unit is 13.
Further, for each pixel unit of the display panel, determining a clock count compensation value corresponding to the pixel unit as a clock lead of a rising edge and a falling edge of a driving signal corresponding to the pixel unit; and carrying out forward processing on the rising edge and the falling edge of the original driving signal according to the clock advance to obtain a target driving signal corresponding to the pixel unit.
Here, referring to the eighth pixel unit, if the phase of the original driving signal of the eighth pixel unit is 0.8 μ s, the original driving signal of the eighth pixel unit corresponds to 52 clock counts, when the phase offset of the eighth pixel unit is 0.2 μ s, the eighth pixel unit needs to be shifted forward by 13 clock counts, the target driving signal of the eighth pixel unit is 39 clock counts, and the calculation method of the remaining pixel units refers to the eighth pixel unit, which is not repeated herein.
Further, the active level time of each pixel unit is the same.
The embodiment of the invention provides a method for compensating phase deviation of a display panel driving signal, which comprises the following steps: acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation in advance; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. In the mode, the delay of the driving signals between different pixel rows is eliminated by dividing the display panel into a plurality of pixel units according to the resolution, the method does not need to carry out accurate compensation on each falling edge and rising edge, the area of a driving chip is saved, and the compensation is more efficient.
Example three:
fig. 8 is a schematic diagram of a compensation apparatus for driving signals of a display panel according to a third embodiment of the present invention.
Referring to fig. 8, the display panel driving signal compensating apparatus includes:
the display device comprises an acquisition unit 1, a calculation unit and a control unit, wherein the acquisition unit is used for acquiring clock counting compensation values corresponding to pixel rows of a display panel; the clock counting compensation value is obtained by calculating the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation in advance;
the adjusting unit 2 is configured to adjust, for each pixel row of the display panel, a timing sequence of an original driving signal according to a clock count compensation value corresponding to the pixel row, so as to obtain a target driving signal corresponding to the pixel row;
and the driving unit 3 is used for driving the display panel to display according to the target driving signal.
The embodiment of the invention provides a compensation device for a display panel driving signal, which comprises: acquiring a clock counting compensation value corresponding to each pixel row of the display panel; the clock counting compensation value is obtained by calculating the phase offset of the theoretical phase of the original driving signal in each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel obtained by simulation in advance; for each pixel row of the display panel, adjusting the time sequence of an original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row; and driving the display panel to display according to the target driving signal. In the method, the theoretical phase of each pixel row of the display panel is compared with the actual phase of each pixel row of the display panel through pre-simulation to obtain the actual phase of each pixel row of the display panel, the phase offset between the theoretical phase and the actual phase is calculated to obtain the delay condition of the driving signal of each pixel row of the display panel, the delay condition is stored in a clock counting compensation mode in advance, when the driving chip outputs the driving signal of the display panel, the clock counting compensation value corresponding to each pixel row is directly obtained, and further, the time sequence of the driving signal corresponding to each pixel row is adjusted, so that the delay phenomenon that some pixel rows receive the driving signal (for example, the driving signal received by the pixel row at the far end can be delayed) can be relieved, different pixel rows receive the driving signal at the same time for displaying, and the problem of poor display uniformity of the OLED display panel is improved.
The embodiment of the invention also provides a display panel, which comprises the compensation device for the display panel driving signal.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processing device to perform the steps of the method for compensating for phase offset of a display panel driving signal.
The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the method embodiment, which is not described herein again.
The above description is intended to be illustrative of the present invention and not to limit the scope of the invention, which is defined by the claims appended hereto.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although the steps and sequence of steps of the embodiments of the present invention are presented in method and method diagrams, the executable instructions of the steps implementing the specified logical functions may be re-combined to create new steps. The sequence of the steps should not be limited to the sequence of the steps in the method and the method illustrations, and can be modified at any time according to the functional requirements. Such as performing some of the steps in parallel or in reverse order.
In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The term "and/or" in the present invention is only an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" in the present invention means any combination of any one or more of a plurality, for example, including at least one of a, B, and C, and may mean including any one or more elements selected from the group consisting of a, B, and C.

Claims (10)

1. A method for compensating for phase offset of a driving signal of a display panel, comprising:
acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating in advance based on the theoretical phase of an original driving signal in each pixel row of the display panel and the phase offset of the original driving signal in the actual phase of each pixel row of the display panel obtained by simulation;
for each pixel row of the display panel, adjusting the time sequence of the original driving signal according to the clock counting compensation value corresponding to the pixel row to obtain a target driving signal corresponding to the pixel row;
and driving the display panel to display according to the target driving signal.
2. The method of claim 1, wherein the clock count compensation value is calculated by:
acquiring theoretical phases of the original driving signals in all pixel rows of the display panel;
constructing a simulation circuit according to the impedance model of the display panel;
inputting the original driving signal into the simulation circuit, and simulating to obtain the actual phase of each pixel row of the display panel;
determining a phase offset corresponding to each pixel row of the display panel based on a theoretical timing diagram of the original driving signal and an actual timing diagram of the original driving signal;
and determining a clock counting compensation value corresponding to each pixel line according to the phase offset corresponding to each pixel line of the display panel.
3. The method for compensating phase shift of driving signals of a display panel according to claim 2, wherein the step of determining the clock count compensation value corresponding to each pixel row of the display panel according to the phase shift amount corresponding to each pixel row comprises:
dividing the phase offset corresponding to each pixel row of the display panel by a preset clock period to obtain a ratio corresponding to each pixel row;
and rounding the ratio upwards to obtain a clock counting compensation value corresponding to each pixel row.
4. The method as claimed in claim 1, wherein the step of adjusting the timing of the original driving signal according to the clock count compensation value corresponding to the pixel row to obtain the target driving signal corresponding to the pixel row comprises:
for each pixel row of the display panel, determining the clock counting compensation value corresponding to the pixel row as the clock lead of the rising edge and the falling edge of the driving signal corresponding to the pixel row;
and performing forward processing on the rising edge and the falling edge of the original driving signal according to the clock advance to obtain a target driving signal corresponding to the pixel row.
5. The method for compensating for phase shift of driving signals of a display panel according to claim 1, wherein the step of obtaining the clock count compensation value corresponding to each pixel row of the display panel comprises:
grouping each pixel line of the display panel in advance to obtain a plurality of pixel units; the clock counting compensation values corresponding to all pixel rows in each pixel unit are the same;
and acquiring a clock counting compensation value corresponding to each pixel unit.
6. The method of claim 5, wherein the active level time of each pixel unit is the same.
7. The method of claim 5, wherein each of the plurality of pixel units comprises the same number of pixel rows.
8. An apparatus for compensating a driving signal of a display panel, comprising:
the acquisition unit is used for acquiring clock counting compensation values corresponding to all pixel rows of the display panel; the clock counting compensation value is obtained by calculating the phase offset of the original driving signal in the theoretical phase of each pixel row of the display panel and the actual phase of the original driving signal in each pixel row of the display panel, wherein the phase offset is obtained by simulation in advance;
the adjusting unit is used for adjusting the time sequence of the original driving signal according to the clock counting compensation value corresponding to each pixel row of the display panel to obtain a target driving signal corresponding to the pixel row;
and the driving unit is used for driving the display panel to display according to the target driving signal.
9. A display panel comprising the compensation arrangement for a display panel drive signal of claim 8.
10. A computer-readable storage medium, having stored thereon a computer program, characterized in that the computer program, when being executed by a processing device, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
CN202210933197.9A 2022-08-04 2022-08-04 Method and device for compensating phase offset of display panel driving signal and display panel Pending CN115148154A (en)

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CN202210933197.9A CN115148154A (en) 2022-08-04 2022-08-04 Method and device for compensating phase offset of display panel driving signal and display panel

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