CN115144797A - Simulation test method for Hall mobility of JFET (junction field effect transistor) area in SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) - Google Patents
Simulation test method for Hall mobility of JFET (junction field effect transistor) area in SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) Download PDFInfo
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- CN115144797A CN115144797A CN202211043652.4A CN202211043652A CN115144797A CN 115144797 A CN115144797 A CN 115144797A CN 202211043652 A CN202211043652 A CN 202211043652A CN 115144797 A CN115144797 A CN 115144797A
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Abstract
The invention relates to the technical field of semiconductors, and particularly provides a simulation test method for Hall mobility of a JFET (junction field effect transistor) region in a SiC MOSFET (metal-oxide-semiconductor field effect transistor), which comprises the following steps: performing N-type ion implantation on one surface of the SiC wafer; covering SiO on the surface of the SiC wafer implanted with N-type ions 2 A film; in the SiO 2 Etching Hall strip on film, and etching off SiO in Hall strip region 2 A film; depositing Ni on the Hall strips, annealing, and evaporating and coating Al as an electrode after annealing; cutting the Hall strip after the electrode is evaporated from the SiC wafer to form a Hall strip chip; the method comprises the steps of putting a Hall strip-shaped chip into a sealed cavity, vacuumizing the sealed cavity, controlling the internal temperature of the sealed cavity, and testing the Hall mobility of the Hall strip-shaped chip by applying various magnetic field strengths. According to the scheme of the invention, the simulation test method can simulate and measure JAnd the FET region body mobility facilitates later-stage device process optimization.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a simulation test method for Hall mobility of a JFET (junction field effect transistor) region in a SiC MOSFET (metal-oxide-semiconductor field effect transistor).
Background
SiC, which is a wide bandgap semiconductor material rapidly developed in recent decades, has advantages of a wide bandgap, high thermal conductivity, high carrier saturation mobility, high power density, and the like, compared with other semiconductor materials, such as Si, gaN, and GaAs. SiC can be thermally oxidized to produce silicon dioxide, making it possible to implement power devices and circuits such as SiC MOSFETs and SBDs. With the great increase of the power level of the power device, the higher power level brings larger switching loss and conduction loss, and particularly for the device with the withstand voltage of below 900V, the JFET resistance in the MOSFET device can reach about 10% of the on-resistance of the whole device. The reduction of the partial resistance of the JFET has extremely important significance for reducing the on-resistance of the device, optimizing the area of a chip, reducing the cost of the device and reducing the power loss of the device.
Currently, the method of measuring the mobility of the channel region of a MOSFET mainly uses the effective mobility, and given the gate length and the device width of a MOSFET, the current on the drain can be expressed as a function of the mobility when the drain voltage is small (50 mv). The carrier concentration in the channel is obtained according to the gate inductance, so that the effective mobility in the channel of the MOSFET device can be obtained:
wherein, in the step (A),
is the effective mobility of the electron beam emitted from the electron source,
is the conductance of the drain electrode,
is the capacitance of the gate electrode and is,
is the voltage of the gate-source,
is the voltage of the threshold voltage of the transistor,
is the length of the gate electrode(s),
is the MOSFET device width.
Then, the scheme in the prior art cannot measure the mobility of the JFET region in the MOSFET, so that the optimal process conditions cannot be determined; v GS -V T When the value of (A) is larger, the effective mobility is more accurate, and when V is larger GS -V T When the mobility approaches 0, the value of the effective mobility is greatly deviated; transconductance g d Is dependent on the drain voltage V d Varying, each time V is selected d The mobility rates of different tests are also greatly different; furthermore, the prior art can only calculate the mobility of the surface, and cannot measure the mobility of the body.
Disclosure of Invention
The invention aims to solve at least one technical problem in the background art and provides a simulation test method for Hall mobility of a JFET (junction field effect transistor) area in a SiC MOSFET (metal-oxide-semiconductor field effect transistor).
In order to achieve the above object, the present invention provides a method for analog testing of hall mobility of a JFET region in a SiC MOSFET, comprising:
performing N-type ion implantation on one surface of the SiC wafer;
performing high-temperature annealing on the surface of the SiC wafer injected with N-type ions and covering SiO 2 A film;
in the SiO 2 Etching Hall strip on film, and etching off SiO in Hall strip region 2 A film;
depositing Ni on the Hall strips, annealing, and evaporating and coating Al as an electrode after annealing;
cutting the Hall strip-shaped chip subjected to electrode evaporation and the corresponding SiC wafer to form a Hall strip-shaped chip;
the method comprises the steps of putting a Hall strip chip into a sealed cavity, vacuumizing the sealed cavity, then controlling the internal temperature of the sealed cavity, and testing the Hall mobility of the Hall strip chip by applying various magnetic field strengths.
According to one aspect of the invention, before the Hall strip-shaped chip is placed in the sealed cavity, the Hall strip-shaped chip is placed in a chip carrier, and the electrode of the Hall strip-shaped chip is led out to the chip carrier through metal bonding.
According to one aspect of the invention, the N-type ions are implanted at a dose of 2e12 and an energy of 200keV.
According to one aspect of the invention, the surface of the SiC wafer implanted with N-type ions is subjected to high temperature annealing, the N-type ions are activated, and SiC is oxidized to form the SiO 2 A film;
the SiO 2 The thickness of the film was 20nm.
According to one aspect of the invention, after the Hall strip-shaped chip is placed in the chip carrier, a PMMA film is covered on the Hall strip-shaped chip.
According to one aspect of the invention, the internal temperature of the sealed chamber is controlled as follows:
and introducing helium gas into the sealed cavity for cooling.
According to one aspect of the invention, the internal temperature of the sealed cavity is controlled as follows:
the chip carrier is heated by a heating device.
According to one aspect of the present invention, the hall mobility of the hall bar chip is tested after applying a vertically upward magnetic field from the bottom of the hall bar chip.
According to the scheme of the invention, the method can be used for measuring the mobility and the carrier concentration of the material with low conductivity; compared with the prior art, the method has higher measurement precision and lower requirement on the material doping uniformity; the testing method can measure the mobility of the JFET area body, and facilitates the process optimization of devices in the later period.
Moreover, because the mobility can not change due to different applied voltages, the curve of the mobility along with the temperature can be measured, and the change rate of the mobility at different temperatures can be conveniently known. Aiming at different doping concentrations in the JFET region, the optimal value (process condition) can be found through the testing method provided by the invention, and data support is provided for later-stage production of high-quality SiC MOSFETs.
Drawings
FIG. 1 schematically shows a flow chart of a method for analog testing of Hall mobility of a JFET region in a SiC MOSFET according to one embodiment of the present invention;
2-5 show process diagrams of a simulation test method for Hall mobility of JFET regions in SiC MOSFETs;
FIG. 6 shows an electron flow diagram under a condition that a vertically upward magnetic field is applied to a Hall strip chip;
FIG. 7 shows a flow diagram of electrons in the absence of a magnetic field.
Detailed Description
The content of the invention will now be discussed with reference to exemplary embodiments. It is to be understood that the embodiments discussed are merely intended to enable one of ordinary skill in the art to better understand and thus implement the teachings of the present invention, and do not imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment".
Fig. 1 schematically shows a flow chart of a method of analog testing of hall mobility of a JFET region in a SiC MOSFET according to an embodiment of the invention. As shown in fig. 1, in the present embodiment, the method for analog testing of hall mobility of JFET region in SiC MOSFET includes the following steps:
carrying out N-type ion implantation on one surface of the SiC wafer;
covering SiO on the surface of the SiC wafer implanted with N-type ions 2 A film;
in SiO 2 Etching Hall bars (Hall bar) on the film, and etching off SiO in the Hall bar region 2 A film;
depositing Ni on the Hall strip, annealing, and evaporating and coating Al as an electrode after annealing;
cutting off the Hall strip after the evaporation of the electrode and the corresponding SiC wafer to form a Hall strip chip;
the Hall strip-shaped chip is placed in a sealed cavity, the sealed cavity is vacuumized, the internal temperature of the sealed cavity is controlled, and the Hall mobility of the Hall strip-shaped chip is tested by applying various magnetic field strengths.
Because the JFET area in the SiC MOSFET is actually a low-doped semiconductor, siC low doping is realized through N-type ion implantation so as to simulate the JFET area in the SiC MOSFET, and the tested data can be consistent with the data obtained from the JFET area.
According to one embodiment of the invention, before the Hall strip chip is placed in the sealed cavity, the Hall strip chip is placed in the chip carrier, the electrode of the Hall strip chip is led out to the chip carrier through metal bonding, and then the Hall strip chip on the chip carrier is externally connected with other devices to realize various measurements such as current and voltage.
According to one embodiment of the present invention, the N-type ions are implanted at a dose of 2e12 and an energy of 200keV.
According to one embodiment of the invention, the surface implanted with N-type ions on the SiC wafer is subjected to high-temperature annealing, the high-temperature annealing is used for realizing the repair of the crystal lattice damage of the N-type ions, impurity atoms move to the crystal lattice points and are activated, and the high-temperature annealing is used for oxidizing SiC into SiO 2 Thereby forming a thin SiO layer 2 A film;
SiO 2 the thickness of the film was 20nm.
According to one embodiment of the invention, after the Hall strip-shaped chips are placed in the chip carrier, the Hall strip-shaped chips are covered with the PMMA film.
According to one embodiment of the present invention, the internal temperature of the sealed chamber is controlled as follows:
and introducing helium gas into the sealed cavity for cooling.
According to one embodiment of the present invention, the internal temperature of the sealed chamber is controlled as follows:
the chip carrier is heated by a heating device.
According to one embodiment of the present invention, the hall mobility of the hall bar chip is tested after applying a vertically upward magnetic field from the bottom of the hall bar chip.
According to the scheme of the invention, the method can be used for measuring the mobility and the carrier concentration of the material with low conductivity; compared with Van der pauw method test, the method has higher measurement precision and lower requirement on material doping uniformity; the testing method can measure the mobility of the JFET area body, and facilitates the process optimization of devices in the later period.
Moreover, because the mobility can not change due to different applied voltages, the curve of the mobility along with the temperature can be measured, and the change rate of the mobility at different temperatures can be conveniently known. Aiming at different doping concentrations in the JFET region, the optimal value (process condition) can be found out through the testing method provided by the invention, and data support is provided for later-stage production of high-quality SiC MOSFETs.
Based on the above scheme, the technical scheme of the invention is further described in a mode of a specific embodiment by combining the attached drawings.
Example 1
Fig. 2-5 show process diagrams of a simulation test method for hall mobility in JFET regions in SiC MOSFETs.
Specifically, fig. 2 is a diagram of a SiC wafer subjected to N-type ion implantation according to experimental requirements, wherein the implantation dose is 2e12 and the energy is 200keV.
FIG. 3 shows the implantation of N-type ions followed by a high temperature anneal of the carbon film to activate the dopant ions, which would damage the SiC wafer surface by thermal oxidation to form a layer of about 20nm SiO 2 Film 1.
FIG. 4 is a process of forming Hall bars 2 by photolithography, etching away SiO in the Hall bar regions 2 Then, depositing a layer of Ni and annealing, then evaporating Al as an electrode, cutting the wafer and the Hall strip-shaped structure on the wafer to ensure the integrity and shape of the whole Hall strip-shaped structureForming a Hall-bar chip 3.
FIG. 5 is a diagram showing that an electrode forming a Hall strip chip is led out (by using a gold wire 4) to a chip carrier 5 through metal bonding, and then the Hall strip chip is covered with a thin PMMA film to prevent water vapor and oxygen from permeating into the chip to influence the measurement of the conductivity, and the current and voltage of the chip can be measured directly through the carrier at the later stage;
the carrier is put into a sealed cavity (such as a cryogen free measurement system), and the temperature can be reduced by introducing helium after vacuumizing, and the Hall mobility and the like can be tested by applying different magnetic field strengths, and the Hall mobility at high temperature can also be tested by heating equipment.
Fig. 6 and 7 show the electron flow direction under the condition where a vertically upward magnetic field is applied and under the condition where no magnetic field is applied.
Firstly, the doping concentration (doping concentration of N-type ions) and the depth t of the peak concentration (the depth of the highest point of the doping concentration on the surface of the SiC wafer) can be measured by SIMS (single ion concentration), and a four-point measurement technology
The conductivity σ is measured, where U is the voltage applied across the Hall bar, I is a constant current source, L is the length of the Hall bar, and S is the product of the Hall bar width and t.
As shown in fig. 7, when a voltage difference is applied between the electrodes No. 1 and No. 4 under the condition of no applied magnetic field, current can be observed to pass through, but there is almost no voltage difference between the electrodes No. 3 and No. 6, mainly because no electrons and holes fall onto the two electrodes, and there is no voltage difference because there is basically equipotential from the perspective of potential; however, when a 12T vertical upward magnetic field is applied and a voltage difference is applied between the No. 1 electrode and the No. 4 electrode, a large amount of electrons are gathered on the No. 16 electrode due to the shift of the electrons in the process of transmission from 4 to 1, so that the potential of the No. 6 electrode is obviously higher than that of the No. 16 electrode, and a voltage difference V (+ 12T) is formed 6-16 Similarly, the magnetic field direction is changed, a 12T magnetic field which is vertically downward is applied, and a voltage V (-12T) can be measured between the No. 16 electrode and the No. 6 electrode 6-16 。
In the present embodiment, according to the Hall calculation formula, the Hall coefficient is
Wherein
The working current between the No. 1 electrode and the No. 4 electrode, t is the doping depth, and B is the magnetic field intensity.
Hall mobility
Wherein
The working current between the No. 1 electrode and the No. 4 electrode is shown, sigma is the conductivity, t is the doping depth, and B is the magnetic field intensity.
Concentration of carrier
Wherein q is the charge carrier magnitude.
In the experiment, the current between the No. 1 electrode and the No. 4 electrode is changed by applying a constant magnetic field intensity B
A current can be derived
And Hall voltage U H From this, a constant value of the Hall mobility, which varies only with the temperature, and the current can be calculated
Independent of the magnetic field strength.
Furthermore, by the scheme, the curve of the Hall mobility, the carrier concentration and the Hall coefficient changing along with the temperature can be tested by changing the temperature (heating or liquid helium cooling) of the chip carrier, which is of great help for analyzing the static characteristics of the device under different temperature conditions, and the optimal working condition of the device can be analyzed accordingly.
According to the scheme of the invention, the JFET region in the SiC MOSFET can be simulated through the mode, so that the simulation test of the Hall mobility of the JFET region in the SiC MOSFET is realized, the mobility of the JFET region in the MOSFET can be accurately measured through the scheme, the optimal process condition of a later device is determined, and data support is provided for later production of high-quality SiC MOSFETs.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (8)
- A simulation test method for Hall mobility of a JFET region in a SiC MOSFET is characterized by comprising the following steps:carrying out N-type ion implantation on one surface of the SiC wafer;covering SiO on the surface of the SiC wafer implanted with N-type ions 2 A film;in the SiO 2 Etching Hall strip on film, and etching off SiO in Hall strip region 2 A film;depositing Ni on the Hall strips, annealing, and evaporating and coating Al as an electrode after annealing;cutting the Hall strip-shaped chip subjected to electrode evaporation and the corresponding SiC wafer to form a Hall strip-shaped chip;the method comprises the steps of putting a Hall strip-shaped chip into a sealed cavity, vacuumizing the sealed cavity, controlling the internal temperature of the sealed cavity, and testing the Hall mobility of the Hall strip-shaped chip by applying various magnetic field strengths.
- 2. The method for analog testing of the hall mobility of a JFET region in a SiC MOSFET of claim 1, wherein the hall bar chip is placed into a chip carrier before being placed into the sealed cavity, and electrodes of the hall bar chip are led out onto the chip carrier by metal bonding.
- 3. The method of claim 1, wherein the N-type ions are implanted at a dose of 2e12 and an energy of 200keV.
- 4. The method of claim 1, wherein the surface of the SiC wafer implanted with N-type ions is annealed at high temperature to activate the N-type ions and oxidize SiC to form the SiO 2 A film;the SiO 2 The thickness of the film was 20nm.
- 5. The method for analog testing of the hall mobility of a JFET region in a SiC MOSFET of claim 2, wherein the hall bar chip is covered with a PMMA film after the hall bar chip is placed into the chip carrier.
- 6. The method of claim 1, wherein controlling the internal temperature of the sealed cavity is:and introducing helium gas into the sealed cavity for cooling.
- 7. The method for analog testing of hall mobility of JFET regions in a SiC MOSFET of claim 2, wherein controlling the internal temperature of the sealed cavity is:the chip carrier is heated by a heating device.
- 8. The method for analog testing of the hall mobility of a JFET region in a SiC MOSFET of any of claims 1-7, wherein the hall mobility of the hall bar chip is tested after applying a vertically upward magnetic field from the bottom of the hall bar chip.
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