CN115141750A - Silicon-based nanopore array sequencing chip and preparation method thereof - Google Patents

Silicon-based nanopore array sequencing chip and preparation method thereof Download PDF

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CN115141750A
CN115141750A CN202110335019.1A CN202110335019A CN115141750A CN 115141750 A CN115141750 A CN 115141750A CN 202110335019 A CN202110335019 A CN 202110335019A CN 115141750 A CN115141750 A CN 115141750A
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不公告发明人
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Shanghai Jinguan Technology Co ltd
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Abstract

The invention provides a silicon-based nanopore array sequencing chip and a preparation method thereof, wherein the chip sequentially comprises the following components from bottom to top: the silicon chip comprises a silicon substrate, a first dielectric layer, a second dielectric layer and a plurality of electrodes, wherein the first dielectric layer and the second dielectric layer are made of different materials; a common cavity is formed in the silicon substrate and penetrates through the silicon substrate; a plurality of nano holes penetrating through the first dielectric layer are formed in the first dielectric layer; a plurality of cavities penetrating through the second dielectric layer are formed in the second dielectric layer; the plurality of cavities are correspondingly arranged on the plurality of nano holes; the plurality of electrodes are correspondingly arranged on the plurality of cavities and the surface of the second dielectric layer, and the exposed part of each electrode and the corresponding cavity form a bridge-shaped structure; the common cavity exposes a number of nanopores. The chip is based on the existing mature silicon micromachining process combined with the breakdown principle of dielectric materials, has small and controllable process fluctuation, low cost and simple process, is suitable for controllable large-scale parallelization to form a nanopore array, and is further suitable for industrial mass production.

Description

Silicon-based nanopore array sequencing chip and preparation method thereof
Technical Field
The invention belongs to the technical field of micro-nano medical detection application, and particularly relates to a silicon-based nanopore array sequencing chip and a preparation method thereof.
Background
The invention relates to a nanopore-based sequencing technology, which is originated from a Coulter counter and an ion channel single current recording technology, and has the basic principle that: the two electrolyte chambers are separated by an insulating film, forming cis and trans compartments, and only one nanoscale hole in the insulating film is communicated with the two chambers. When a voltage is applied to the electrolyte chamber, electrolyte ions in the solution move through the nanopore by electrophoresis, forming a steady state ionic current, and when a particle having a size slightly smaller than the pore size passes through the pore, the current flowing through the nanopore will be blocked, interrupting the current signal, and then restoring the original signal. The addition of a sample of charged biomolecules (ions, DNA, RNA, peptides, proteins, drugs, polymer macromolecules, etc.) to an electrolyte compartment results in the entry and exit of the biomolecules from the nanopore, which produces a series of blocking current signals in the ionic current signal, the magnitude and duration of which convey many characteristics of the sample, including the size, concentration and structure of the biomolecules.
Nanopores currently used for sequencing are roughly classified into 2 types: biological nanopores and solid-state nanopores. The biological nano-pores are prepared on phospholipid bilayers, need to be stored at low temperature, and have short stability and service life. To address the shortcomings of biological nanopores, studies of solid-state nanopores have emerged. The current solid state nanopore preparation methods include electron beam or ion beam drilling, feedback etching, pore making and other technologies. The electron beam or ion beam drilling needs to be carried out one by one, the cost is high, the preparation time is too long, and the mass production of the array nano-holes in large scale cannot be realized; the feedback etching hole making needs to use a plurality of mask plates, so that the preparation cost is improved, in addition, the process fluctuation is large, and the size of the formed nano hole is unstable, so that the mass production of the array nano hole in a large scale cannot be realized.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a silicon-based nanopore array sequencing chip and a method for preparing the same, which are used to solve the problem that the preparation method of solid-state nanopores in the prior art is not suitable for controllable large-scale parallelization to form a solid-state nanopore array due to high cost, long preparation time, large process fluctuation, and unstable controllability.
In order to achieve the above objects and other related objects, the present invention provides a method for preparing a silicon-based nanopore array sequencing chip, the method comprising the steps of:
providing a silicon substrate, and sequentially depositing a first dielectric layer and a second dielectric layer which are made of different materials on the front surface of the silicon substrate;
forming a plurality of cavities penetrating through the second dielectric layer in the second dielectric layer through photoetching and etching processes;
filling metal in the cavities to form a plurality of metal layers;
forming a plurality of electrodes on the second dielectric layer, wherein the plurality of electrodes are correspondingly formed above the plurality of metal layers, and the exposed part of each electrode is connected with the corresponding metal layer in a bridge structure;
etching the back surface of the silicon substrate to form a common cavity penetrating through the silicon substrate;
filling electrolyte into the common cavity, applying breakdown voltage between the electrodes and the electrolyte, and breaking down the first dielectric layer to form nano holes in the first dielectric layer corresponding to each metal layer;
and (3) inverting the structure, melting the metal layer, and removing the molten metal layer by adopting a vacuum suction mode.
Optionally, the silicon substrate is a (110) silicon substrate; forming the first dielectric layer and the second dielectric layer by adopting a chemical vapor deposition process; and etching the back surface of the silicon substrate by adopting a potassium hydroxide solution wet method to form the common cavity.
Optionally, the metal layer is made of Cd, sn, in or Bi; the electrode is made of Cu, al, tiN, au or Pt.
Optionally, the step of forming a number of said cavities comprises:
coating a photoresist layer on the surface of the second dielectric layer and patterning to form a patterned photoresist layer;
etching the second dielectric layer based on the patterned photoresist layer to form a plurality of cavities penetrating through the second dielectric layer;
and removing the patterned photoresist layer.
Optionally, the step of forming a number of the metal layers comprises:
depositing a layer of metal on the second dielectric layer by adopting a metal deposition process, and completely filling a plurality of cavities with the metal;
and removing the metal on the second dielectric layer by adopting a chemical mechanical polishing process, and only remaining the metal in the cavity.
Optionally, the step of forming a number of said electrodes comprises:
coating a photoresist layer on the surface of the second dielectric layer and patterning to form a patterned photoresist layer, wherein the exposed part of the patterned photoresist layer and the corresponding metal layer are exposed;
depositing an electrode material layer on the patterned photoresist layer by adopting a metal deposition process;
and removing the patterned photoresist layer, and grinding the electrode material layer by adopting a chemical mechanical grinding process to form a plurality of electrodes.
The invention also provides a silicon-based nanopore array sequencing chip, which sequentially comprises the following components from bottom to top: the chip comprises a silicon substrate, a first dielectric layer, a second dielectric layer and a plurality of electrodes, wherein the first dielectric layer and the second dielectric layer are made of different materials;
a common cavity penetrating through the silicon substrate is formed in the silicon substrate;
a plurality of nano holes penetrating through the first dielectric layer are formed in the first dielectric layer;
a plurality of cavities penetrating through the second dielectric layer are formed in the second dielectric layer;
the plurality of cavities are correspondingly arranged on the plurality of nano holes; the plurality of electrodes are correspondingly arranged on the plurality of cavities and formed on the surface of the second dielectric layer, and the exposed part of each electrode and the corresponding cavity form a bridge-shaped structure; the common cavity exposes a plurality of the cavities and a plurality of the nanopores.
Optionally, the thickness of the silicon substrate is between 500 μm and 1000 μm, the thickness of the first dielectric layer is between 10nm and 1000nm, and the thickness of the second dielectric layer is between 10nm and 100 μm.
Optionally, the size of the nanopore is between 0.1nm and 100 nm.
Optionally, the cross-sectional shape of a plurality of the cavities is square, rectangular, circular or oval.
Optionally, the cavity has a cross-sectional minimum dimension between 50nm and 5000nm.
Optionally, the cavities are the same and arranged in an array, and the space between the cavities in two adjacent rows and the space between two adjacent cavities are equal.
Optionally, the pitch is between 200nm and 10 μm.
Optionally, the material of the first dielectric layer is SiN, siO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 (ii) a The second dielectric layer is made of SiN or SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 。
Optionally, the material of the electrode is Cu, al, tiN, au or Pt
As described above, the silicon-based nanopore array sequencing chip and the preparation method thereof are based on the existing mature silicon micromachining process combined with the breakdown principle of dielectric materials, have small and controllable process fluctuation, low cost and simple process, and are suitable for controllable large-scale parallelization to form a nanopore array, so that the problem that the existing solid state nanopore array sequencing chip can only be applied to laboratories is broken through, and the chip can be widely applied to industrial mass production.
Drawings
Fig. 1 to 16 are schematic structural diagrams of steps in the preparation process of the silicon-based nanopore array sequencing chip of the present invention, wherein fig. 16 is a schematic structural diagram of the silicon-based nanopore array sequencing chip of the present invention.
Fig. 17 is a schematic flow chart of a method for preparing a silicon-based nanopore array sequencing chip according to the present invention.
Description of the element reference numerals
10. Silicon substrate
101. Common cavity
11. A first dielectric layer
111. Nano-pores
12. Second dielectric layer
121. Hollow cavity
122. Metal
123. Metal layer
124. Partial metal layer
13. Electrode for electrochemical cell
131. Electrode material layer
141. Photoresist layer
142. Patterned photoresist layer
D1 Cross-sectional minimum dimension of cavity
D2 Size of the nanopore
L pitch
S1 to S7
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.
Example one
As shown in fig. 17, this embodiment provides a method for preparing a silicon-based nanopore array sequencing chip, where the method includes the following steps:
as shown in fig. 17 and fig. 1, step S1 is performed to provide a silicon substrate 10, and a first dielectric layer 11 and a second dielectric layer 12 with different materials are sequentially deposited on a front surface of the silicon substrate 10.
The orientation of the crystal planes of the silicon substrate 10 is not limited as long as etching thereof to form the common cavity 101 (as shown in fig. 14) can be achieved in the subsequent etching step. In this embodiment, the common cavity 101 is formed by wet etching using a potassium hydroxide solution, so that the silicon substrate 10 is selected as a (110) silicon substrate in this embodiment from the viewpoint of etching rate.
As an example, the first dielectric layer 11 and the second dielectric layer 12 may be formed using an existing conventional deposition process. In this embodiment, a Chemical Vapor Deposition (CVD) process is selected to form the first dielectric layer 11 and the second dielectric layer 12.
For example, the silicon substrate 10 may have a thickness of 500 to 1000 μm, for example, 500 to 600, 700, 800, 900, 1000 μm, the first dielectric layer 11 may have a thickness of 10 to 1000nm, for example, 10 to 50, 100, 200, 300, 500, 700, 800, 900, 1000nm, and the second dielectric layer 12 may have a thickness of 10 to 100 μm, for example, 10 to 50, 100, 1000, 10, 40, 60, 80, 100 μm. In this embodiment, the thickness of the silicon substrate 10 is 700 μm, the thickness of the first dielectric layer 11 is 200nm, and the thickness of the second dielectric layer 12 is 500nm.
As an example, the materials of the first dielectric layer 11 and the second dielectric layer 12 are different for facilitating the subsequent processThe control of the etching step is performed. The material of the first dielectric layer 11 may be selected from SiN and SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 The material of the second dielectric layer 12 may also be selected from SiN and SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 As long as the two materials are different. Based on a better selective etching ratio, in this embodiment, the first dielectric layer 11 is selected to be SiN material, and the second dielectric layer 12 is selected to be SiO material 2 A material.
As shown in fig. 17 and 5, step S2 is performed to form a plurality of cavities 121 penetrating through the second dielectric layer 12 in the second dielectric layer 12 by photolithography and etching processes. The plurality of cavities 121 formed by this step provide a basis for the subsequent formation of a plurality of nanopores 111 (as shown in FIG. 15) in the first dielectric layer 11 in parallel and form separate sample storage chambers for the present sequencing chip.
As shown in fig. 2 to 5, as an example, a specific method for forming a plurality of cavities 121 is provided, which includes:
2-1), as shown in fig. 2 and 3, coating a photoresist layer 141 on the surface of the second dielectric layer 12 and patterning to form a patterned photoresist layer 142; the shape of the openings of the patterned photoresist layer 142 is specifically realized by a photolithographic mask according to actual needs, and is not limited herein.
2-2), as shown in fig. 4, etching the second dielectric layer 12 based on the patterned photoresist layer 142 to form a plurality of cavities 121 penetrating the second dielectric layer 12; the cavity 121 may be formed by a wet method or a dry etching method, for example, when the second dielectric layer 12 is selected to be SiO in the embodiment 2 When the material is used, the cavity 121 can be formed by etching with a BHF wet etching solution or dry etching with RIE.
2-3) and the patterned photoresist layer 142 is removed as shown in fig. 5.
The arrangement of the plurality of cavities 121 in the second dielectric layer 12 has a great influence on the arrangement of the plurality of subsequently formed nano-holes 111 in the first dielectric layer 11, so that the arrangement of the plurality of cavities 121 in the second dielectric layer 12 is designed according to actual needs. In consideration of reducing the process complexity, as shown in fig. 13, in the present embodiment, a plurality of the cavities 121 are selected to be arranged in a regular array, where a distance L between two adjacent rows of the cavities 121 is equal to a distance L between two adjacent cavities 121; the pitch L is generally between 200nm and 10 μm, preferably 1 μm in this embodiment.
The cross-sectional shape of the cavity 121 is not limited, and the cavity having a regular cross-sectional shape may be a cavity having an irregular cross-sectional shape. In view of reducing the complexity of the process, it is preferable to provide the cross-sectional shape of the cavity 121 with a regular shape, which may be, for example, a square, a rectangle, a circle, or an ellipse. Since the subsequent nano-holes are formed by breaking down in the area where the first dielectric layer 11 corresponding to the cavity 121 is located, and the positions of the nano-holes are uncertain, if the cross section of the cavity 121 is set to be irregular, the nano-holes 111 may appear in the irregular area corresponding to the cavity 121, so that the communication effect between the cavity 121 and the nano-holes 111 is reduced, and the subsequent detection accuracy is affected. In this embodiment, the cross-sectional shape of the cavity 121 is preferably rectangular, and the cross-sectional shapes of a plurality of cavities 121 are all rectangular.
As shown in fig. 16, the cross-sectional minimum dimension D1 of the cavity refers to a minimum value that can represent the cross-sectional dimension of the cavity. For example, when the cross section of the cavity 121 is a square, D1 refers to a side length of the square; when the cross section of the cavity 121 is rectangular, D1 refers to the width side length of the rectangle; when the cross-section of the cavity 121 is circular, D1 refers to the diameter of the circle; when the cross-section of the cavity 121 is an ellipse, D1 refers to the minor axis of the ellipse. By way of example, the cavity has a cross-sectional minimum dimension D1 of between 50nm and 5000nm, which may be, for example, 50nm, 100nm, 500nm, 1000nm, 2000nm, 3000nm, 4000nm, 5000nm. The cross-sectional minimum dimension D1 of the cavity is chosen to be 500nm in this embodiment.
As shown in fig. 17 and fig. 7, step S3 is performed to fill metal 122 (as shown in fig. 6) into the cavities 121, so as to form metal layers 123 (as shown in fig. 7). The number of metal layers 123 formed by this step provides a basis for electrical connection to electrodes in the subsequent formation of the nanopore 111 by breaking down the first dielectric layer 11.
As shown in fig. 6 and 7, as an example, a specific method for forming a plurality of the metal layers 123 is provided, which includes:
3-1), as shown in fig. 6, depositing a layer of the metal 122 on the second dielectric layer 12 by using a metal deposition process, and completely filling the metal 122 into the plurality of cavities 121; the metal 122 may be formed by conventional metal deposition processes, such as magnetron sputtering, physical vapor deposition coating, and the like.
3-2), as shown in fig. 7, a chemical mechanical polishing process (CMP) is used to remove the metal 122 on the second dielectric layer 12, and only the metal 122 in the cavity 121 remains, so as to form a plurality of metal layers 123.
Since the metal layer 123 is subsequently melted and removed In the presence of the electrode, and needs to be electrically connected with the electrode to form a nanopore, the material of the metal layer 123 is selected to have good conductivity and a low melting point, such as Cd, sn, in, or Bi.
As shown in fig. 17, fig. 12, and fig. 13, fig. 13 is a top view of fig. 12, and then step S4 is performed to form a plurality of electrodes 13 on the second dielectric layer 12, wherein a plurality of the electrodes 13 are correspondingly formed above a plurality of the metal layers 123, and each of the electrodes 13 has a portion exposed and corresponding to the metal layer 123. Each electrode 13 is exposed and a part of the metal layer 123 corresponding to the electrode is exposed, so that when the metal layer 123 is removed by subsequent melting, molten fluid can flow out through the exposed part. The step can realize the large-scale parallel formation of the electrodes corresponding to the plurality of nano holes, has small process fluctuation and easy control, and provides a foundation for forming the plurality of nano holes in a breakdown mode subsequently.
As shown in fig. 8 to 12, as an example, there is provided a specific method of forming a plurality of the electrodes 13, including:
4-1), as shown in fig. 8 to 10, fig. 10 is a top view of fig. 9, a photoresist layer 141 is coated on a surface of the second dielectric layer 12 and patterned to form a patterned photoresist layer 142, a portion of the metal layer 124 corresponding to the patterned photoresist layer 142 is exposed from the patterned photoresist layer 142, as shown in fig. 10, the patterned photoresist layer 142 covers a portion of the upper and lower ends of the metal layer 123, the exposed portion is the portion of the metal layer 124, and the patterned photoresist layer 142 exposes portions of the left and right ends of the second dielectric layer 12.
4-2), as shown in fig. 11, a metal deposition process is used to deposit a layer of electrode material 131 on the patterned photoresist layer 142.
4-3), as shown in fig. 12, removing the patterned photoresist layer 142, and polishing the electrode material layer 131 by using a chemical mechanical polishing process to form a plurality of electrodes 13, so that each electrode 13 is exposed to a portion corresponding to the metal layer 123 and forms a bridge-like structure connection on the second dielectric layer 12.
The electrode 13 is subsequently used as an electrode layer of a chip, and it is ensured that the metal layer 123 is not melted when removed, so the material of the electrode 13 is preferably a material with good electrical conductivity and a high melting point, for example, cu, al, tiN, au, or Pt can be selected.
As shown in fig. 17 and 14, step S5 is performed to etch the back surface of the silicon substrate 10, so as to form a common cavity 101 penetrating through the silicon substrate 10, and the metal layer 123 is exposed from the common cavity 101. The common chamber 101 serves as a holding chamber for the chip electrolyte.
By way of example, the common cavity 101 may be formed using a dry or wet etch. The embodiment chooses to form the common cavity 101 by wet etching with a potassium hydroxide solution.
As shown in fig. 17 and fig. 15, step S6 is performed to fill an electrolyte into the common cavity 101, and apply a breakdown voltage between the electrodes 13 and the electrolyte to break down the first dielectric layer 11, so as to form a nanopore 111 in the corresponding first dielectric layer 11 under each metal layer 123. Therefore, a plurality of the nano holes 111 are formed in parallel at one time, the process fluctuation is small, the control is easy, and the uniformity of the pore size of the nano holes is high.
The principle of forming the nanopore 111 is as follows: when a breakdown voltage is applied across the first dielectric layer 11, positive and negative charge accumulation is induced on the surface of the first dielectric layer 11, positive charge accumulation occurs on the surface of the first dielectric layer 11 on the anode side, and negative charge accumulation occurs on the surface of the first dielectric layer 11 on the cathode side, thereby generating a potential difference across the membrane; under the driving of the potential difference, positive and negative charges on the surface of the first dielectric layer 11 permeate and leak to the opposite side through defects in the material of the first dielectric layer 11, accumulation of trapped charges is formed in the material of the first dielectric layer 11, and joule heating is generated; when the trapped charges are accumulated to a certain extent, the inside of the first dielectric layer material is physically damaged, and the nanopore 111 is formed. The magnitude of the breakdown voltage and the voltage application time affect the size of the pore diameter of the nanopore.
By way of example, the size D2 of the nanopore 111 is generally between 0.1nm and 100nm, preferably between 1nm and 2 nm. As described above, in the present embodiment, when the material of the first dielectric layer 11 is SiN and the thickness is 200nm, the size D2 of the nanopore 111 formed is about 1.5nm when a breakdown voltage of 1V to 50V, preferably 15V to 25V, and more preferably 20V is applied to both ends thereof.
As shown in fig. 17 and 16, step S7 is finally performed to invert the structure formed as described above, melt the metal layer 123, and remove the melted metal layer 123 by vacuum suction. The molten metal layer 123 is more easily removed from the cavity 121 by gravity due to the inverted structure during vacuum pumping. Thus, the silicon-based nanopore array sequencing chip is formed.
As described above, the preparation method for forming the silicon-based nanopore array sequencing chip in the embodiment is based on the existing mature silicon micromachining process combined with the breakdown principle of the dielectric material, has small and controllable process fluctuation, low cost and simple process, and is suitable for controllable large-scale parallel formation of nanopore arrays, thereby being suitable for industrial mass production.
Example two
The present embodiment provides a silicon-based nanopore array sequencing chip, which can be prepared by the preparation method of the first embodiment, and the beneficial effects achieved by the silicon-based nanopore array sequencing chip can be found in the first embodiment, which are not described in detail below.
As shown in fig. 16, the sequencing chip comprises, in order from bottom to top: the structure comprises a silicon substrate 10, a first dielectric layer 11, a second dielectric layer 12 and a plurality of electrodes 13, wherein the first dielectric layer 11 and the second dielectric layer 12 are made of different materials;
a common cavity 101 penetrating through the silicon substrate 10 is formed in the silicon substrate 10;
a plurality of nano holes 111 penetrating through the first dielectric layer 11 are formed in the first dielectric layer;
a plurality of cavities 121 penetrating through the second dielectric layer 12 are formed in the second dielectric layer;
a plurality of the cavities 121 are correspondingly arranged on a plurality of the nanopores 111; a plurality of the electrodes 13 are correspondingly arranged on the plurality of cavities 121 and formed on the surface of the second dielectric layer 12, and the exposed part of each electrode 13 forms a bridge-shaped structure with the corresponding cavity 121; the common cavity 101 exposes a number of the cavities 12 and a number of the nanopores 111.
Illustratively, the silicon substrate 10 has a thickness of 500 μm to 1000 μm, the first dielectric layer 11 has a thickness of 10nm to 1000nm, and the second dielectric layer 12 has a thickness of 10nm to 100 μm.
As an example, the size D2 of the nanopore 111 is between 0.1nm and 100 nm.
As an example, the cross-sectional shape of several of the cavities 121 is square, rectangular, circular or oval.
Illustratively, the cavity 121 has a cross-sectional minimum dimension D1 of between 50nm and 5000nm.
As an example, the cavities 121 are the same and are arranged in an array, and a distance L between two adjacent rows of the cavities 121 is equal to a distance L between two adjacent cavities.
As an example, the pitch L is between 200nm and 10 μm.
As an example, the material of the first dielectric layer 11 is SiN or SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 (ii) a The second dielectric layer 12 is made of SiN or SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 。
As an example, the material of the electrode 13 is Cu, al, tiN, au, or Pt.
In summary, the present invention provides a silicon-based nanopore array sequencing chip and a method for preparing the same, wherein the sequencing chip is based on the existing mature silicon micromachining process combined with the breakdown principle of dielectric materials, has small and controllable process fluctuation, low cost and simple process, and is suitable for controllable large-scale parallel formation of nanopore arrays, thereby breaking through the fact that the existing solid state nanopore array sequencing chip can only be applied to laboratories, and can be widely applied to industrial mass production. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (15)

1. A preparation method of a silicon-based nanopore array sequencing chip is characterized by comprising the following steps:
providing a silicon substrate, and sequentially depositing a first dielectric layer and a second dielectric layer which are made of different materials on the front surface of the silicon substrate;
forming a plurality of cavities penetrating through the second dielectric layer in the second dielectric layer through photoetching and etching processes;
a plurality of the cavities are filled with metal, forming a plurality of metal layers;
forming a plurality of electrodes on the second dielectric layer, wherein the plurality of electrodes are correspondingly formed above the plurality of metal layers, and the exposed part of each electrode is connected with the corresponding metal layer in a bridge-shaped structure;
etching the back surface of the silicon substrate to form a common cavity penetrating through the silicon substrate;
filling electrolyte into the common cavity, applying breakdown voltage between the electrodes and the electrolyte, and breaking down the first dielectric layer to form nano holes in the first dielectric layer corresponding to each metal layer;
and (3) inverting the structure, melting the metal layer, and removing the melted metal layer by adopting a vacuum suction mode.
2. The method for preparing a silicon-based nanopore array sequencing chip of claim 1, wherein: the silicon substrate is a (110) silicon substrate; forming the first dielectric layer and the second dielectric layer by adopting a chemical vapor deposition process; and etching the back surface of the silicon substrate by adopting a potassium hydroxide solution wet method to form the common cavity.
3. The method for preparing a silicon-based nanopore array sequencing chip of claim 1, wherein: the metal layer is made of Cd, sn, in or Bi; the electrode is made of Cu, al, tiN, au or Pt.
4. The method of preparing a silicon-based nanopore array sequencing chip of claim 1, wherein the step of forming the plurality of cavities comprises:
coating a photoresist layer on the surface of the second dielectric layer and patterning to form a patterned photoresist layer;
etching the second dielectric layer based on the patterned photoresist layer to form a plurality of cavities penetrating through the second dielectric layer;
and removing the patterned photoresist layer.
5. The method of claim 1, wherein the step of forming the plurality of metal layers comprises:
depositing a layer of metal on the second dielectric layer by adopting a metal deposition process, and completely filling a plurality of cavities with the metal;
and removing the metal on the second dielectric layer by adopting a chemical mechanical polishing process, and only retaining the metal in the cavity.
6. The method of preparing a silicon-based nanopore array sequencing chip of claim 1, wherein the step of forming a plurality of said electrodes comprises:
coating a photoresist layer on the surface of the second dielectric layer and patterning to form a patterned photoresist layer, wherein the exposed part of the patterned photoresist layer corresponds to the metal layer;
depositing an electrode material layer on the patterned photoresist layer by adopting a metal deposition process;
and removing the patterned photoresist layer, and grinding the electrode material layer by adopting a chemical mechanical grinding process to form a plurality of electrodes.
7. The silicon-based nanopore array sequencing chip is characterized by comprising the following components in sequence from bottom to top: the silicon chip comprises a silicon substrate, a first dielectric layer, a second dielectric layer and a plurality of electrodes, wherein the first dielectric layer and the second dielectric layer are made of different materials;
a common cavity penetrating through the silicon substrate is formed in the silicon substrate;
a plurality of nano holes penetrating through the first dielectric layer are formed in the first dielectric layer;
a plurality of cavities penetrating through the second dielectric layer are formed in the second dielectric layer;
the plurality of cavities are correspondingly arranged on the plurality of nano holes; the plurality of electrodes are correspondingly arranged on the plurality of cavities and formed on the surface of the second dielectric layer, and the exposed part of each electrode and the corresponding cavity form a bridge-shaped structure; the common cavity exposes a plurality of the cavities and a plurality of the nanopores.
8. The silicon-based nanopore array sequencing chip of claim 7, wherein: the thickness of the silicon substrate is between 500 and 1000 microns, the thickness of the first dielectric layer is between 10 and 1000nm, and the thickness of the second dielectric layer is between 10 and 100 microns.
9. The silicon-based nanopore array sequencing chip of claim 7, wherein: the size of the nano-pores is between 0.1nm and 100 nm.
10. The silicon-based nanopore array sequencing chip of claim 7, wherein: the cross sections of the cavities are square, rectangular, circular or oval.
11. The silicon-based nanopore array sequencing chip of claim 10, wherein: the minimum size of the cross section of the cavity is between 50nm and 5000nm.
12. The silicon-based nanopore array sequencing chip of claim 7, wherein: the cavities are the same and are arranged in an array mode, and the space between every two adjacent rows of cavities is equal to the space between every two adjacent cavities.
13. The silicon-based nanopore array sequencing chip of claim 12, wherein: the distance is between 200nm and 10 mu m.
14. The silicon-based nanopore array sequencing chip of claim 7, wherein: the first dielectric layer is made of SiN or SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 (ii) a The second dielectric layer is made of SiN or SiO 2 、Al 2 O 3 、HfO 2 ZnO or TiO 2 。
15. The silicon-based nanopore array sequencing chip of claim 7, wherein: the electrode is made of Cu, al, tiN, au or Pt.
CN202110335019.1A 2021-03-29 2021-03-29 Silicon-based nanopore array sequencing chip and preparation method thereof Pending CN115141750A (en)

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