CN115132820A - Semiconductor device and control method of semiconductor device - Google Patents

Semiconductor device and control method of semiconductor device Download PDF

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Publication number
CN115132820A
CN115132820A CN202110333701.7A CN202110333701A CN115132820A CN 115132820 A CN115132820 A CN 115132820A CN 202110333701 A CN202110333701 A CN 202110333701A CN 115132820 A CN115132820 A CN 115132820A
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China
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region
semiconductor device
plate
field plate
electrode
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CN202110333701.7A
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何乃龙
张森
许杰
姚玉恒
邹敏
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202110333701.7A priority Critical patent/CN115132820A/en
Priority to PCT/CN2021/119828 priority patent/WO2022205803A1/en
Publication of CN115132820A publication Critical patent/CN115132820A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention relates to a semiconductor device, which comprises a device main body, a field plate structure and a plurality of electrodes, wherein the field plate structure comprises a plurality of plate bodies which are separated from each other; the semiconductor device further includes a control circuit including: the output ends are connected with a plate body; a plurality of input terminals, different input terminals being connected to different electrodes of the device body; and the control unit is used for judging the working state of the device main body according to the input signals of the input ends and controlling the voltage output by the output ends according to the working state so as to control the potential of each plate body. The invention dynamically controls the potential of each plate body by judging the working state of the device, so that the device main body can achieve the optimal performance under different working states according to the requirements under the working states.

Description

Semiconductor device and control method of semiconductor device
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a method for controlling the semiconductor device.
Background
The field plate technique is an edge termination technique that can be used for RESURF (reduced surface electric field). The exemplary field plate technique is primarily concerned with optimizing the static BV (reverse breakdown voltage) of the device.
Disclosure of Invention
In view of the above, there is a need for an improved field plate technology for a device, and a semiconductor device and a control method for a semiconductor device that can achieve other performance of the device.
A semiconductor device comprising a device body including a field plate structure and a plurality of electrodes, the field plate structure comprising a plurality of mutually separated plate bodies; the semiconductor device further includes a control circuit including: the output ends are connected with a plate body; a plurality of input terminals, different input terminals being connected to different electrodes of the device body; and the control unit is used for judging the working state of the device main body according to the input signals of the input ends and controlling the voltage output by the output ends according to the working state so as to control the potential of each plate body.
According to the semiconductor device, the field plate structure comprises the plurality of plate bodies which are separated from each other, so that the control unit can independently and accurately adjust the potential of each position of the field plate structure. The control unit dynamically controls the potential of each plate body by judging the working state of the device, so that the device main body can achieve the best performance under different working states according to the requirements under the working states.
In one embodiment, the field plate structure is at least one of a longitudinal field plate, a floating field plate, a polysilicon field plate, a metal field plate and a high-resistance surrounding field plate.
In one embodiment, the plurality of electrodes includes a gate electrode, a source electrode, and a drain electrode.
In one embodiment, the device body is a laterally diffused metal oxide semiconductor field effect transistor.
In one embodiment, each plate is disposed between a source region and a drain region of the device body.
In one embodiment, the device body further comprises a field plate insulating medium disposed between each of the plate bodies and the drift region, each of the plate bodies and field plate insulating medium being disposed on or extending into the drift region.
In one embodiment, each of the plate bodies includes an insertion portion extending downward into the drift region from an upper surface of the drift region, and an electrode lead connected to the insertion portion.
In one embodiment, each of the board bodies includes a plurality of the insertion portions, the insertion portions of each of the board bodies are aligned in a channel width direction of the semiconductor device, and the insertion portions of each of the board bodies are electrically connected to the same electrode lead-out.
In one embodiment, the control unit comprises an application specific integrated circuit.
In one embodiment, the application specific integrated circuit is a programmable circuit.
In one embodiment, the device body and the control circuit are located on different chips and packaged in different packages, and the packages of the device body include gate pins, source pins, drain pins, and board pins that are equal in number to the boards and are connected to the boards in a one-to-one correspondence.
In one embodiment, the device body and the control circuit are located on different chips and packaged in the same package, each of the plate bodies of the device body is electrically connected to the plurality of output terminals of the control circuit in a one-to-one correspondence manner through a lead, and the gate electrode, the source electrode, and the drain electrode of the device body are electrically connected to the plurality of input terminals of the control circuit in a one-to-one correspondence manner through leads.
In one embodiment, the device body and the control circuit are integrated on a same chip, and each plate body, the gate electrode, the source electrode and the drain electrode of the device body are electrically connected to the control circuit through a metal interconnection line.
In one embodiment, the control unit is configured to control the electric potential of each plate body so that the electric potential between the source region and the drain region of the device body is uniform when the operating state is a static reverse bias state.
A semiconductor device comprising a device body and control circuitry, the device body being a lateral diffused metal oxide semiconductor field effect transistor, the device body comprising: a substrate having a second conductivity type; the drift region is arranged in the substrate and has a first conduction type, and the first conduction type and the second conduction type are opposite conduction types; the first conduction type well region is arranged on the first side of the drift region; a second conductivity type well region disposed on a second side of the drift region, the second side being opposite to the first side; the drain region is arranged in the first conduction type well region and has a first conduction type; a source region of the first conductivity type disposed in the second conductivity type well region; the leading-out region is arranged in the second conductive type well region and on the surface of the source region opposite to the drain region, and has a second conductive type; the first field oxide layer is arranged on the drift region, is positioned between the source region and the drain region in the transverse direction and is close to the second conduction type well region; a second field oxide layer extending from above the drift region to above the first conductivity type well region and laterally between the source region and the drain region; a gate extending from above the first field oxide layer to the source region; the field plate structure comprises a plurality of plate bodies which are separated from each other; the field plate insulating medium is arranged between each plate body and the drift region, and each plate body and the field plate insulating medium are arranged on the drift region or extend into the drift region; the control circuit includes: the output ends are connected with a plate body; a plurality of input terminals, different input terminals being connected to different electrodes of the device body; and the control unit is used for judging the working state of the device main body according to the input signals of the input ends and controlling the voltage output by the output ends according to the working state so as to control the potential of each plate body.
In one embodiment, each plate body includes an insertion portion extending downward into the drift region from an upper surface of the drift region, and an electrode lead electrically connected to the insertion portion.
A control method of a semiconductor device, comprising: acquiring the potentials of a source electrode, a drain electrode and a grid electrode of the semiconductor device; judging the working state of the semiconductor device according to the potentials of the source electrode, the drain electrode and the grid electrode; and controlling the potential of each mutually separated plate body of the field plate structure of the semiconductor device according to the working state.
According to the control method of the semiconductor device, the potential of each plate body is dynamically controlled by judging the working state of the device, so that the device main body can achieve the best performance under different working states according to the requirements under the working states.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the best modes of presently understanding these inventions.
FIG. 1 is a pin diagram of a packaged chip formed from a device body in one embodiment;
FIG. 2 is a schematic diagram of the structure of a device body in one embodiment;
FIG. 3 is a cross-sectional view taken along line A-A' of FIG. 2;
fig. 4 is a flowchart of a control method of a semiconductor device in an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
In order to dynamically optimize a field plate structure of a device, the present application provides a semiconductor device comprising a device body and a control circuit. The device body includes a field plate structure and a plurality of electrodes (input and output electrodes of the device). The field plate structure may be any field plate and similar field plate technologies, and the field plate structure includes a plurality of separated plate bodies (there may be a filling structure or other non-conductive structure between the separated plate bodies). The control circuit comprises a control unit, a plurality of output ends and a plurality of input ends. Wherein each output terminal is connected with one of the plate bodies, and different input terminals are connected with different electrodes of the device main body. The control unit judges the working state of the device main body according to the input signals of the input ends and controls the voltage output by the output ends according to the working state, so that the potential of each plate body is controlled. The operating state may be a static reverse bias state, a linear state, a saturated operating state, or the like. For different working states, the control unit can control the potential of each plate body according to the reverse breakdown voltage requirement, the conduction capability requirement, the safe working area requirement, the reliability requirement and the like of the device.
Each plate body of field plate structure separates each other and indicates: the plate bodies are not directly electrically connected with each other, so that the control unit can apply different voltages to different plate bodies to enable the plate bodies to have different potentials.
According to the semiconductor device, the field plate structure comprises the plurality of plate bodies which are separated from each other, so that the control unit can independently and accurately adjust the potential of each position of the field plate structure. The control unit dynamically controls the potential of each plate body by judging the working state of the device, so that the device main body can achieve the best performance under different working states according to the requirements under the working states.
In one embodiment of the present application, the device body includes a gate electrode, a source electrode, and a drain electrode, and the control circuit includes three input terminals respectively connected to the electrodes in a one-to-one correspondence. The control unit can judge the working state of the device body through the potentials of the gate, the source and the drain of the device.
In one embodiment of the present application, the device body is a Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET). In other embodiments, the device body may also be other semiconductor devices having field plate structures (e.g., field plate structures for RESURF).
In one embodiment of the present application, each plate body of the field plate structure is disposed between the source and drain regions of the device body in the lateral direction (the length direction of the conductive channel). The control unit can adjust the surface electric field between the source region and the drain region of the device body by adjusting the output voltage of each output terminal. It is understood that the source/drain regions and the bodies have a certain height, so that the bodies and the source/drain regions may not be located on the same horizontal plane.
In one embodiment of the present application, the control unit is configured to control the potentials of the plate bodies so that the potentials between the source region and the drain region of the device body are uniform when the operating state of the device body is a static reverse bias state. Specifically, if the device is in a static reverse bias state, then according to the RESURF principle, the electric field on the surface of the device needs to be uniformly distributed, that is, the electric potential from the source end to the drain end is uniform, and at this time, the electric potential of each plate body can be controlled by the control unit, so that the device is at the maximum limit of withstand voltage.
In one embodiment of the present Application, the control unit comprises an Application Specific Integrated Circuit (ASIC). The ASIC module can determine the working state of the device body according to the potentials (e.g., the potentials of the source and drain gates of the device body) collected from the electrodes of the device body, and provide different potentials for the field plate structure according to different working states of the device body, so that the device body can achieve the best performance in different working states according to the requirements of the working states. The function that the control unit judges the working state of the device main body according to the input signals of the input ends and controls the potential of each plate body according to the working state is easy to realize by adopting a special application integrated circuit.
In one embodiment of the present application, the ASIC is a Programmable Device, such as a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA), etc. Through programming the control unit, the control unit can judge the working state of the device main body according to the electric potential collected from each electrode of the device main body, and accordingly the electric potential corresponding to the field plate structure set in the programming according to the working state can independently control the electric potential of each section of plate body. In one embodiment of the present application, the control unit supports the user to program the control unit himself as needed to adjust the correspondence between the potential of each segment of the plate body and the operating state of the device main body.
In one embodiment of the present application, the device body and the control circuit are on different chips and packaged in different packages. Generally, the device body and the control circuit are different in device type, and electrical connection after being packaged separately is easier to realize in actual production. In one embodiment of the present application, the package body of the device body includes a gate lead, a source lead, a drain lead, and board body leads that are equal in number to the board bodies and are connected to the board bodies in a one-to-one correspondence. Referring to fig. 1, in one embodiment of the present application, a packaged chip IC1 of a device body includes a gate lead G, a source lead S, a drain lead D, and N board leads (Out 1-Out N), and the ellipses in fig. 1 indicate that a plurality of board leads are omitted and not shown. Correspondingly, the packaged chip of the control circuit comprises three input pins which are connected with a grid electrode pin G, a source electrode pin S and a drain electrode pin D, and also comprises N output pins which are correspondingly connected with the N plate pins one by one.
In another embodiment of the present application, the device body and the control circuit are on different chips and packaged in the same package. And each plate body of the device main body is electrically connected with the plurality of output ends of the control circuit in a one-to-one correspondence manner through leads. And the gate electrode, the source electrode and the drain electrode of the device main body are respectively and correspondingly electrically connected with the plurality of input ends of the control circuit one by one through leads.
In another embodiment of the present application, the device body and the control circuit are integrated on the same chip, and the respective plate bodies, the gate electrode, the source electrode, and the drain electrode of the device body are electrically connected to the control circuit through metal interconnection lines.
The structure of the semiconductor device of the present application is explained below by a specific embodiment. Referring to fig. 2 and 3, fig. 2 is a schematic structural view of a device body in one embodiment, and fig. 3 is a sectional view taken along line a-a' of fig. 2. In this embodiment, the device body is a laterally diffused metal oxide semiconductor Field effect transistor, and the Field Plate structure adopts a VFP (Vertical Field Plate) technology. It will be appreciated that the field plate is not limited to VFP technology and may be a conventional polysilicon (poly) field plate, metal (metal) field plate, other floating (floating) field plates, high resistance wrap around field plates, etc. In the embodiments shown in fig. 2 and 3, each of the N plate bodies Out1 to Out N of the field plate structure includes an insertion portion 122 extending downward into the drift region 102 from the upper surface of the drift region 102 of the LDMOS, and an electrode lead 124 connected to the insertion portion 122. In order to facilitate the position of the relevant structure to be viewed from the figure, structures such as the drift region 102 and the electrode lead-out 124 are subjected to a transparentization process in fig. 2. In one embodiment of the present application, each plate body may include a plurality of insertion portions 122, and the insertion portions 122 of each plate body are electrically connected to the same electrode lead 124. In the embodiment shown in fig. 2 and 3, the respective insertion portions 122 of each plate body are aligned in the width direction of the conductive channel. In one embodiment of the present application, the material of the insertion portion 122 is polysilicon. In one embodiment of the present application, a field plate insulating medium is further disposed between the insertion portion 122 and the drift region 102 (i.e., around and at the bottom of the insertion portion 122); optionally, the field plate insulating medium may be made of silicon dioxide. In another embodiment of the present application, the plate bodies and the field plate insulating medium are provided on the drift region.
In one embodiment of the present application, the plates may be equal in size; in other embodiments, the sizes of the plates may not be equal.
In the embodiment shown in fig. 2 and 3, the device body includes a substrate 101, a drift region 102, a source region 104, and a drain region 110. The substrate 101 has a second conductivity type. The drift region 102 is provided in the substrate 101 and has a first conductivity type. The source region 104 and the drain region 110 have a first conductivity type and are respectively disposed on one side of the drift region 102. In the embodiment shown in fig. 2 and 3, the device is an NLDMOS, the substrate 101 is a P-type substrate, and the drift region 102 is an N-type drift region (which may be an N-drift region) disposed on the substrate 101.
In the embodiment shown in fig. 2 and 3, the device body further includes a second conductivity type well region 107. The second conductivity type well region 107 is a source second conductivity type region of the LDMOS device, the source region 104 and the lead-out region 103 are disposed in the second conductivity type well region 107, and the concentration of the second conductivity type well region 107 will affect the drift region depletion and the threshold voltage. In one embodiment of the present application, the second conductivity type ion concentration of second conductivity type well region 107 is smaller than the second conductivity type ion concentration of extraction region 103.
In the embodiment shown in fig. 2 and 3, the device body further comprises a first conductivity type well region 109. The first conductivity type well 109 is an N-type region around the drain terminal, and the drain region 110 is disposed in the first conductivity type well 109 to optimize the forward conduction current.
In the embodiment shown in fig. 2 and 3, the device body further includes a gate 108, a field oxide layer 112, and an extraction region 103. The field oxide layer 112 includes a first field oxide layer and a second field oxide layer, wherein the first field oxide layer is disposed on the drift region 102, laterally between the source region 104 and the drain region 110, and disposed adjacent to the second conductive type well region 107; the second field oxide layer extends from above the drift region 102 onto the first conductivity type well region 109, laterally between the source region 104 and the drain region 110. A gate 108 of polysilicon material extends from above the first field oxide layer towards the source region 104. The extraction region 103 is a P-type doped region (specifically, a P + doped region), is disposed on a side of the source region 104 away from the gate 108, and is in contact with the source region 104.
In one embodiment of the present application, the substrate 101 is a semiconductor substrate, and the material thereof may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. In the embodiment shown in fig. 2, the substrate 101 is made of monocrystalline silicon.
In the embodiment shown in fig. 2, the gate 108 is a polysilicon material, and in other embodiments, a metal nitride, a metal silicide or the like may be used as the material of the gate 108.
In one embodiment of the present application, the field oxide layer 112 is silicon dioxide.
The present application accordingly provides a method for controlling a semiconductor device, see e.g. 4, which in one embodiment of the present application comprises the steps of:
and S410, acquiring the potentials of a source electrode, a drain electrode and a grid electrode of the semiconductor device.
The semiconductor device may be the device body described in any of the preceding embodiments.
And S420, judging the working state of the semiconductor device according to the potentials of the source electrode, the drain electrode and the grid electrode.
The operating state may be a static reverse bias state, a linear state, a saturated operating state, or the like.
And S430, controlling the potential of each mutually separated plate body of the field plate structure of the semiconductor device according to the working state.
For different working states, the potential of each plate body can be controlled according to the reverse breakdown voltage requirement, the conduction capability requirement, the safe working area requirement, the reliability requirement and the like of the device.
In one embodiment of the present application, when the operating state is a static reverse bias state, the potentials of the plate bodies are controlled such that the potentials between the source region and the drain region of the semiconductor device are uniform. Specifically, if the device is in a static reverse bias state, then according to the RESURF principle, the electric field on the surface of the device needs to be uniformly distributed, that is, the electric potential from the source end to the drain end is uniform, and at this time, the electric potential of each plate body can be controlled by the control unit, so that the device is at the maximum limit of withstand voltage.
According to the control method of the semiconductor device, the potential of each plate body is dynamically controlled by judging the working state of the device, so that the device main body can achieve the best performance under different working states according to the requirements under the working states.
It should be understood that, although the steps in the flowchart of fig. 4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in fig. 4 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternatively with other steps or at least a part of the steps or stages in other steps.
In one embodiment of the present application, the steps of the control method of the semiconductor device described in any one of the above embodiments are implemented by an ASIC. The ASIC module can judge the working state of the device according to the electric potential (such as the electric potential of a source drain grid of the device) collected from each electrode of the semiconductor device, and provides different electric potentials for the field plate structure according to different working states of the device, so that the device can achieve the best performance under different working states according to the requirements under the working states. The function that the control unit judges the working state of the device main body according to the input signals of the input ends and controls the potential of each plate body according to the working state is easy to realize by adopting a special application integrated circuit.
In one embodiment of the present application, the ASIC is a Programmable Device, such as a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA), etc. By programming the ASIC, the ASIC can judge the working state of the device according to the electric potential acquired from each electrode of the device, and the electric potential of each section of plate body is independently controlled according to the electric potential corresponding to the field plate structure set in the programming of the working state. In one embodiment of the application, the support user programs the ASIC by himself as required to adjust the correspondence between the potential of each board segment and the operating state of the device.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic depictions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A semiconductor device comprising a device body, wherein the device body comprises a field plate structure and a plurality of electrodes, the field plate structure comprising a plurality of mutually separated plate bodies; the semiconductor device further includes a control circuit including:
the output ends are connected with a plate body;
a plurality of input terminals, different input terminals being connected to different electrodes of the device body;
and the control unit is used for judging the working state of the device main body according to the input signals of the input ends and controlling the voltage output by the output ends according to the working state so as to control the potential of each plate body.
2. The semiconductor device of claim 1, wherein the field plate structure is at least one of a longitudinal field plate, a floating field plate, a polysilicon field plate, a metal field plate, and a high-resistance-wrap-around field plate.
3. The semiconductor device according to claim 1, wherein the plurality of electrodes comprises a gate electrode, a source electrode, and a drain electrode.
4. The semiconductor device of claim 3, wherein the device body is a laterally diffused metal oxide semiconductor field effect transistor.
5. The semiconductor device of claim 4, wherein each plate is disposed between a source region and a drain region of the device body.
6. The semiconductor device of claim 1, wherein the control unit comprises an application specific integrated circuit.
7. The semiconductor device according to claim 3, wherein the device body and the control circuit are located on different chips and packaged in different packages, and the packages of the device body include gate pins, source pins, drain pins, and board body pins that are equal in number to the board bodies and are connected to the board bodies in a one-to-one correspondence;
or, the device main body and the control circuit are located on different chips and packaged in the same package, each of the plate bodies of the device main body is electrically connected with the plurality of output ends of the control circuit in a one-to-one correspondence manner through leads, and the gate electrode, the source electrode and the drain electrode of the device main body are electrically connected with the plurality of input ends of the control circuit in a one-to-one correspondence manner through leads;
or, the device main body and the control circuit are integrated on the same chip, and each plate body, the gate electrode, the source electrode and the drain electrode of the device main body are electrically connected with the control circuit through metal interconnection lines.
8. The semiconductor device according to claim 3, wherein the control unit is configured to control a potential of each of the plate bodies so that a potential between a source region and a drain region of the device body is uniform when the operating state is a static reverse bias state.
9. A semiconductor device comprising a device body and a control circuit, wherein the device body is a lateral diffusion metal oxide semiconductor field effect transistor, the device body comprising:
a substrate having a second conductivity type;
the drift region is arranged in the substrate and has a first conduction type, and the first conduction type and the second conduction type are opposite conduction types;
the first conduction type well region is arranged on the first side of the drift region;
a second conductivity type well region disposed on a second side of the drift region, the second side being opposite to the first side;
a drain region arranged in the first conductivity type well region and having a first conductivity type;
a source region of the first conductivity type disposed in the second conductivity type well region;
the leading-out region is arranged in the second conductive type well region and on the surface of the source region opposite to the drain region, and has a second conductive type;
the first field oxide layer is arranged on the drift region, is positioned between the source region and the drain region in the transverse direction and is close to the second conduction type well region;
a second field oxide layer extending from the drift region to the first conductivity type well region and laterally between the source region and the drain region;
a gate extending from above the first field oxide layer to the source region;
the field plate structure comprises a plurality of plate bodies which are separated from each other;
the field plate insulating medium is arranged between each plate body and the drift region, and each plate body and the field plate insulating medium are arranged on the drift region or extend into the drift region;
the control circuit includes:
the output ends are connected with a plate body;
a plurality of input terminals, different input terminals being connected to different electrodes of the device body;
and the control unit is used for judging the working state of the device main body according to the input signal of each input end and controlling the voltage output by each output end according to the working state so as to control the potential of each plate body.
10. A control method of a semiconductor device, comprising:
acquiring the potentials of a source electrode, a drain electrode and a grid electrode of the semiconductor device;
judging the working state of the semiconductor device according to the potentials of the source electrode, the drain electrode and the grid electrode;
and controlling the potential of each mutually separated plate body of the field plate structure of the semiconductor device according to the working state.
CN202110333701.7A 2021-03-29 2021-03-29 Semiconductor device and control method of semiconductor device Pending CN115132820A (en)

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DE10313712B4 (en) * 2003-03-27 2008-04-03 Infineon Technologies Ag Lateral field-controllable semiconductor device for RF applications
DE102006055742B4 (en) * 2006-11-25 2011-07-14 Infineon Technologies Austria Ag Semiconductor device arrangement with a plurality of adjacent to a drift zone control electrodes
US8878154B2 (en) * 2011-11-21 2014-11-04 Sensor Electronic Technology, Inc. Semiconductor device with multiple space-charge control electrodes
CN110518056B (en) * 2019-08-02 2021-06-01 无锡华润上华科技有限公司 Lateral diffusion metal oxide semiconductor device and manufacturing method thereof
CN110459602A (en) * 2019-08-31 2019-11-15 电子科技大学 Device and its manufacturing method with longitudinal floating field plate
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