CN115132666A - Semiconductor structure, memory structure and preparation method thereof - Google Patents

Abstract

The application relates to a semiconductor structure, a memory structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and forming a plurality of active columns which are arranged at intervals in the substrate; the active column comprises a first connecting end, a second connecting end and a channel area positioned between the first connecting end and the second connecting end; etching the substrate to form a trench, wherein the trench defines the position of the word line structure; forming a filling mask layer in the groove; etching back the substrate to expose the filling mask layer and the second connecting ends of the active columns; and forming a side wall mask layer on the side wall of the filling mask layer and the side wall of the second connecting end, wherein the side wall mask layer and the filling mask layer jointly form a word line mask layer, and the word line mask layer defines the shape and the position of the word line structure. The preparation method of the semiconductor structure can form the word line structure based on the word line mask layer in the subsequent process, realizes the self-alignment in the process of forming the word line structure and simplifies the preparation flow.

Description

Semiconductor structure, memory structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure, a memory structure, and a method for manufacturing the same.

Background

Transistors are a key component of modern integrated circuits. In order to improve the control of the channel and reduce the short channel effect, a transistor with a vertical all-around gate structure is developed, wherein the corresponding transistor is also called a vertical gate all around transistor (VGAA for short). In VGAA transistors, the gate dielectric and gate electrode completely surround the channel region. This configuration achieves good control of the channel and reduces short channel effects.

Currently, the semiconductor industry has entered an era in which nanotechnology nodes with higher device density, higher performance, and lower price are sought, and the challenges of manufacturing and design have made the development of VGAA transistors face challenges from both manufacturing and design issues.

Disclosure of Invention

In view of the above, it is necessary to provide a semiconductor structure, a memory structure and a method for manufacturing the same.

The present application provides, according to some embodiments, a method of fabricating a semiconductor structure, comprising:

providing a substrate, and forming a plurality of active columns which are arranged at intervals in the substrate; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

etching the substrate to form a groove, wherein the groove defines the position of the word line structure;

forming a filling mask layer in the groove;

etching back the substrate to expose the filling mask layer and the second connecting end of each active column;

and forming a side wall mask layer on the side wall of the filling mask layer and the side wall of the second connecting end, wherein the side wall mask layer and the filling mask layer jointly form a word line mask layer, and the word line mask layer defines the shape and the position of a word line structure.

In one of the embodiments, the first and second electrodes are,

the providing of the substrate, forming a plurality of active pillars arranged in an array in the substrate, includes:

providing a substrate;

forming a first isolation groove in the substrate; the first isolation groove extends along a first direction;

filling a first isolation medium layer in the first isolation groove;

etching the substrate and the first isolation medium layer to form a second isolation groove; the second isolation groove extends along a second direction, and the first direction intersects with the second direction; the second isolation groove and the first isolation groove jointly isolate a plurality of active columns; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

and forming a second isolation medium layer in the second isolation groove.

The etching the substrate to form a trench includes:

and etching the first isolation medium layer to form a groove, wherein the groove defines the position of the word line structure.

In one embodiment, before forming the second isolation dielectric layer in the second isolation trench, the method for manufacturing a semiconductor structure further includes:

forming a plurality of bit line grooves arranged at intervals in the substrate, wherein the bit line grooves are positioned below the active pillars and extend along the first direction;

forming a metal silicide layer in the bit line groove;

forming a bit line on the surface of the metal silicide layer; the bit lines are located in the bit line grooves and extend along the first direction so as to sequentially connect the first connection ends of the active pillars located in the same column in series.

In one embodiment, before forming the bit line trench, the method for manufacturing a semiconductor structure further includes:

and forming a side wall protection layer on the side wall of the second isolation groove.

In one embodiment, the substrate comprises a silicon substrate; forming a metal silicide layer in the bit line trench includes:

forming a metal layer in the bit line groove;

and carrying out rapid thermal treatment on the obtained structure, so that the metal layer reacts with the substrate to form a metal silicide layer in the bit line groove.

In one embodiment, after forming a sidewall mask layer on the sidewall of the mask layer and the sidewall of the second connection terminal, the method for manufacturing a semiconductor structure further includes:

continuously etching back the second isolation dielectric layer and the first isolation dielectric layer based on the word line mask layer to expose the channel region;

and forming a word line structure on the surface of the channel region, wherein the word line structure extends along the second direction to cover the channel regions of the active columns in the same row.

In one embodiment, the forming a word line structure on the surface of the channel region includes:

forming a grid electrode dielectric layer on the surface of the channel region, wherein the grid electrode dielectric layer wraps the channel region;

and forming a word line conducting layer on the surface of the gate dielectric layer, wherein the word line conducting layer extends along the second direction to cover the channel regions of the active columns in the same row, and the word line conducting layer and the gate dielectric layer jointly form the word line structure.

In one embodiment, the forming a word line conductive layer on the surface of the gate dielectric layer includes:

forming a word line conductive material layer, wherein the word line conductive material layer fills gaps between adjacent active pillars and covers the active pillars and the upper surfaces of the word line mask layers;

and removing the word line conductive material layer on the active column and the word line mask layer, and etching the word line conductive material layer based on the word line mask layer to form the word line conductive layer on the surface of the gate dielectric layer.

In one embodiment, after the word line structure is formed on the surface of the gate dielectric layer, the method for manufacturing a semiconductor structure further includes:

forming a filling dielectric layer; the filling dielectric layers are positioned on the upper surfaces of the reserved first isolation dielectric layers and the reserved second isolation dielectric layers and fill gaps between the adjacent word line structures.

The present application further provides, in accordance with some embodiments, a semiconductor structure comprising:

a substrate; a plurality of active columns arranged in an array are arranged in the substrate; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

the word line structure wraps the channel regions of the active columns in the same row;

and the word line mask layer is positioned on the upper surface of the word line structure and covers the second connecting end of each active pillar.

In one embodiment, the substrate is provided with a first isolation groove and a second isolation groove, and the first isolation groove and the second isolation groove isolate a plurality of active columns which are arranged at intervals; the first isolation groove extends along a first direction, the second isolation groove extends along a second direction, and the first direction is intersected with the second direction; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

the first isolation medium layer is positioned in the first isolation groove;

the second isolation medium layer is positioned in the second isolation groove, and the second isolation medium layer and the first isolation medium layer jointly cover the first connecting end of each active column;

wherein the word line structure extends along the second direction.

In one embodiment, the semiconductor structure further comprises:

and the side wall protective layer is positioned on the side wall of the second isolation groove.

In one embodiment, the semiconductor structure further comprises:

a plurality of bit lines arranged at intervals; the bit lines are positioned below the active pillars and extend along the first direction so as to sequentially connect the first connecting ends of the active pillars positioned in the same column in series;

a metal silicide layer between the bit line and the substrate.

In one embodiment, the word line structure includes:

the grid dielectric layer is positioned on the surface of the channel region and wraps the channel region;

and the word line conducting layer is positioned on the surface of the grid electrode dielectric layer, extends along the second direction and wraps the channel regions of the active columns positioned in the same row.

In one embodiment, the semiconductor structure further comprises:

and the filling dielectric layer is positioned on the upper surface of the first isolation dielectric layer and the upper surface of the second isolation dielectric layer and fills a gap between the adjacent word line structures.

The present application also provides, in accordance with some embodiments, a method of making a memory structure, comprising:

preparing the semiconductor structure by using the method for preparing a semiconductor structure provided by any one of the embodiments;

forming a plurality of storage node structures, wherein the storage node structures are positioned above the second connecting ends of the active pillars and are connected with the second connecting ends in a one-to-one correspondence manner;

and forming a plurality of capacitors, wherein the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

The present application further provides, in accordance with some embodiments, a memory structure comprising:

the semiconductor structure as provided in any of the preceding embodiments;

the storage node structures are positioned above the second connecting ends of the active columns and are connected with the second connecting ends in a one-to-one correspondence mode;

the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

The semiconductor structure, the memory structure and the preparation method thereof have the following beneficial effects:

according to the preparation method of the semiconductor structure, the substrate is etched to form the groove, the filling mask layer is formed in the groove, the substrate is etched back, the side wall mask layers formed on the side wall of the filling mask layer and the side wall of the second connecting end form the word line mask layer, so that the word line structure can be formed on the basis of the word line mask layer in the subsequent process, the self-alignment in the process of forming the word line structure is realized, the preparation flow is simplified, and the preparation cost is reduced.

The semiconductor structure provided by the application has the word line mask layer and can be used as a mask pattern in a self-alignment process when the word line structure is formed, so that the preparation flow is simplified, and the preparation cost is reduced.

The method for manufacturing a memory structure provided by the present application includes the step of manufacturing the semiconductor structure by using the method for manufacturing a semiconductor structure provided by the foregoing embodiment, and therefore, the technical effects that can be achieved by the method for manufacturing a semiconductor structure provided by the foregoing embodiment can be achieved by the method for manufacturing a memory structure, and detailed descriptions are omitted here.

The memory structure provided by the present application includes the semiconductor structure provided by the foregoing embodiment, and therefore, the technical effects that can be achieved by the semiconductor structure provided by the foregoing embodiment can also be achieved by the above memory structure, and detailed descriptions thereof are omitted here.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 2 is a flowchart of step S100 in a method for fabricating a semiconductor structure according to an embodiment of the present application;

fig. 3 is a schematic top view of a semiconductor structure fabricated by a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 4 (a) is a schematic cross-sectional structure of the structure obtained in step S5 in an embodiment of the present application along direction aa 'in fig. 2, (b) in fig. 4 is a schematic cross-sectional structure of the structure obtained in step S5 in an embodiment of the present application along direction bb' in fig. 2, (c) in fig. 4 is a schematic cross-sectional structure of the structure obtained in step S5 in an embodiment of the present application along direction cc 'in fig. 2, and (d) in fig. 4 is a schematic cross-sectional structure of the structure obtained in step S5 in an embodiment of the present application along direction dd' in fig. 2;

fig. 5 (a) is a schematic cross-sectional structure of the structure obtained in step S6 in an embodiment of the present application along direction aa 'in fig. 2, (b) in fig. 5 is a schematic cross-sectional structure of the structure obtained in step S6 in an embodiment of the present application along direction bb' in fig. 2, (c) in fig. 5 is a schematic cross-sectional structure of the structure obtained in step S6 in an embodiment of the present application along direction cc 'in fig. 2, and (d) in fig. 5 is a schematic cross-sectional structure of the structure obtained in step S6 in an embodiment of the present application along direction dd' in fig. 2;

fig. 6 (a) is a schematic cross-sectional structure of the structure obtained in step S7 in an embodiment of the present application along the direction aa 'in fig. 2, fig. 6 (b) is a schematic cross-sectional structure of the structure obtained in step S7 in an embodiment of the present application along the direction bb' in fig. 2, fig. 6 (c) is a schematic cross-sectional structure of the structure obtained in step S7 in an embodiment of the present application along the direction cc 'in fig. 2, and fig. 6 (d) is a schematic cross-sectional structure of the structure obtained in step S7 in an embodiment of the present application along the direction dd' in fig. 2;

fig. 7 (a) is a schematic cross-sectional structure of the structure obtained in step S8 in an embodiment of the present application along the direction aa 'in fig. 2, (b) in fig. 7 is a schematic cross-sectional structure of the structure obtained in step S8 in an embodiment of the present application along the direction bb' in fig. 2, (c) in fig. 7 is a schematic cross-sectional structure of the structure obtained in step S8 in an embodiment of the present application along the direction cc 'in fig. 2, and (d) in fig. 7 is a schematic cross-sectional structure of the structure obtained in step S8 in an embodiment of the present application along the direction dd' in fig. 2;

fig. 8 (a) is a schematic diagram illustrating a cross-sectional structure of the structure obtained in step S9 in an embodiment of the present application along direction aa 'in fig. 2, fig. 8 (b) is a schematic diagram illustrating a cross-sectional structure of the structure obtained in step S9 in an embodiment of the present application along direction bb' in fig. 2, fig. 8 (c) is a schematic diagram illustrating a cross-sectional structure of the structure obtained in step S9 in an embodiment of the present application along direction cc 'in fig. 2, and fig. 8 (d) is a schematic diagram illustrating a cross-sectional structure of the structure obtained in step S9 in an embodiment of the present application along direction dd' in fig. 2;

fig. 9 (a) is a schematic cross-sectional structure of a structure obtained after exposing a channel region in an embodiment of the present application in a direction aa 'in fig. 2, fig. 9 (b) is a schematic cross-sectional structure of a structure obtained after exposing a channel region in an embodiment of the present application in a direction bb' in fig. 2, fig. 9 (c) is a schematic cross-sectional structure of a structure obtained after exposing a channel region in an embodiment of the present application in a direction cc 'in fig. 2, and fig. 9 (d) is a schematic cross-sectional structure of a structure obtained after exposing a channel region in an embodiment of the present application in a direction dd' in fig. 2;

fig. 10 (a) is a schematic cross-sectional structure of a structure obtained after forming a gate dielectric layer in an embodiment of the present application along a direction aa 'in fig. 2, fig. 10 (b) is a schematic cross-sectional structure of a structure obtained after forming a gate dielectric layer in an embodiment of the present application along a direction bb' in fig. 2, fig. 10 (c) is a schematic cross-sectional structure of a structure obtained after forming a gate dielectric layer in an embodiment of the present application along a direction cc 'in fig. 2, and fig. 10 (d) is a schematic cross-sectional structure of a structure obtained after forming a gate dielectric layer in an embodiment of the present application along a direction dd' in fig. 2;

fig. 11 (a) is a schematic cross-sectional structure of a structure obtained after forming a word line conductive material layer according to an embodiment of the present invention, taken along a direction aa 'in fig. 2, (b) in fig. 11 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive material layer according to an embodiment of the present invention, taken along a direction bb' in fig. 2, (c) in fig. 11 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive material layer according to an embodiment of the present invention, taken along a direction cc 'in fig. 2, and (d) in fig. 11 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive material layer according to an embodiment of the present invention, taken along a direction dd' in fig. 2;

fig. 12 (a) is a schematic cross-sectional structure of a structure obtained after forming a word line conductive layer in an embodiment of the present application along a direction aa 'in fig. 2, (b) in fig. 12 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive layer in an embodiment of the present application along a direction bb' in fig. 2, (c) in fig. 12 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive layer in an embodiment of the present application along a direction cc 'in fig. 2, and (d) in fig. 12 is a schematic cross-sectional structure of the structure obtained after forming the word line conductive layer in an embodiment of the present application along a direction dd' in fig. 2;

fig. 13 (a) is a schematic cross-sectional structure view of a structure obtained after forming a filling medium layer in an embodiment of the present application along a direction aa 'in fig. 2, fig. 13 (b) is a schematic cross-sectional structure view of a structure obtained after forming a filling medium layer in an embodiment of the present application along a direction bb' in fig. 2, fig. 13 (c) is a schematic cross-sectional structure view of a structure obtained after forming a filling medium layer in an embodiment of the present application along a direction cc 'in fig. 2, and fig. 13 (d) is a schematic cross-sectional structure view of a structure obtained after forming a filling medium layer in an embodiment of the present application along a direction dd' in fig. 2; fig. 13 (a) is a schematic cross-sectional structure of the semiconductor structure according to an embodiment of the present disclosure along the direction aa 'in fig. 2, fig. 13 (b) is a schematic cross-sectional structure of the semiconductor structure according to an embodiment of the present disclosure along the direction bb' in fig. 2, fig. 13 (c) is a schematic cross-sectional structure of the semiconductor structure according to an embodiment of the present disclosure along the direction cc 'in fig. 2, and fig. 13 (d) is a schematic cross-sectional structure of the semiconductor structure according to an embodiment of the present disclosure along the direction dd' in fig. 2;

fig. 14 is a flowchart of a method for manufacturing a memory structure according to an embodiment of the present disclosure.

Description of reference numerals:

11. a substrate; 13. a first isolation dielectric layer; 15. a sidewall protection layer; 17. a metal silicide layer; 18. a bit line; 19. a second isolation dielectric layer; 20. a trench; 211. filling the mask layer; 212. a side wall mask layer; 21. a word line mask layer; 221. a gate dielectric layer; 222. a word line conductive material layer; 223. a word line conductive layer; 22. a word line structure; 23. filling the dielectric layer; 31. an active column; 312. a second connection end; 313. a channel region.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on" the top surface of … or "connected to" …, it can be directly on or connected to the top surface of the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first or second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first isolation dielectric layer may be referred to as a second isolation dielectric layer, and similarly, the second isolation dielectric layer may be referred to as a first isolation dielectric layer; the first isolation dielectric layer and the second isolation dielectric layer are different isolation dielectric layers.

Spatial relationship terms, such as "under …," may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below …" would then be oriented "above" the other elements or features. Thus, the exemplary term "below …" can include both an upper and lower orientation. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

The present application provides, according to some embodiments, a method of fabricating a semiconductor structure.

Referring to fig. 1, in one embodiment, a method for fabricating a semiconductor structure may include the steps of:

s100: providing a substrate, and forming a plurality of active columns which are arranged at intervals in the substrate; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

s200: etching the substrate to form a trench, wherein the trench defines the position of the word line structure;

s300: forming a filling mask layer in the groove;

s400: etching back the substrate to expose the filling mask layer and the second connecting end of each active column;

s500: and forming a side wall mask layer on the side wall of the filling mask layer and the side wall of the second connecting end, wherein the side wall mask layer and the filling mask layer jointly form a word line mask layer, and the word line mask layer defines the shape and the position of the word line structure.

In the method for manufacturing a semiconductor structure according to the above embodiment, the word line mask layer is formed by forming the trench, forming the filling mask layer in the trench, etching back the substrate, and forming the side wall mask layer on the side wall of the filling mask layer and the side wall of the second connection end, so that the word line structure can be formed based on the word line mask layer in the subsequent process, and self-alignment in the process of forming the word line structure is realized, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Referring to fig. 2, in one embodiment, the step S100 may specifically include the following steps:

s1: a substrate is provided.

S2: a first isolation trench is formed in the substrate.

It should be noted that the first isolation groove may extend in the first direction.

S3: and filling a first isolation medium layer in the first isolation groove.

S4: and etching the substrate and the first isolation medium layer to form a second isolation groove.

It should be noted that the second isolation groove may extend along the second direction, and the second direction intersects with the first direction. The second isolation groove and the first isolation groove can jointly isolate a plurality of active columns; the active pillar may include a first connection end, a second connection end, and a channel region between the first connection end and the second connection end.

S5: and forming a second isolation dielectric layer in the second isolation groove.

On the basis of the above steps, step S200 may specifically include the following steps: and etching the first isolation medium layer to form a groove.

It should be noted that the trench should define the location of the word line structure.

Referring to fig. 3, fig. 3 shows the aa 'direction, bb' direction, cc 'direction and dd' direction in the present application.

Referring to fig. 4, in step S1, a substrate 11 is provided.

In the method for manufacturing a semiconductor structure provided in the present application, the material of the substrate 11 is not particularly limited. By way of example, the substrate 11 may include, but is not limited to, any one or more of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or the like.

Referring to fig. 4, in step S2, a first isolation trench is formed in the substrate 11. It should be noted that the first isolation groove may extend in the first direction.

In the method for manufacturing a semiconductor structure provided in the present application, the manner of forming the first isolation trench in step S2 is not particularly limited. As an example, a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process may be employed to form the first isolation groove in the substrate 11.

With reference to fig. 4, in step S3, the first isolation dielectric layer 13 is filled in the first isolation trench.

The material of the first isolation dielectric layer 13 is not specifically limited in this application. As an example, the first isolation dielectric layer 13 may include, but is not limited to, a first oxide layer.

By way of example, but not limitation, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process may be used to fill the first oxide Layer in the first isolation trench.

With reference to fig. 4, in step S4, the substrate 11 and the first isolation dielectric layer 13 are etched to form a second isolation trench. It should be noted that the second isolation groove may extend along the second direction, and the second direction intersects with the first direction.

As shown in fig. 3, the second isolation trench may isolate the plurality of active pillars 31 in common with the first isolation trench. The active pillars 31 may include a first connection terminal, a second connection terminal, and a channel region between the first connection terminal and the second connection terminal 312.

As an example, the substrate 11 and the first isolation dielectric layer 13 may be etched to form the second isolation trench in the following manner, for example: forming a patterned mask layer on the surfaces of the substrate 11 and the first isolation dielectric layer 13, wherein the patterned mask layer may have an opening therein, and the opening may be used to define the shape and position of the second isolation trench; after forming the patterned mask layer, the substrate 11 and the first isolation dielectric layer 13 may be etched based on the patterned mask layer to form second isolation trenches.

The material of the patterned mask layer is not specifically limited in the present application. As an example, the patterned mask layer may include, but is not limited to, a second oxide layer. It is understood that the material of the second oxide layer and the material of the first oxide layer may be the same oxide or different oxides.

In the method for manufacturing a semiconductor structure according to the above embodiment, the patterned mask layer formed can prevent the second connection end of the active pillar 31 from performing an unnecessary chemical reaction (e.g., silicidation) in the subsequent process, thereby improving the yield of the manufactured structure.

In one embodiment, the method for manufacturing a semiconductor structure may further include the steps of:

performing first ion implantation on the active column 31 to form a drain region at the first connection end, a source region at the second connection end, and a channel region between the first connection end and the second connection end; after the first ion implantation, a second ion implantation is performed on the channel region.

The first ion implantation process is not particularly limited in the present application. As an example, the implanted ions In the first ion implantation process may include any one or more of Boron (Boron, B) ions, gallium (Mg) ions, Indium (Indium, In) ions, or the like; in this case, the implanted ions in the second ion implantation process may include any one or more of Phosphorus (P) ions, Arsenic (As) ions, Antimony (Sb) ions, and the like.

Referring to fig. 4, in an embodiment, before forming the second isolation dielectric layer in the second isolation trench in step S5, the method for manufacturing a semiconductor structure may further include the following steps:

forming a plurality of bit line trenches arranged at intervals in the substrate 11; forming a metal silicide layer 17 in the bit line trench; bit lines 18 are formed on the surface of the metal silicide layer 17.

Note that the bit line trenches should be located below the active pillars 31, and each bit line trench should extend in the first direction. It should be noted that the bit line should be located in the bit line trench and extend along the first direction to serially connect the first connection ends of the active pillars 31 located in the same column.

In the method for manufacturing a semiconductor structure according to the above embodiment, the metal silicide layer is formed in the bit line trench, so that the resistance of the bit line formed in the subsequent manufacturing process can be reduced.

In one embodiment, before the bit line trench is formed, a sidewall protection layer 15 may be further formed on the sidewall of the second isolation trench.

The material of the sidewall protection layer 15 is not particularly limited in this application. As an example, the sidewall protection layer 15 may include, but is not limited to, a third oxide layer.

As an example, the sidewall protection layer 15 may be formed on the sidewall of the second isolation trench using, but not limited to, a thermal oxidation process or an atomic layer deposition process.

In the method for manufacturing the semiconductor structure according to the above embodiment, the sidewall protection layer 15 is formed to prevent the sidewall of the second isolation trench from generating an unnecessary chemical reaction (e.g., silicidation) in the subsequent process, thereby improving the yield of the manufactured structure.

As an example, the sidewall protection layer 15 may be formed in the following manner, for example: depositing a side wall protective material layer in the second isolation groove; after the sidewall protection material layer is formed, the sidewall protection material layer is etched back, and only the sidewall protection material layer on the sidewall surface of the second isolation trench is remained as the sidewall protection layer 15.

The shape of the bit line trench formed in some embodiments is not particularly limited. As an example, the shape of the bit line trench may be bowl-shaped, rectangular, elliptical, or circular in cross section in the aa' direction in fig. 2, or the like.

As an example, when the substrate is a silicon substrate, the following steps may be taken to form the metal silicide layer 17 in the bit line trench, such as: forming a metal layer in the bit line groove; after the metal layer is formed, Rapid Thermal Processing (RTP) is performed on the resulting structure, so that the metal layer reacts with the substrate 11 to form a metal silicide layer 17 in the bit line trench.

The material of the metal layer is not particularly limited in the present application. As an example, the metal layer may include, but is not limited to, a cobalt (Co) layer.

It should be noted that the bit lines 18 should be located in the bit line trenches and extend along the first direction to serially connect the first connection ends of the active pillars 31 located in the same column.

Referring to fig. 4, (a) in fig. 4 shows a schematic cross-sectional structure of the structure obtained in step S5 in the direction aa 'in fig. 2, (b) in fig. 4 shows a schematic cross-sectional structure of the structure obtained in step S5 in the direction bb' in fig. 2, (c) in fig. 4 shows a schematic cross-sectional structure of the structure obtained in step S5 in the direction cc 'in fig. 2, and (d) in fig. 4 shows a schematic cross-sectional structure of the structure obtained in step S5 in the direction dd' in fig. 2.

S5: and forming a second isolation dielectric layer 19 in the second isolation trench.

The material of the second isolation dielectric layer 19 is not particularly limited in this application. As an example, the second isolation dielectric layer 19 may include, but is not limited to, a fourth oxide layer. It is understood that the material of the fourth oxide layer and the material of the first oxide layer may be the same oxide or different oxides.

Referring to fig. 5, (a) in fig. 5 shows a schematic cross-sectional structure of the structure obtained in step S6 in the direction aa 'in fig. 2, (b) in fig. 5 shows a schematic cross-sectional structure of the structure obtained in step S6 in the direction bb' in fig. 2, (c) in fig. 5 shows a schematic cross-sectional structure of the structure obtained in step S6 in the direction cc 'in fig. 2, and (d) in fig. 5 shows a schematic cross-sectional structure of the structure obtained in step S6 in the direction dd' in fig. 2.

S6: the first isolation dielectric layer 13 is etched to form a trench 20.

It should be noted that the trench 20 should define the position of the word line structure.

Referring to fig. 6, (a) in fig. 6 shows a schematic cross-sectional structure of the structure obtained in step S7 in the direction aa 'in fig. 2, (b) in fig. 6 shows a schematic cross-sectional structure of the structure obtained in step S7 in the direction bb' in fig. 2, (c) in fig. 6 shows a schematic cross-sectional structure of the structure obtained in step S7 in the direction cc 'in fig. 2, and (d) in fig. 6 shows a schematic cross-sectional structure of the structure obtained in step S7 in the direction dd' in fig. 2.

In step S7, a filling mask layer 211 is formed in the trench 20.

Referring to fig. 7, (a) in fig. 7 shows a schematic cross-sectional structure of the structure obtained in step S8 in the direction aa 'in fig. 2, (b) in fig. 7 shows a schematic cross-sectional structure of the structure obtained in step S8 in the direction bb' in fig. 2, (c) in fig. 7 shows a schematic cross-sectional structure of the structure obtained in step S8 in the direction cc 'in fig. 2, and (d) in fig. 7 shows a schematic cross-sectional structure of the structure obtained in step S8 in the direction dd' in fig. 2.

In step S8, the first isolation dielectric layer 13 and the second isolation dielectric layer 19 are etched back to expose the filling mask layer 211 and the second connecting ends 312 of the active pillars 31.

Referring to fig. 8, (a) in fig. 8 shows a schematic cross-sectional structure of the structure obtained in step S9 in the direction aa 'in fig. 2, (b) in fig. 8 shows a schematic cross-sectional structure of the structure obtained in step S9 in the direction bb' in fig. 2, (c) in fig. 8 shows a schematic cross-sectional structure of the structure obtained in step S9 in the direction cc 'in fig. 2, and (d) in fig. 8 shows a schematic cross-sectional structure of the structure obtained in step S9 in the direction dd' in fig. 2.

In step S9, a sidewall mask layer 212 is formed on the sidewalls of the filling mask layer 211 and the sidewalls of the second connection ends 312; the sidewall mask layer 212 and the fill mask layer 211 may together form a word line mask layer 21; the wordline mask layer 21 may define the shape and location of the wordline structure.

In one embodiment, after the sidewall mask layer 212 is formed on the sidewalls of the filling mask layer 211 and the sidewalls of the second connection ends 312, the method for manufacturing the semiconductor structure may further include the following steps:

continuing to etch back the second isolation dielectric layer 19 and the first isolation dielectric layer 13 based on the word line mask layer 21 to expose the channel region 313; after the channel region 313 is exposed, a word line structure is formed on the surface of the channel region 313.

It should be noted that the word line structure should extend along the second direction to cover the channel region 313 of the active pillars 31 in the same row.

As shown in fig. 9, (a) in fig. 9 shows a schematic cross-sectional structure view along aa 'in fig. 2 after the channel region 313 is exposed, (b) in fig. 9 shows a schematic cross-sectional structure view along bb' in fig. 2 after the channel region 313 is exposed, (c) in fig. 9 shows a schematic cross-sectional structure view along cc 'in fig. 2 after the channel region 313 is exposed, and (d) in fig. 9 shows a schematic cross-sectional structure view along dd' in fig. 2 after the channel region 313 is exposed.

As an example, the following steps may be taken to form the word line structure 22 on the surface of the channel region 313, such as:

a gate dielectric layer 221 is formed on the surface of the channel region 313, and the channel region 313 is covered by the gate dielectric layer 221.

As shown in fig. 10, (a) in fig. 10 shows a schematic cross-sectional structure of the resulting structure after forming the gate dielectric layer 221 in the aa 'direction in fig. 2, (b) in fig. 10 shows a schematic cross-sectional structure of the resulting structure after forming the gate dielectric layer 221 in the bb' direction in fig. 2, (c) in fig. 10 shows a schematic cross-sectional structure of the resulting structure after forming the gate dielectric layer 221 in the cc 'direction in fig. 2, and (d) in fig. 10 shows a schematic cross-sectional structure of the resulting structure after forming the gate dielectric layer 221 in the dd' direction in fig. 2.

After forming the gate dielectric layer 221, a word line conductive layer 223 is formed on the surface of the gate dielectric layer 221.

It should be noted that the word line conductive layer 223 should extend along the second direction to cover the channel regions 313 of the active pillars 31 located in the same row.

The word line conductive layer 223 and the gate dielectric layer 221 may collectively constitute the word line structure 22.

As an example, the word line conductive layer 223 may be formed on the surface of the gate dielectric layer 221 in the following manner, for example:

forming a word line conductive material layer 222, wherein the word line conductive material layer 222 fills the gap between the adjacent active pillars 31 and covers the active pillars 31 and the upper surfaces of the word line mask layers 21; after the word line conductive material layer 222 is formed, the word line conductive material layer 222 on the active pillars 31 and the word line mask layer 21 is removed, and the word line conductive material layer 222 is etched based on the word line mask layer 21 to form a word line conductive layer 223 on the surface of the gate dielectric layer 221.

As shown in fig. 11, (a) in fig. 11 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive material layer 222 in the aa 'direction in fig. 2, (b) in fig. 11 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive material layer 222 in the bb' direction in fig. 2, (c) in fig. 11 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive material layer 222 in the cc 'direction in fig. 2, and (d) in fig. 11 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive material layer 222 in the dd' direction in fig. 2.

As shown in fig. 12, (a) in fig. 12 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive layer 223 in the aa 'direction in fig. 2, (b) in fig. 12 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive layer 223 in the bb' direction in fig. 2, (c) in fig. 12 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive layer 223 in the cc 'direction in fig. 2, and (d) in fig. 12 shows a schematic cross-sectional structure of the resulting structure after forming the word line conductive layer 223 in the dd' direction in fig. 2.

In one embodiment, after forming the word line structure 22 on the surface of the gate dielectric layer 221, the method for manufacturing a semiconductor structure may further include a step of forming a filling dielectric layer.

As shown in fig. 13, (a) in fig. 13 shows a schematic cross-sectional structure of the resulting structure after forming the filling dielectric layer 23 in the aa 'direction in fig. 2, (b) in fig. 13 shows a schematic cross-sectional structure of the resulting structure after forming the filling dielectric layer 23 in the bb' direction in fig. 2, (c) in fig. 13 shows a schematic cross-sectional structure of the resulting structure after forming the filling dielectric layer 23 in the cc 'direction in fig. 2, and (d) in fig. 13 shows a schematic cross-sectional structure of the resulting structure after forming the filling dielectric layer 23 in the dd' direction in fig. 2.

Specifically, the filling dielectric layer 23 is located on the upper surface of the remaining first isolation dielectric layer 13 and the upper surface of the remaining second isolation dielectric layer 19, and fills the gap between the adjacent word line structures 22.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

The present application further provides a semiconductor structure, according to some embodiments.

Referring to fig. 13, a diagram (a) in fig. 13 also shows a schematic cross-sectional structure of the semiconductor structure provided in an embodiment of the present application along a direction aa 'in fig. 2, a diagram (b) in fig. 13 also shows a schematic cross-sectional structure of the semiconductor structure provided in an embodiment of the present application along a direction bb' in fig. 2, a diagram (c) in fig. 13 also shows a schematic cross-sectional structure of the semiconductor structure provided in an embodiment of the present application along a direction cc 'in fig. 2, and a diagram (d) in fig. 13 also shows a schematic cross-sectional structure of the semiconductor structure provided in an embodiment of the present application along a direction dd' in fig. 2.

In one embodiment, the semiconductor structure may include a substrate 11, a wordline structure 22, and a wordline mask layer 21.

The substrate 11 has a plurality of active pillars 31 arranged in an array; the active pillar 31 includes a first connection end, a second connection end 312, and a channel region 313 between the first connection end and the second connection end 312. The word line structure 22 wraps the channel regions 313 of the active pillars 31 in the same row. The word line mask layer 21 is located on the upper surface of the word line structure 22 and covers the second connection ends 312 of the active pillars 31.

The semiconductor structure provided by the above embodiment has the word line mask layer 21, and the word line mask layer 21 can be used as a mask pattern in a self-alignment process when the word line structure 22 is formed, so that the preparation process is simplified, and the preparation cost is reduced.

In one embodiment, the substrate 11 may have a first isolation trench and a second isolation trench therein; the first isolation groove can isolate a plurality of active pillars 31 arranged at intervals from the second isolation groove. Specifically, the first isolation groove extends along the first direction, the second isolation groove extends along the second direction, and the active pillar 31 may include a first connection end, a second connection end 312, and a channel region 313 between the first connection end and the second connection end 312.

The first isolation medium layer 13 is positioned in the first isolation groove; the second isolation dielectric layer 19 is located in the second isolation trench. The second isolation dielectric layer 19 may cover the first connection terminal of each active pillar 31 together with the first isolation dielectric layer 13.

The word line structure 22 extends along the second direction to cover the channel regions 313 of the active pillars 31 in the same row.

The word line mask layer 21 is located on the upper surface of the word line structure 22 and covers the second connection ends 312 of the active pillars 31.

With continued reference to fig. 13, in one embodiment, the semiconductor structure may further include a sidewall protection layer 15.

Specifically, the sidewall protection layer 15 is located on the sidewall of the second isolation trench (not labeled in fig. 13).

With continued reference to fig. 13, in one embodiment, the semiconductor structure may further include a plurality of bit lines 18 and metal silicide layers 17 arranged at intervals.

Specifically, the bit line 18 is located below the active pillar 31; the bit lines 18 extend in the first direction to sequentially connect the first connection terminals of the active pillars 31 located in the same column in series. A metal silicide layer 17 is located between the bit line 18 and the substrate 11.

In the semiconductor structure provided by the above embodiment, the metal silicide layer 17 is provided between the bit line 18 and the substrate 11, and the metal silicide layer 17 can reduce the resistance of the bit line 18.

With continued reference to fig. 13, in one embodiment, the word line structure 22 may include a gate dielectric layer 221 and a word line conductive layer 223.

Specifically, the gate dielectric layer 221 may be located on the surface of the channel region 313 and cover the channel region 313. The word line conductive layer 223 may be on the surface of the gate dielectric layer 221 and cover the channel region 313 of the active pillars 31 in the same row.

Note that the word line conductive layer 223 should extend in the second direction.

With continued reference to fig. 13, in one embodiment, the semiconductor structure may further include a fill dielectric layer 23.

The filling dielectric layer 23 is located on the upper surface of the first isolation dielectric layer 13 and the upper surface of the second isolation dielectric layer 19, and fills the gap between the adjacent word line structures 22.

The present application also provides, in accordance with some embodiments, a method of making a memory structure.

Referring to fig. 14, in one embodiment, a method for manufacturing a memory structure may include the steps of:

s10: the semiconductor structure is prepared by the method for preparing a semiconductor structure provided by any one of the embodiments.

S20: a plurality of storage node structures are formed.

It should be noted that the storage node structure formed in step S20 should be located above the second connection end 312 of the active pillar 31, and connected to the second connection end 312 in a one-to-one correspondence.

S30: a plurality of capacitors are formed.

It should be noted that the capacitors formed in step S30 should be located on the upper surface of the storage node structure and be arranged in one-to-one correspondence with the storage node structure.

The method for manufacturing a memory structure according to the foregoing embodiment includes the step of manufacturing the semiconductor structure by using the method for manufacturing a semiconductor structure according to the foregoing embodiment, so that the technical effects that can be achieved by the method for manufacturing a semiconductor structure according to the foregoing embodiment can be achieved by the method for manufacturing a memory structure, and detailed descriptions thereof are omitted here.

The present application further provides, according to some embodiments, a memory structure.

In one embodiment, the storage structure may include a semiconductor structure, a plurality of storage node structures, and a plurality of capacitors as provided in any of the previous embodiments.

Specifically, the storage node structures may be located above the second connection ends 312 of the active pillars 31, and connected to the second connection ends 312 in a one-to-one correspondence. The capacitors may be located on an upper surface of the storage node structure and arranged in one-to-one correspondence with the storage node structure.

The memory structure provided by the foregoing embodiment includes the semiconductor structure provided by the foregoing embodiment, and therefore, the technical effects that can be achieved by the semiconductor structure provided by the foregoing embodiment can also be achieved by the above memory structure, and detailed descriptions thereof are omitted here.

All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims (16)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, and forming a plurality of active columns which are arranged at intervals in the substrate; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

etching the substrate to form a groove, wherein the groove defines the position of the word line structure;

forming a filling mask layer in the groove;

etching back the substrate to expose the filling mask layer and the second connecting end of each active column;

and forming a side wall mask layer on the side wall of the filling mask layer and the side wall of the second connecting end, wherein the side wall mask layer and the filling mask layer jointly form a word line mask layer, and the word line mask layer defines the shape and the position of a word line structure.

2. The method of claim 1, wherein providing a substrate and forming a plurality of active pillars in the substrate in an array comprises:

providing a substrate;

forming a first isolation groove in the substrate; the first isolation groove extends along a first direction;

filling a first isolation medium layer in the first isolation groove;

etching the substrate and the first isolation medium layer to form a second isolation groove; the second isolation groove extends along a second direction, and the first direction intersects with the second direction; the second isolation groove and the first isolation groove jointly isolate a plurality of active columns; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

forming a second isolation medium layer in the second isolation groove;

the etching the substrate to form a trench includes:

and etching the first isolation medium layer to form a groove, wherein the groove defines the position of the word line structure.

3. The method of claim 2, wherein before forming the second isolation dielectric layer in the second isolation trench, the method further comprises:

forming a plurality of bit line grooves arranged at intervals in the substrate, wherein the bit line grooves are positioned below the active pillars and extend along the first direction;

forming a metal silicide layer in the bit line groove;

forming a bit line on the surface of the metal silicide layer; the bit lines are positioned in the bit line grooves and extend along the first direction so as to sequentially connect the first connecting ends of the active columns positioned in the same column in series.

4. The method of claim 3, wherein prior to forming the bitline trench, the method further comprises:

and forming a side wall protection layer on the side wall of the second isolation groove.

5. The method of claim 3, wherein the substrate comprises a silicon substrate; forming a metal silicide layer in the bit line trench includes:

forming a metal layer in the bit line groove;

and carrying out rapid thermal treatment on the obtained structure, so that the metal layer reacts with the substrate to form a metal silicide layer in the bit line groove.

6. The method of claim 2, wherein after forming a sidewall mask layer on sidewalls of the mask layer and sidewalls of the second connection terminal, the method further comprises:

continuously etching back the second isolation dielectric layer and the first isolation dielectric layer based on the word line mask layer to expose the channel region;

and forming a word line structure on the surface of the channel region, wherein the word line structure extends along the second direction to cover the channel regions of the active columns in the same row.

7. The method of claim 6, wherein forming a word line structure on a surface of the channel region comprises:

forming a grid electrode dielectric layer on the surface of the channel region, wherein the grid electrode dielectric layer wraps the channel region;

and forming a word line conducting layer on the surface of the gate dielectric layer, wherein the word line conducting layer extends along the second direction to cover the channel regions of the active columns in the same row, and the word line conducting layer and the gate dielectric layer jointly form the word line structure.

8. The method of claim 7, wherein forming a word line conductive layer on a surface of the gate dielectric layer comprises:

forming a word line conductive material layer, wherein the word line conductive material layer fills gaps between adjacent active pillars and covers the active pillars and the upper surfaces of the word line mask layers;

and removing the word line conductive material layer on the active column and the word line mask layer, and etching the word line conductive material layer based on the word line mask layer to form the word line conductive layer on the surface of the gate dielectric layer.

9. The method of claim 7, wherein after the word line structure is formed on the surface of the gate dielectric layer, the method further comprises:

forming a filling dielectric layer; the filling dielectric layers are positioned on the upper surfaces of the reserved first isolation dielectric layers and the reserved second isolation dielectric layers and fill gaps between the adjacent word line structures.

10. A semiconductor structure, comprising:

a substrate; a plurality of active columns arranged in an array are arranged in the substrate; the active column comprises a first connecting end, a second connecting end and a channel region positioned between the first connecting end and the second connecting end;

a word line structure wrapping the channel regions of the active pillars located in a same row;

and the word line mask layer is positioned on the upper surface of the word line structure and covers the second connecting end of each active column.

11. The semiconductor structure of claim 10, wherein the substrate has a first isolation trench and a second isolation trench, the first isolation trench and the second isolation trench isolating the plurality of active pillars arranged at intervals; the first isolation groove extends along a first direction, the second isolation groove extends along a second direction, and the first direction is intersected with the second direction;

the first isolation medium layer is positioned in the first isolation groove;

the second isolation medium layer is positioned in the second isolation groove, and the second isolation medium layer and the first isolation medium layer jointly cover the first connecting end of each active column;

wherein the word line structure extends along the second direction.

12. The semiconductor structure of claim 11, further comprising:

a plurality of bit lines arranged at intervals; the bit lines are positioned below the active pillars and extend along the first direction so as to sequentially connect the first connecting ends of the active pillars positioned in the same column in series;

a metal silicide layer between the bit line and the substrate.

13. The semiconductor structure of claim 11, wherein the word line structure comprises:

the grid dielectric layer is positioned on the surface of the channel region and wraps the channel region;

and the word line conducting layer is positioned on the surface of the grid electrode dielectric layer, extends along the second direction and wraps the channel region of the active column positioned in the same row.

14. The semiconductor structure of claim 11, further comprising:

and the filling dielectric layer is positioned on the upper surface of the first isolation dielectric layer and the upper surface of the second isolation dielectric layer and fills a gap between the adjacent word line structures.

15. A method of making a memory structure, comprising:

preparing the semiconductor structure using the method for preparing a semiconductor structure according to any one of claims 1 to 9;

forming a plurality of storage node structures, wherein the storage node structures are positioned above the second connecting ends of the active pillars and are connected with the second connecting ends in a one-to-one correspondence manner;

and forming a plurality of capacitors, wherein the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

16. A memory structure, comprising:

a semiconductor structure as in any one of claims 10-14;

the storage node structures are positioned above the second connecting ends of the active columns and are connected with the second connecting ends in a one-to-one correspondence mode;

the capacitors are located on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

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