CN115132138A - Light emitting control unit, control method thereof, gate drive circuit and display device - Google Patents

Abstract

The application discloses a light-emitting control unit and a control method thereof, a grid drive circuit and a display device, and the light-emitting control unit of the embodiment of the application comprises: the setting sub-circuit comprises a first transistor and a second transistor, wherein the first end of the first transistor is connected to a first power supply signal end, the second end of the first transistor is connected to a first node, the control end of the first transistor is connected to a clock signal end independent of the shift register unit, the first end of the second transistor is connected to the second node, the second end of the second transistor is connected to a second power supply signal end, and the control end of the second transistor is connected to the clock signal end; a reset sub-circuit resetting the first node by the second power supply signal and pulling up a potential of the second node by the first power supply signal in response to control of the reset signal; and an output sub-circuit which controls to output the first power supply signal or the second power supply signal based on potentials of the first node and the second node. The embodiment of the application provides the light-emitting control unit with a simple structure through the position sub-circuit, the reset sub-circuit and the output sub-circuit.

Description

Light emitting control unit, control method thereof, gate drive circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a light emitting control unit, a control method thereof, a gate driving circuit, and a display device.

Background

The current mature technologies in the display field include LCD display technology and active matrix OLED display technology. The display device formed by the OLED display technology has a fast response speed, and simultaneously can achieve the maximum contrast ratio, so that the OLED display device is expected to become a mainstream product for next generation display.

Generally, an OLED display device includes: the display device comprises a display panel and a gate drive circuit (GOA circuit) directly formed on the display panel, wherein the gate drive circuit comprises a shift register unit forming a pixel scanning signal and a light-emitting control circuit forming a light-emitting control signal EM of a pixel, and the light-emitting control signal is used for controlling a light-emitting control tube in the pixel drive circuit.

The light-emitting control tube is used for controlling the light-emitting time of the pixel, and is a pulse signal in one frame of image, and is generally a PWM module or a cascade unit in the related art, which is not favorable for the narrow frame design.

Disclosure of Invention

In order to solve at least one of the above problems, a first aspect of the present application provides a light emission control unit, comprising:

a set sub-circuit including a first transistor and a second transistor, a first terminal of the first transistor being electrically connected to a first power signal terminal, a second terminal being electrically connected to a first node, a control terminal being electrically connected to a clock signal terminal independent of the shift register unit, a first terminal of the second transistor being electrically connected to the second node, a second terminal being electrically connected to a second power signal terminal, the control terminal being electrically connected to the clock signal terminal, and configured to set the first node by a first power signal of the first power signal terminal and pull down a potential of the second node by a second power signal of the second power signal terminal in response to control of a clock signal of the clock signal terminal;

a reset sub-circuit which resets the first node by the second power supply signal and pulls up the potential of the second node by the first power supply signal in response to the control of a reset signal of the reset signal terminal; and

and an output sub-circuit that controls to output the first power supply signal or the second power supply signal based on a potential of the first node and a potential of the second node.

In some alternative embodiments, the reset sub-circuit includes: a third transistor and a fourth transistor, wherein,

the first end of the third transistor is electrically connected to the first power signal end, the second end of the third transistor is electrically connected to the second node, the control end is electrically connected to the reset signal end, the first end of the fourth transistor is electrically connected to the first node, the second end of the fourth transistor is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

In some alternative embodiments, the output sub-circuit comprises a fifth transistor and a sixth transistor,

the first end of the fifth transistor is electrically connected to the first power signal end, the second end of the fifth transistor is electrically connected to the output end, the control end is electrically connected to the first node, the first end of the sixth transistor is electrically connected to the output end, the second end of the sixth transistor is electrically connected to the second power signal end, and the control end is electrically connected to the second node.

In some alternative embodiments, the storage sub-circuit further comprises a first storage capacitor and a second storage capacitor,

the first end of the first storage capacitor is electrically connected to the first node, the second end of the first storage capacitor is electrically connected to the output end, the first end of the second storage capacitor is electrically connected to the second node, and the second end of the second storage capacitor is electrically connected to the second power signal end.

In some optional embodiments, the first power signal of the first power signal terminal is a high level signal, and the second power signal of the second power signal terminal is a low level signal.

In some alternative embodiments, the transistors in the light emission control unit are N-type transistors or P-type transistors.

A second aspect of the present application provides a gate driving circuit, including: a plurality of cascaded shift register cells and a plurality of emission control cells according to the above, the emission control cells corresponding one-to-one to the shift register cells,

the output end of each shift register unit is electrically connected with the reset signal end of the corresponding light-emitting control unit; and

wherein each shift register unit comprises a first clock signal end electrically connected to the first clock signal line, the shift register unit generates a gate scanning signal under the control of a clock signal accessed by the first clock signal end,

the clock signal end of each light-emitting control unit is electrically connected to a second clock signal line, and the first clock signal line and the second clock signal line are mutually independent clock signal lines.

A third aspect of the present application provides a display device comprising the gate driver circuit described above.

A fourth aspect of the present application provides a light emission control method for the light emission control unit described above, including:

a first stage in which the set sub-circuit transmits a first power supply signal to a first node in response to the received set signal to cause an output terminal of the output sub-circuit to output the first power supply signal,

in the second stage, the reset signal responds to the received reset signal to transmit the first power supply signal to the second node so as to reset the first node through the second power supply signal and enable the output end of the output sub-circuit to output the second power supply signal; and

and in the third stage, the setting signal is applied to the setting sub-circuit again so that the output end of the output sub-circuit outputs the first power supply signal.

In some of the alternative embodiments, the first and second,

the light emission control unit further comprises a storage sub-circuit comprising a first storage capacitor and a second storage capacitor, wherein a first end of the first storage capacitor is electrically connected to the first node, a second end of the first storage capacitor is electrically connected to the output terminal, a first end of the second storage capacitor is electrically connected to the second node, a second end of the second storage capacitor is electrically connected to the second power signal terminal,

the method further comprises the following steps:

in the second phase, potentials of the first node and the second node are held by the first storage capacitor and the second storage capacitor.

The beneficial effect of this application is as follows:

aiming at the existing problems at present, the light-emitting control unit and the control method thereof, the grid drive circuit and the display device are formulated, the light-emitting control unit with the setting sub-circuit, the resetting sub-circuit and the output sub-circuit is provided, the setting sub-circuit is set to comprise the first transistor and the second transistor, the setting sub-circuit is configured to respond to the control of the clock signal end, the first node is set through the first power signal of the first power signal end, and the potential of the second node is pulled down through the second power signal of the second power signal end, so that a stable light-emitting control signal can be provided by a simple circuit structure, and the structure does not need to be cascaded and is beneficial to narrow-frame design; in addition, the control ends of the first transistor and the second transistor are electrically connected to the clock signal end independent of the shift register unit, so that the light-emitting time of the pixel can be flexibly controlled through the independent clock signal, and the pixel driving circuit has a wide application prospect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic block diagram of a main sub-circuit included in a light emission control unit according to an embodiment of the present application;

fig. 2 shows a schematic circuit diagram of a lighting control unit of an embodiment of the present application;

fig. 3 shows a schematic timing diagram of a light emission control unit according to an embodiment of the present application;

fig. 4 shows a cascade diagram of a shift register unit and a light emission control unit according to an embodiment of the present application;

FIG. 5 shows a schematic diagram of a shift register cell in the cascade diagram of FIG. 4;

fig. 6 shows a schematic diagram of a shift register unit in a display device according to an embodiment of the present application.

Detailed Description

In order to more clearly illustrate the present application, the present application is further described below in conjunction with the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not intended to limit the scope of the present application.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the terms "a," "an," and the like, do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiment of the present application, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first terminal, the other pole is referred to as a second terminal, and the gate is referred to as a control terminal. In addition, the transistors may be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistor is used for explanation, when the N-type transistor is used, the first end is the drain of the N-type transistor, the second end is the source of the N-type transistor, when the gate inputs a high level, the source and the drain are turned on, and when the gate inputs a low level, the source and the drain are turned on. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and is therefore within the scope of the embodiments of the present application.

In view of the above problem, referring to fig. 1, an embodiment of the present application provides a light emission control unit, including:

a set sub-circuit 110 including a first transistor T1 and a second transistor T2, the first terminal of the first transistor T1 being electrically connected to a first power supply signal terminal VGH, the second terminal being electrically connected to a first node Q, the control terminal being electrically connected to a clock signal terminal CLK independent of the shift register unit, the first terminal of the second transistor T2 being electrically connected to a second node QB, the second terminal being electrically connected to a second power supply signal terminal VGL, the control terminal being electrically connected to the clock signal terminal CLK, configured to set the first node Q by the first power supply signal of the first power supply signal terminal VGH and pull down the potential of the second node QB by the second power supply signal of the second power supply signal terminal VGL in response to control of the clock signal terminal CLK;

a reset sub-circuit 120 that resets the first node Q by the second power signal and pulls up the potential of the second node QB by the first power signal in response to the control of the reset signal terminal in (n); and

the output sub circuit 130 controls to output the first power supply signal or the second power supply signal based on the potential of the first node Q and the potential of the second node QB.

In this embodiment, a light emission control unit having a set sub-circuit, a reset sub-circuit, and an output sub-circuit is provided, and the set sub-circuit is configured to include a first transistor and a second transistor, and is configured to set a first node by a first power signal of a first power signal terminal and pull down a potential of a second node by a second power signal of a second power signal terminal in response to control of a clock signal terminal, so that a stable light emission control signal can be provided with a simple circuit structure, and the structure does not need to be cascaded, which is beneficial to narrow-frame design; in addition, by electrically connecting the control terminals of the first transistor and the second transistor to a clock signal terminal independent of the shift register unit, the light emitting time of the pixel can be flexibly controlled by the independent clock signal.

In a specific embodiment, with reference to fig. 1 and fig. 2, fig. 1 shows a schematic structural block diagram of a main sub-circuit included in a shift register unit according to an embodiment of the present application, and fig. 2 shows a circuit diagram of a more specific circuit satisfying the structural block diagram shown in fig. 1. In the figure, N represents the nth light-emitting control unit, N is a positive integer greater than or equal to 1 and less than or equal to N, and N represents the total number of the light-emitting control units in the display device.

Referring to fig. 1 and 2, the light emission control unit includes: a set sub-circuit 110, a reset sub-circuit 120, and an output sub-circuit 130.

In particular, the set sub-circuit 110 includes a first transistor T1 and a second transistor T2. A first terminal of the first transistor T1 is electrically connected to the first power signal terminal VGH, a second terminal is electrically connected to the first node Q, and a control terminal is electrically connected to the clock signal terminal CLK; the second transistor T2 has a first terminal connected to the second node QB, a second terminal electrically connected to the second power signal terminal VGL, and a control terminal electrically connected to the clock signal terminal CLK. The clock signal terminal CLK is required to be a clock signal terminal independent of the shift register unit. The set sub-circuit 110 is configured to set the first node Q by the first power signal of the first power signal terminal VGH and pull down the potential of the second node QB by the second power signal of the second power signal terminal VGL in response to the control of the clock signal terminal CLK.

Specifically, in the present application, the first power signal of the first power signal terminal VGH is at a high level, and the second power signal of the second power signal terminal VGL is at a low level. When the clock signal of the clock signal terminal CLK is at a high level, the first transistor T1 and the second transistor T2 are turned on, and the first transistor T1 transmits the first power signal of the high level of the first power signal terminal VGH to the first node Q, setting it; the second transistor T2 transmits the low-level second power signal of the second power signal terminal VGL to the second node QB, pulling down the potential of the second node QB.

As further shown in fig. 1, the reset sub-circuit 120 is electrically connected to the first node Q, the second node QB, the first power signal terminal VGH, the second power signal terminal VGL, and the reset signal terminal in (n), and is configured to reset the first node Q by the second power signal and pull up the potential of the second node QB by the first power signal in response to the control of the reset signal terminal in (n).

Specifically, referring to fig. 2, the reset sub-circuit 120 includes a third transistor T3 and a fourth transistor T4. A first terminal of the third transistor T3 is electrically connected to the first power signal terminal VGH, a second terminal is electrically connected to the second node QB, a control terminal is electrically connected to the reset signal terminal in (n), a first terminal of the fourth transistor T4 is electrically connected to the first node Q, a second terminal is electrically connected to the second power signal terminal VGL, and a control terminal is electrically connected to the second node QB.

When the reset signal of the reset signal terminal in (n) is at a high level, the third transistor T3 is turned on, and the third transistor T3 transmits the high-level first power signal of the first power signal terminal VGH to the second node QB, pulling up the potential of the second node QB by the first power signal; at this time, since the potential of the second node QB is high, the fourth transistor T4 is also turned on, and the first node Q is reset by the second power signal of low level.

As shown in fig. 1, the output sub-circuit 130 is electrically connected to the first node Q, the second node QB, the first power signal terminal VGH, and the second power signal terminal VGL, and is configured to control to output the first power signal or the second power signal based on the potential of the first node Q and the potential of the second node QB.

Specifically, referring to fig. 2, the output sub-circuit 130 includes a fifth transistor T5 and a sixth transistor T6. A first terminal of the fifth transistor T5 is electrically connected to the first power signal terminal VGH, a second terminal of the fifth transistor T5 is electrically connected to the output terminal em (n), a control terminal of the fifth transistor T5 is electrically connected to the first node Q, a first terminal of the sixth transistor T6 is electrically connected to the output terminal em (n), a second terminal of the sixth transistor T6 is electrically connected to the second power signal terminal VGL, and a control terminal of the sixth transistor T5 is electrically connected to the second node QB.

When the voltage level of the first node Q is high and the voltage level of the second node QB is low, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, the output end em (n) outputs the first power signal, and the output signal is at a high level; when the voltage level of the first node Q is low and the voltage level of the second node QB is high, the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, the output terminal em (n) outputs the second power signal, and the output signal is at a low level.

In this example, referring to fig. 2, the light emission control unit further includes a storage unit including a first storage capacitor C1 and a second storage capacitor C2. A first terminal of the first storage capacitor C1 is electrically connected to the first node Q, a second terminal thereof is electrically connected to the output terminal, a first terminal of the second storage capacitor C2 is electrically connected to the second node QB, and a second terminal thereof is electrically connected to the second power signal terminal VGL. The first storage capacitor C1 and the second storage capacitor C2 are used to hold the potentials of the first node Q and the second node QB, so that the output end em (n) always maintains a stable output when no potential change occurs in the first node Q and the second node QB.

To further understand the structure and function of the embodiments of the present application, the timing function of the light emission control unit is described in detail below with reference to the schematic circuit diagram of fig. 2 and the specific timing diagram shown in fig. 3. It should be noted that, since the light-emission control unit of the present application is only an independent unit circuit, there is no cascade connection, IN order to emphasize the role of the light-emission control unit IN a specific application, the clock signal timings of the clock signal terminals CLK (n) and CLK (n +1), the reset signal timings of the reset signal terminals IN (n) and IN (n +1), and the output signal timings of the corresponding output terminals EM (n) and EM (n +1) are respectively given for the nth light-emission control unit and the (n +1) th light-emission control unit. CKL1, CLK2, CLK3, and CLK4 represent timing signals of clock signal lines corresponding to a plurality of clock signal terminals in the case of a plurality of light emission control units, respectively. In the present example, it is assumed that the light emission control terminal of the nth light emission control unit corresponds to the timing signal of CLK 1.

Specifically, in the first period T1, the clock signal of the clock signal terminal CLK (n) is at a high level, the first transistor T1 is turned on, the potential of the first node Q is set to be high, and at the same time, since the control terminal of the second transistor T2 is also electrically connected to the clock signal terminal CLK, the second transistor T2 is also turned on, the first power signal at a low level is transmitted to the second node QB, and the potential of the node is pulled down; meanwhile, the potential of the reset signal terminal IN (n) is low, and the first node Q and the second node QB are not influenced; at this time, since the first node Q is at a high level and the second node QB is at a low level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the output terminal em (n) outputs a high-level output signal.

In the second stage T2, when the clock signal of the clock signal terminal clk (n) is changed to a low level and the first transistor T1 and the second transistor T2 are turned off, at this time, the potential of the reset signal terminal in (n) is high, the third transistor T3 is turned on, and the first power signal of the high level is transmitted to the second node QB, and since the potential of the second node QB is high, the fourth transistor T4 is turned on, and the second power signal of the low level is transmitted to the first node Q through the fourth transistor T4; accordingly, the first node Q is at a low level, the second node QB is at a high level, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the output terminal em (n) outputs an output signal at a low level.

Furthermore, in the period T2', the clock signal at the clock signal terminal clk (n) and the reset signal at the reset signal terminal in (n) are at the low level at the same time, the fifth transistor T5 and the sixth transistor T6 are both turned off, and in the case where there is no other circuit structure, the output terminal em (n) is floated, and there may be a case where it is not possible to ensure that the output terminal em (n) stably outputs the correct level.

In the present application, since the memory cell is provided, specifically, the first storage capacitor C1 is connected across between the control terminal and the second terminal of the fifth transistor T5, and the second storage capacitor C2 is connected across between the control terminal and the second terminal of the sixth transistor T6, so that the second storage capacitor C1 and the second storage capacitor C2 simultaneously perform the potential holding function in the period T2', the output terminal em (n) holds the potential output of the second stage T2, that is, outputs a low level signal, which may be referred to as a potential holding stage.

Next, in the third stage T3, the clock signal of the clock signal terminal clk (n) changes to high level again, the first transistor T1 and the second transistor T2 are turned on simultaneously, the first transistor T1 sets the first node Q to high level again, the second transistor T2 pulls down the potential of the second node QB by the low-level second power supply signal again, while the potential of the reset signal terminal in (n) remains low, and the third transistor T3 and the fourth transistor T4 are turned off; at this time, the first node Q is at a high level, the second node QB is at a low level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the output terminal em (n) outputs the output signal at a high level again.

Thus, after passing through the first, second, and third stages t1, t2, and t3, the output terminal em (n) can output the negative pulse signal of which only the periods t2 and t2' are low and the other periods are high through cooperation of the respective transistors.

From the above analysis, the start period of the negative pulse signal is controlled by the reset signal terminal IN (n), and the pulse width of the negative pulse signal is substantially determined by the clock signal of the clock signal terminal CLK. In the application, the clock signal terminal CLK is independent of the shift register unit, so that the clock signal of the clock signal terminal CLK is not influenced by other circuits, that is, the pulse width of the light-emitting control signal can be freely controlled, and the light-emitting control unit of the embodiment of the application can flexibly control the light-emitting duration of the pixel.

In addition, the light-emitting control unit of the embodiment of the application solves the problem that output is uncertain when the output end EM (n) floats by arranging the storage unit, so that a correct and stable light-emitting control signal can be always output.

Further, as can be seen from fig. 3 and the above timing analysis, if the light emission control is performed between the pixels IN each row IN a row scanning manner, and the nth light emission control unit corresponding to the pixel IN the nth row and the (n +1) th light emission control unit corresponding to the pixel IN the (n +1) th row are to sequentially output the negative pulse signal, it is only necessary to control the reset signals of the reset signal terminals IN (n) and IN (n +1) and the clock signal terminals CLK (n) and CLK (n +1) to be separated by a high level clock period, and the reset signal terminals IN (n) and IN (n +1) may be provided by the shift register unit of the gate driving circuit, so that only the clock signal terminal with the timing variation needs to be provided. Therefore, the embodiment of the application realizes that the cascaded light-emitting control units are not needed through the connection and the matching of the transistors among the set sub-circuit, the reset sub-circuit and the output sub-circuit, each light-emitting control unit only has 6 transistors, the occupied area is small, the narrow-frame design is facilitated, the application requirements of the current industry on narrow-frame display products are met, and the application prospect is wide.

Based on the same inventive concept, referring to fig. 4, an embodiment of the present application further provides a gate driving circuit, including: 4 cascaded shift register cells 20-1, 20-2, 20-3, and 20-4; and 4 light emission control units 10-1, 10-2, 10-3, and 10-4 corresponding to the respective shift register units, wherein the light emission control units are the light emission control units described in the above embodiments.

Each shift register unit outputs pixel scanning signals, and each light-emitting control unit is correspondingly and electrically connected to one shift register unit so as to output light-emitting control signals for controlling the pixels to emit light.

It should be noted that, although the example of fig. 4 shows a case including 4 shift register units and 4 light-emission control units, the present application is not limited thereto, and a person skilled in the art may set the number of cascaded shift register units and the number of corresponding light-emission control units according to the number of pixel rows (or columns) to be scanned.

In this embodiment, by providing cascaded shift register units and light emission control units electrically connected to each shift register unit, and each light emission control unit includes the set sub-circuit, the reset sub-circuit, and the output sub-circuit described in the above embodiments, light emission control of each row (or each column) of pixels can be completed by using a light emission control unit with a simple structure, and the light emission control unit with an independent clock signal end can flexibly control the light emission time of the pixels, which has a wide application prospect.

Specifically, in order to more clearly illustrate the connection relationship and functions of the shift register unit and the light emission control unit, fig. 5 shows a specific example of the circuit structure of the shift register unit.

Referring to fig. 5, the main parts of a conventional shift register unit are shown in fig. 5. The shift register unit comprises an input sub-circuit formed by a transistor M1, a pull-up sub-circuit formed by a transistor M2 and a capacitor C, and a reset sub-circuit formed by a transistor M3. The input sub-circuit transmits a signal of a high-level signal end VDD to a pull-up node PU under the control of an input signal end STU; the pull-up sub-circuit transmits the clock signal of the clock signal terminal CK to the output terminal CR under the control of the potential of the pull-up node PU, that is, the shift register unit can be considered to output the scanning signal under the control of the clock signal accessed by the clock signal terminal CK (i.e., the first clock signal terminal); the reset sub-circuit resets the pull-up node through the low level signal terminal VGL under the signal control of the reset signal terminal TRS. The inverter simplifies and summarizes the circuit functions of the pull-down sub-circuit and the pull-down control sub-circuit, and reflects the signal relationship between the pull-up node PU and the pull-down node PU. Further, referring to fig. 4, the shift register unit further includes a noise reduction sub-circuit, here including a transistor M4 and a transistor M5, the pair of noise reduction sub-circuits being configured to reduce noise on the pull-up node PU through a transistor M4 and on the output CR through a transistor M5 under control of the pull-down node PU.

To further embody the signal terminals of the pull-down sub-circuit and the pull-down control sub-circuit, fig. 6 further provides a schematic diagram of an exemplary circuit including the pull-down sub-circuit and the pull-down control sub-circuit on the basis of fig. 5.

Referring to fig. 6, in this example, the pull-down control sub-circuit includes transistor M6 and the pull-down sub-circuit includes transistor M7. The pull-down control sub-circuit is electrically connected with the clock signal terminal CKB and the pull-down node PD, and transmits a clock signal of the clock signal terminal CKB to the pull-down node PD under the control of the clock signal terminal CKB; the pull-down sub-circuit is electrically connected with the pull-up node PU, the pull-down node PD and the low-level signal terminal VGL, and is configured to pull down the potential of the pull-down node PD through the low-level signal terminal VGL under the control of the pull-up node PU.

It should be noted that the circuit structures in fig. 5 and fig. 6 are only exemplary, and are not intended to limit the specific structure of the shift register unit included in the gate driving circuit, and the specific number of transistors of the pull-up sub-circuit, the reset sub-circuit, the noise reduction sub-circuit, the pull-down control sub-circuit, and the pull-down sub-circuit is not limited to that shown in fig. 5 and fig. 6, and is not repeated herein.

Further, taking the circuit configuration shown in fig. 6 as an example, the connection relationship between the shift register unit and the light emission control unit will be described with reference to fig. 4.

Specifically, the clock signal terminal CK and the clock signal terminal CKB of the 1 st-stage shift register unit 20-1 are electrically connected to the clock signal line CK and the clock signal line CKB, respectively, the clock signal line CK and the clock signal line CKB of the 2 nd-stage shift register unit 20-2 are electrically connected to the clock signal line CKB and the clock signal line CK, respectively, and so on, and are alternately connected in a two-stage repeating manner, and when there is no need to distinguish, the clock signal line electrically connected to the clock signal terminal CK is referred to as a first clock signal line; the reset signal terminals TRS of the shift register units 20-1, 20-2, 20-3, 20-4 are electrically connected to the input signal line TRS; the high-level signal terminal VDD is electrically connected to a high-level signal line DC; the input end STU of the 1 st stage shift register unit 20-1 is connected to an input signal, and the input ends of the following shift register units are all electrically connected to the output end CR of the shift register unit of the previous stage.

Further, the output CR of each stage of shift register unit is electrically connected to the corresponding light emission control unit, i.e. the output CR of the 1 st stage of shift register unit 20-1 is electrically connected to the input IN of the light emission control unit 10-1, the output CR of the 2 nd stage of shift register unit 20-2 is electrically connected to the input IN of the light emission control unit 10-2, the output CR of the 3 rd stage of shift register unit 20-3 is electrically connected to the input IN of the light emission control unit 10-3, and the output CR of the 4 th stage of shift register unit 20-4 is electrically connected to the input IN of the light emission control unit 10-4. In the present application, by using the step-by-step shift characteristic of the shift register unit, the third transistor T3 and the fourth transistor T4 in the light emission control unit are controlled to be turned on, so as to control each light control unit to correspondingly output the light emission control signal of the negative level step by step.

Further, referring to FIG. 4, it can be seen that the clock signal terminal CLK of the emission control units 10-1, 10-2, 10-3, 10-4 is connected to a clock signal line independent of the clock signal line of the shift register unit. In other words, when the clock signal line connected to the clock signal terminal CLK is referred to as a second clock signal line, the second clock signal line connected to the clock signal terminal of the light emission control unit and the first clock signal line electrically connected to the shift register unit are independent clock signal lines. Through the arrangement, the pulse width of the negative pulse of each light-emitting control unit can be independently controlled, so that the light-emitting duration of each light-emitting control unit is not limited by the circuit of the shift register, and the pulse width of the light-emitting control signal is more flexible.

In addition, it should be understood by those skilled in the art that the present application is not intended to limit the specific number of the clock signal lines, when the number of the light-emitting control units is greater, if 4 clock signal lines still need to be set, only the clock signal level of the 5 th clock signal end needs to be consistent with the clock signal of the 1 st clock signal end, as shown in the timing diagram shown in fig. 3, as long as the duty ratio of the clock signal of each clock signal line is 1/4, only 4 clock signal lines are needed to satisfy the design of any number of light-emitting control units, and the setting of the other number of clock signal lines is the same, and is not described herein again.

Based on the same inventive concept, a third aspect of the present application provides a display device including the gate driving circuit described in the above embodiments.

It should be noted that the gate driving circuit according to the embodiments of the present application can be applied to various display devices, and those skilled in the art should understand that any display device based on the operation mode of the gate driving circuit of the present application is within the scope of the present application.

A fourth aspect of the present application provides a control method for a light emission control unit of an embodiment of the present application, corresponding to the same inventive concept, including:

in the first stage, a high-level signal is provided to the input end to serve as an input signal, and the input sub-circuit transmits the input signal to a pull-up node to pull up the potential of the pull-up node;

a first stage in which the set sub-circuit transmits a first power supply signal to a first node in response to the received set signal to cause an output terminal of the output sub-circuit to output the first power supply signal,

in the second stage, the reset signal responds to the received reset signal to transmit the first power supply signal to the second node so as to reset the first node through the second power supply signal and enable the output end of the output sub-circuit to output the second power supply signal; and

and in the third stage, the setting signal is applied to the setting sub-circuit again so that the output end of the output sub-circuit outputs the first power supply signal.

Specifically, when the memory cell is included, the method further includes:

in the second phase, potentials of the first node and the second node are held by the first storage capacitor and the second storage capacitor.

It should be noted that the above control method is consistent with each stage described above with reference to fig. 3, and the specific process is not described again.

In the above manner, by using the light-emitting control unit with the set sub-circuit, the reset sub-circuit and the output sub-circuit, and by the above first stage, second stage and third stage, the transistors are mutually matched, so that a stable light-emitting control signal can be provided by a simple circuit structure, and the structure does not need to be cascaded, thereby being beneficial to narrow-frame design; in addition, by electrically connecting the control terminals of the first transistor and the second transistor to a clock signal terminal independent of the shift register unit, the light emitting time of the pixel can be flexibly controlled by the independent clock signal.

Aiming at the existing problems at present, the light-emitting control unit and the control method thereof, the grid drive circuit and the display device are formulated, the light-emitting control unit with the setting sub-circuit, the resetting sub-circuit and the output sub-circuit is provided, the setting sub-circuit is set to comprise the first transistor and the second transistor, the setting sub-circuit is configured to respond to the control of the clock signal end, the first node is set through the first power signal of the first power signal end, and the potential of the second node is pulled down through the second power signal of the second power signal end, so that a stable light-emitting control signal can be provided by a simple circuit structure, and the structure does not need to be cascaded and is beneficial to narrow-frame design; in addition, the control ends of the first transistor and the second transistor are electrically connected to the clock signal end independent of the shift register unit, so that the light emitting time of the pixel can be flexibly controlled through the independent clock signal, and the pixel driving circuit has a wide application prospect.

It should be understood that the above-mentioned examples are given for the purpose of illustrating the present application clearly and not for the purpose of limiting the same, and that various other modifications and variations of the present invention may be made by those skilled in the art in light of the above teachings, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed.

Claims (10)

1. A lighting control unit, comprising:

a set sub-circuit including a first transistor and a second transistor, a first terminal of the first transistor being electrically connected to a first power supply signal terminal, a second terminal being electrically connected to a first node, a control terminal being electrically connected to a clock signal terminal independent of the shift register unit, a first terminal of the second transistor being electrically connected to a second node, a second terminal being electrically connected to a second power supply signal terminal, the control terminal being electrically connected to the clock signal terminal, configured to set the first node by a first power supply signal of the first power supply signal terminal and pull down a potential of the second node by a second power supply signal of the second power supply signal terminal in response to control of a clock signal of the clock signal terminal;

a reset sub-circuit which resets the first node by the second power supply signal and pulls up a potential of the second node by the first power supply signal in response to control of a reset signal terminal; and

an output sub-circuit that controls output of the first power supply signal or the second power supply signal based on a potential of the first node and a potential of the second node.

2. The lighting control unit of claim 1, wherein the reset sub-circuit comprises: a third transistor and a fourth transistor,

a first terminal of the third transistor is electrically connected to the first power signal terminal, a second terminal of the third transistor is electrically connected to the second node, a control terminal of the third transistor is electrically connected to the reset signal terminal, a first terminal of the fourth transistor is electrically connected to the first node, a second terminal of the fourth transistor is electrically connected to the second power signal terminal, and a control terminal of the fourth transistor is electrically connected to the second node.

3. The lighting control unit of claim 1, wherein the output sub-circuit comprises a fifth transistor and a sixth transistor,

the first terminal of the fifth transistor is electrically connected to the first power signal terminal, the second terminal of the fifth transistor is electrically connected to the output terminal, the control terminal is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the output terminal, the second terminal of the sixth transistor is electrically connected to the second power signal terminal, and the control terminal is electrically connected to the second node.

4. The lighting control unit of claim 3, further comprising a storage sub-circuit comprising a first storage capacitor and a second storage capacitor,

wherein a first terminal of the first storage capacitor is electrically connected to the first node, a second terminal of the first storage capacitor is electrically connected to the output terminal, a first terminal of the second storage capacitor is electrically connected to the second node, and a second terminal of the second storage capacitor is electrically connected to the second power signal terminal.

5. The lighting control unit of claim 1, wherein the first power signal of the first power signal terminal is a high level signal, and the second power signal of the second power signal terminal is a low level signal.

6. The lighting control unit of claim 1, wherein the transistors in the lighting control unit are N-type transistors or P-type transistors.

7. A gate drive circuit, comprising: a plurality of cascaded shift register cells and a plurality of emission control cells according to any one of claims 1 to 6, the emission control cells corresponding one-to-one to the shift register cells,

the output end of each shift register unit is electrically connected with the reset signal end of the corresponding light-emitting control unit; and

wherein each shift register unit comprises a first clock signal terminal electrically connected to a first clock signal line, the shift register unit generates a gate scan signal under the control of a clock signal accessed by the first clock signal terminal,

the clock signal terminal of each light-emitting control unit is electrically connected to a second clock signal line, and the first clock signal line and the second clock signal line are mutually independent clock signal lines.

8. A display device comprising the gate driver circuit according to claim 7.

9. A lighting control method for a lighting control unit according to any one of claims 1 to 6, characterized by comprising:

a first stage in which the set sub-circuit transmits the first power supply signal to a first node in response to the received set signal to cause an output terminal of the output sub-circuit to output the first power supply signal,

a second stage in which the reset signal transmits the first power supply signal to the second node in response to the received reset signal to reset the first node by the second power supply signal and cause the output terminal of the output sub-circuit to output the second power supply signal; and

and in a third stage, the setting signal is applied to the setting sub-circuit again so that the output end of the output sub-circuit outputs the first power supply signal.

10. The light emission control method according to claim 9,

the light emission control unit further includes a storage sub-circuit including a first storage capacitor having a first terminal electrically connected to the first node and a second terminal electrically connected to the output terminal, and a second storage capacitor having a first terminal electrically connected to the second node and a second terminal electrically connected to the second power signal terminal,

the method further comprises the following steps:

in the second phase, potentials of the first node and the second node are held by the first storage capacitor and the second storage capacitor.

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