CN115132121A - Image display system, image processing circuit and panel driving method - Google Patents

Abstract

The application discloses an image display system, an image processing circuit and a panel driving method. The image display system comprises a display device, a second memory circuit and an image processing circuit. The display device comprises a panel and a first memory circuit. The first memory circuit is used for storing first preset data for controlling the panel. The second memory circuit is used for storing a second preset data. The image processing circuit is used for reading a first part of data in the first preset data and a second part of data in the second preset data and comparing the first part of data with the second part of data. If the first part of data is the same as the second part of data, the image processing circuit is also used for outputting a driving signal according to the second preset data to control the panel to start displaying images.

Description

Image display system, image processing circuit and panel driving method

Technical Field

The present invention relates to an image display system, and more particularly, to an image display system, an image processing circuit and a panel driving method capable of reducing the time for a panel to start displaying an image.

Background

In the conventional television system, in order to make a specific panel have a better display effect, an image processing chip needs to read related information about the specific panel from a display device and execute a corresponding image processing program according to the information to control the panel. However, since the display device and the image processing chip usually exchange data through a low-speed transmission interface, if the image processing chip needs to read the complete related information every time the display device is turned on, the time for the panel to start displaying the image is delayed. Thus, the user experience is not good.

Disclosure of Invention

In some embodiments, the image display system includes a display device, a second memory circuit, and an image processing circuit. The display device comprises a panel and a first memory circuit. The first memory circuit is used for storing first preset data for controlling the panel. The second memory circuit is used for storing a second preset data. The image processing circuit is used for reading a first part of data in the first preset data and a second part of data in the second preset data and comparing the first part of data with the second part of data. If the first part of data is the same as the second part of data, the image processing circuit is also used for outputting a driving signal according to the second preset data to control the panel to start displaying images.

In some embodiments, the image processing circuit includes a memory circuit and at least one processing circuit. The memory circuit is used for storing at least one program code. At least one processing circuit for executing the at least one program code to: reading a first part of data in first preset data from a first memory circuit in a display device, and reading a second part of data in second preset data from a second memory circuit; comparing the first portion of data with the second portion of data; and if the first part of data is the same as the second part of data, outputting a driving signal according to the second preset data to control a panel of the display device to start displaying images.

In some embodiments, the panel driving method includes the following operations: reading a first part of data in first preset data from a first memory circuit in a display device, and reading a second part of data in second preset data from a second memory circuit; comparing the first portion of data with the second portion of data; and if the first part of data is the same as the second part of data, outputting a driving signal according to the second preset data to control a panel of the display device to start displaying images.

The features, implementations, and functions of the present application are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of an image display system according to some embodiments of the present application;

FIG. 2 is a flow chart depicting a method of driving a panel according to some embodiments of the present application;

FIG. 3A is a schematic diagram depicting a plurality of lookup tables of FIG. 1 according to some embodiments of the present application;

FIG. 3B is a schematic diagram depicting a plurality of lookup tables of FIG. 1 according to some embodiments of the present application; and

fig. 4 is a schematic diagram illustrating the image processing circuit of fig. 1 according to some embodiments of the present disclosure.

[ notation ] to show

100 image display system

110 display device

112: panel

114,130,420 memory circuit

114A,114B,134A,134B lookup tables

114C,134C checksums

114D,134D Cyclic redundancy check code

120 image processing circuit

200 panel driving method

410 at least one processing circuit

C11-Cxy, G11-Gxy compensation gray scale value

D1, D2 preset data

DA, DB, partial data

S11-Sxy, V11-Vxy, drive voltage

S205, S210, S215, S220, S225, S230, S235, S240 operation

SD drive signal

P11-Pxy pixels

Detailed Description

All terms used herein have their ordinary meaning. The definitions of the above-described words in commonly used dictionaries are provided in the context of this application, and any use of the words discussed herein is meant to be exemplary only, and should not be construed as limiting the scope or meaning of the application. Similarly, the present application is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the present application. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.

Fig. 1 is a schematic diagram of an image display system 100 according to some embodiments of the present disclosure. In some embodiments, the image display system 100 may be a television, but the present application is not limited thereto. The image display system 100 may be any electronic device equipped with a screen.

The image display system 100 includes a display device 110, an image processing circuit 120 and a memory circuit 130. The display device 110 is used for displaying images based on the control of the image processing circuit 120. Display device 110 includes a panel 112 and a memory circuit 114. The panel 112 can display images according to the driving signal SD. In various embodiments, the panel 112 may be, but is not limited to, a backlight panel or a panel using Light Emitting Diodes (LEDs). Backlight panels include, but are not limited to, Twisted Nematic (Twisted Nematic) panels, Super Twisted Nematic (Super Twisted Nematic) panels, or Thin Film Transistor (Thin Film Transistor) panels. Panels that operate using light emitting diodes include Micro light emitting diode (Micro LED) panels, mini light emitting diode (mini LED) panels, Organic Light Emitting Diode (OLED) panels. The above description of the type of panel 112 is provided for purposes of example and the present application is not limited thereto.

The memory circuit 114 may be various types of memory circuits for storing the predetermined data D1. For example, the memory circuit 114 may be, but is not limited to, a flash memory circuit. In some embodiments, the memory circuit 114 may be a flash memory using Serial Peripheral Interface (SPI). The default data D1 includes image compensation parameter data and/or error detection data for the control panel 112. For example, the image compensation parameter data may include, but is not limited to, a lookup table 114A for adjusting (i.e., correcting) a plurality of pixel values (e.g., but not limited to, gray-scale values, chrominance values, RGB values, RGBW values, etc., so that the compensated gray-scale values as described in the following embodiments may be replaced accordingly) of the panel 112 and/or a lookup table 114B for improving the response time of the panel 112. For example, as shown in fig. 3A, the lookup table 114A stores compensation gray-scale values corresponding to a plurality of pixels, which can be used to perform a brightness non-uniformity (demura) correction procedure on the panel 112. For example, as shown in fig. 3B, the lookup table 114B stores driving voltage values corresponding to a plurality of pixels, which can be used for overdriving (overdriving) the corresponding pixels of the panel 112 to adjust (i.e., improve) the response time of the panel 112. In some embodiments, the error detection data may be used to verify the data integrity of the default data D1. The error detection data is pre-generated based on the data error detection algorithm and the complete predetermined data D1. For example, the error detection data may include a checksum (checksum) code 114C and/or a Cyclic Redundancy Check (CRC) code 114D. In other embodiments, the error detection data may be replaced with the product serial number of the panel 112.

It should be understood that in other embodiments, the lookup tables 114A and 114B in the default data D1 may be implemented by at least one (i.e., one or more) lookup tables. Similarly, in other embodiments, the lookup tables 134A and 134B in the default data D2 can also be implemented by at least one lookup table.

The above-mentioned types of the image compensation parameter data and/or the error detection data are used for illustration, and the application is not limited thereto. Various image compensation parameter data associated with the panel 112 and various error detection data that may be used to verify data integrity are within the scope of the present application.

The memory circuit 130 is coupled to the image processing circuit 120 and is configured to store the predetermined data D2. In some embodiments, the preset data D2 may be preset data (e.g., the preset data D1) received by the image processing circuit 120 from the display device 110 (or other display devices) in a previous operation. In other words, the class default data D2 may include image compensation parameter data and/or error detection data corresponding to the default data D1. For example, the predetermined data D2 includes a lookup table 134A corresponding to the lookup table 114A, a lookup table 134B corresponding to the lookup table 114B, a checksum code 134C corresponding to the checksum code 114C, and/or a crc code 134D corresponding to the crc code 114D, but the application is not limited thereto. In some embodiments, memory circuit 130 may be various types of memory circuits. For example, the memory circuit 130 may be, but is not limited to, a flash memory circuit. In some embodiments, the memory circuit 130 may be an embedded multimedia memory card (emmc). In some embodiments, the data transmission speed between the memory circuit 130 and the image processing circuit 120 (e.g., the transmission speed conforming to the emmc standard) is faster than the data transmission speed between the memory circuit 114 and the image processing circuit 120 (e.g., the transmission speed of the SPI interface).

The image processing circuit 120 is configured to read the partial data DA in the preset data D1 from the memory circuit 114 and read the partial data DB in the preset data D2 from the memory circuit 114 to perform a plurality of operations as described in fig. 2. Thus, the image processing circuit 120 can generate the driving signal SD to drive the panel 112 to start displaying the image. The operation will be described later with reference to fig. 2. In some embodiments, the image processing circuit 120 may be, but is not limited to, an image processing chip.

Fig. 2 is a flow chart depicting a method 200 of driving a panel according to some embodiments of the present application. In some embodiments, the panel driving method 200 may be performed by (but not limited to) the image processing circuit 120 of fig. 1.

In operation S205, a first portion of the first predetermined data is read from the first memory circuit, and a second portion of the second predetermined data is read from the second memory circuit. In operation S210, the first partial data and the second partial data are compared. If the first portion of data is the same as the second portion of data, operation S215 is performed. Alternatively, if the first portion of data is different from the second portion of data, operation S240 is performed.

To understand operations S205 and S210, refer to fig. 3A and 3B. Fig. 3A is a diagram illustrating the lookup table 114A and the lookup table 134A in fig. 1 according to some embodiments of the present disclosure, and fig. 3B is a diagram illustrating the lookup table 114B and the lookup table 134B in fig. 1 according to some embodiments of the present disclosure.

As shown in FIG. 3A, the lookup table 114A is used to correct the gray-scale values of the plurality of pixels in the panel 112. The lookup table 114A includes a plurality of data indicating a correspondence between a plurality of pixels P11 Pxy and a plurality of compensated gray-scale values G11 Gxy, wherein x and y are positive integers greater than 1. In operation S205, after the image processing circuit 120 is powered on, the image processing circuit 120 may read the first three data in the lookup table 114A from the memory circuit 114 as partial data DA, but the application is not limited thereto. In other words, the partial data DA is not the complete preset data D1. Corresponding to the lookup table 114A, the lookup table 114B includes a plurality of data indicating the corresponding relationship between the plurality of pixels P11 Pxy and the plurality of compensated gray-scale values C11 Cxy. Similarly, in operation S205, after the image processing circuit 120 is powered on, the image processing circuit 120 may read the first three data in the lookup table 134A from the memory circuit 130 as the partial data DB, but not limited thereto. In other words, the partial data DB is not the complete preset data D2. Thus, the image processing circuit 120 can compare the partial data DA with the partial data DB. If the partial data DA is the same as the partial data DB (e.g., the compensated gray-scale values G11-G13 are the same as the compensated gray-scale values C11-C13), the image processing circuit 120 may perform operation S215. Alternatively, if the partial data DA is different from the partial data DB, the image processing circuit 120 may perform operation S240.

Similarly, as shown in fig. 3B, the lookup table 114B is used to correct the driving voltages of a plurality of pixels in the panel 112. The lookup table 114B includes a plurality of data indicating the correspondence between the plurality of pixels P11 through Pxy and the plurality of driving voltages V11 through Vxy. In operation S205, the image processing circuit 120 may read the first three data in the lookup table 114B from the memory circuit 114 as partial data DA, but the application is not limited thereto. Corresponding to the lookup table 114B, the lookup table 134B includes a plurality of data indicating the corresponding relationship between the plurality of pixels P11 Pxy and the plurality of driving voltages S11 Sxy. Similarly, in operation S205, the image processing circuit 120 can read the first three data in the lookup table 134B from the memory circuit 130 as the partial data DB, but the application is not limited thereto. If the partial data DA is identical to the partial data DB (e.g., the driving voltages V11 to V13 are identical to the driving voltages S11 to S13), the image processing circuit 120 may perform operation S215. Alternatively, if the partial data DA is different from the partial data DB, the image processing circuit 120 may perform operation S240.

It should be understood that the data arrangement of fig. 3A and 3B is for example, and the application is not limited thereto. The partial data DA may be at least one piece of data in the lookup table 114A, and the data amount of the partial data DA is smaller than the data amount of the preset data D1. The partial data DB may be at least one data in the lookup table 134A, and the data amount of the partial data DB is smaller than that of the preset data D2. In some embodiments, partial data DA may be stored anywhere in lookup table 114A and partial data DB may be stored anywhere in lookup table 134A. In some embodiments, partial data DA and partial data DB may be data or critical data sufficient to light panel 112, but are not limited thereto.

Alternatively, in other examples, after the image processing circuit 120 is powered on, the image processing circuit 120 may read the checksum code 114C in the preset data D1 as the partial data DA from the memory circuit 130, read the checksum code 134C in the preset data D2 as the partial data DB from the memory circuit 130, and determine whether to perform the operation S215 or the operation S240 according to the comparison result between the partial data DA and the partial data DB. Similarly, in some examples, after the image processing circuit 120 is powered on, the image processing circuit 120 may read the crc 114D in the predetermined data D1 as the partial data DA from the memory circuit 130, read the crc 134D in the predetermined data D2 as the partial data DB from the memory circuit 130, and perform the operation S215 or the operation S240 according to the comparison result between the partial data DA and the partial data DB.

With reference to fig. 2, in operation S215, the complete second predetermined data is read from the second memory circuit to output the driving signal according to the second predetermined data to control the panel to start displaying the image. For example, if the partial data DA is identical to the partial data DB, the predetermined data D1 may be identical to the predetermined data D2. Under this condition, the image processing circuit 120 can read the complete preset data D2 from the memory circuit 130 and output the corresponding driving signal SD according to the preset data D2 to control the panel 112 to start displaying the image. Since the display device 110 and the image processing circuit 120 usually exchange data through a low-speed interface (such as, but not limited to, a serial peripheral interface), the transmission speed between the memory circuit 130 and the image processing circuit 120 is usually faster than the data transmission speed between the display device 110 and the image processing circuit 120. Therefore, by operations S205, S210 and S215, the image processing circuit 120 can read the complete predetermined data D2 from the memory circuit 130 with the faster transmission speed to start outputting the driving signal SD according to the predetermined data D2 to control the panel 112 to display the image. Thus, the lighting time of the panel 112 (i.e. the time to start displaying the image) can be advanced.

In operation S220, the first predetermined data is read from the first memory circuit. In operation S225, the first preset data and the second preset data are compared. If the first preset data is different from the second preset data, operation S230 is performed. If the first preset data is the same as the second preset data, the driving signal is continuously output according to the second preset data to drive the panel. In operation S230, the driving signal is adjusted according to the first preset data.

For example, during the period of generating the driving signal SD according to the preset data D2, the image processing circuit 120 may read the complete preset data D1 from the memory circuit 114 and compare the complete preset data D1 with the complete preset data D2. If the predetermined data D1 is identical to the predetermined data D2, it represents that the predetermined data D2 previously stored by the memory circuit 130 correctly corresponds to the data for the control panel 112. Under this condition, the image processing circuit 120 may output the driving signal SD according to the preset data D2 and stop comparing the preset data D1 with the preset data D2. Alternatively, if the default data D1 is different from the default data D2, it represents that the default data D2 previously stored by the memory circuit 130 does not correctly correspond to the data for the control panel 112. Under this condition, the image processing circuit 120 adjusts the driving signal SD according to the predetermined data D1, so that the panel 112 can display a more suitable image.

In operation S240, the first memory circuit reads the complete first preset data and outputs a driving signal to control the panel to start displaying the image according to the first preset data. For example, if the partial data DA is different from the partial data DB, the predetermined data D2 represents the image compensation data for controlling other panels (not the panel 112). Therefore, similar to operation S230, the image processing circuit 120 can output the driving signal SD according to the complete preset data D1 to ensure that the panel 112 can display a more suitable image.

In operation S235, the second preset data in the second memory circuit is updated to the first preset data. For example, if the default data D1 is different from the default data D2, the image processing circuit 120 may store the default data D1 in the memory circuit 130 to update the default data D2 to the default data D1. Thus, the lighting time of the panel 112 can be advanced in the next operation.

In some embodiments, operations S215-S230 may be omitted if the partial data DA is error detection data (i.e., checksum code 114C and/or crc code 114D) and the partial data DB is corresponding error detection data (i.e., checksum code 134C and/or crc code 134D). Since the error detection data is generated based on the complete default data D1 and the data error detection algorithm, the partial data DA sufficiently reflects the complete default data D1. Similarly, since the error detection data (i.e., the checksum code 134C and/or the crc code 134D) is generated based on the complete predetermined data D2 and the data error detection algorithm, the partial data DB is sufficient to reflect the complete predetermined data D2. Under this condition, if the partial data DA is the same as the partial data DB, it is sufficient to consider the preset data D1 as the preset data D2. The image processing circuit 120 may output the driving signal SD according to the preset data D2 without comparing the complete preset data D2 with the complete preset data D1 (i.e., operation S225). In other words, operations S215 to S230 may be selectively set depending on the types of the partial data DA and the partial data DB.

In some embodiments, if the default data D1 includes error detection data (i.e., checksum code 134C and/or crc code 134D), the error detection data is preferably read as the partial data DA by the image processing circuit 120.

The above description of the operations can refer to the above embodiments, and thus, the description thereof is not repeated. The operations of the panel driving method 200 are only examples, and need not be performed in the order of the examples. The various operations under the panel driving method 200 may be added, replaced, omitted, or performed in a different order (e.g., simultaneously or partially simultaneously) as appropriate without departing from the manner and scope of operation of the embodiments of the present application.

Fig. 4 is a schematic diagram illustrating the image processing circuit 120 of fig. 1 according to some embodiments of the present disclosure. The image processing circuit 120 includes at least one processing circuit 410 and a memory circuit 420. The at least one processing circuit 410 may be at least one digital signal processing circuit for processing an image to generate the driving signal SD. For example, the at least one digital signal processing circuit may include, but is not limited to, at least one of a video encoder circuit, a video decoder circuit, a scaler circuit, or a translator circuit. In other embodiments, the at least one processing circuit 410 may be a Central Processing Unit (CPU), an Application-specific integrated circuit (ASIC), a multiprocessor, a pipelined processor, a distributed processing system, and/or an image processing circuit. The at least one processing circuit 410 may receive the preset data D1 and/or the partial data DA from the display device 110 and receive the preset data D2 and/or the partial data DB from the memory circuit 130 (i.e., operations S205, S215, S220, or S240 of fig. 2). In some embodiments, if the default data D1 is different from the default data D2, the at least one processing circuit 410 may also transmit the default data D1 to the memory circuit 130 (i.e., operation S235 of fig. 2).

In some embodiments, the memory circuit 420 may be operated as a data buffer to temporarily store various data generated by the at least one processing circuit 410 executing the panel driving method 200 of fig. 2. In some embodiments, the memory circuit 420 stores at least one program code, which may be encoded by a plurality of instruction sets. The at least one processing circuit 410 may execute the at least one program code stored in the memory circuit 420 to perform the operations of the panel driving method 200.

In some embodiments, the memory circuit 420 may be a non-transitory computer readable storage medium storing executable instructions for performing operations as described in FIG. 2. In some embodiments, the computer readable storage medium may be, but is not limited to, an electronic, magnetic, optical, infrared, and/or semiconductor device. For example, a computer-readable storage medium may include, but is not limited to, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical magnetic disk.

In summary, the image display apparatus, the display processing circuit and the panel driving method in some embodiments of the present disclosure can advance the time when the panel starts to display the image. Thus, the user experience can be improved.

Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can apply variations to the technical features of the present application according to the explicit or implicit contents of the present application, and all such variations may fall within the scope of the patent protection sought by the present application, in other words, the scope of the patent protection sought by the present application should be determined by the claims of the present application.

Claims (10)

1. An image display system, comprising:

the display device comprises a panel and a first memory circuit, wherein the first memory circuit is used for storing first preset data for controlling the panel;

a second memory circuit for storing a second predetermined data; and

an image processing circuit for reading a first part of the first predetermined data and a second part of the second predetermined data and comparing the first part of the first predetermined data with the second part of the second predetermined data,

if the first part of data is the same as the second part of data, the image processing circuit is also used for outputting a driving signal according to the second preset data to control the panel to start displaying images.

2. The image display system of claim 1, wherein the first portion of data is not the complete first default data and the second portion of data is not the complete second default data.

3. The image display system of claim 1, wherein the first predetermined data comprises an image compensation parameter data corresponding to the panel.

4. The image display system of claim 3, wherein the image compensation parameter data comprises at least one look-up table, and the at least one look-up table is used to adjust at least one of a plurality of pixel values of the panel or a response time of the panel.

5. The image display system of claim 1, wherein a data transfer speed between the second memory circuit and the image processing circuit is faster than a data transfer speed between the first memory circuit and the image processing circuit.

6. The image display system of claim 1, wherein the first portion of data comprises a checksum code or a crc code.

7. The image display system of claim 1, wherein the image processing circuit is further configured to read the complete first predetermined data to generate the driving signal according to the first predetermined data and update the second predetermined data to the first predetermined data if the first portion of data is different from the second portion of data.

8. The image display system of claim 1, wherein the image processing circuit is further configured to read the first predetermined data and the second predetermined data in their entirety and compare the first predetermined data with the second predetermined data if the first portion of data is the same as the second portion of data, and adjust the driving signal according to the first predetermined data and update the second predetermined data in the second memory circuit to the first predetermined data if the first predetermined data is different from the second predetermined data.

9. An image processing circuit, comprising:

a memory circuit for storing at least one program code; and

at least one processing circuit for executing the at least one program code to:

reading a first part of data in first preset data from a first memory circuit in a display device, and reading a second part of data in second preset data from a second memory circuit;

comparing the first portion of data with the second portion of data; and

and if the first part of data is the same as the second part of data, outputting a driving signal according to the second preset data to control a panel of the display device to start displaying images.

10. A panel driving method, comprising:

reading a first part of data in first preset data from a first memory circuit in a display device, and reading a second part of data in second preset data from a second memory circuit;

comparing the first portion of data with the second portion of data; and

and if the first part of data is the same as the second part of data, outputting a driving signal according to the second preset data to control a panel of the display device to start displaying images.

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