CN115117863A - Method for processing interphase short circuit of three-phase power system - Google Patents
Method for processing interphase short circuit of three-phase power system Download PDFInfo
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- CN115117863A CN115117863A CN202210073737.0A CN202210073737A CN115117863A CN 115117863 A CN115117863 A CN 115117863A CN 202210073737 A CN202210073737 A CN 202210073737A CN 115117863 A CN115117863 A CN 115117863A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
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Abstract
The invention discloses a method for processing interphase short circuit of a three-phase power system, wherein a plurality of switches are arranged on the three-phase power system, the switches can detect current signals and voltage signals, when the interphase short circuit fault occurs so as to generate short-circuit current, from the time of generating the short-circuit current, one switch detects the short-circuit current and continues to a preset trip time period, namely the switch trips, the switch which does not detect the short-circuit current detects the voltage signals, and the other switch does not detect the voltage signals after the planned trip time of the first switch at the upstream of the switch, namely the switch trips. The method can cut off the nearest switches at two sides of the interphase short-circuit fault point so as to cut off the short-circuit fault and enable the system to be self-healed, and is convenient to operate and high in practicability.
Description
Technical Field
The invention relates to the field of power system protection, in particular to a method for processing interphase short circuit of a three-phase power system.
Background
Regarding a method for processing an interphase short circuit of a three-phase power system, common practice at present is as follows: 1. the reclosing mode is adopted: the first breaker on the line is cut off firstly and then closed, if the first breaker is a transient phase-to-phase short circuit and is eliminated after the first breaker is closed, normal power supply is continued. And if the interphase short-circuit fault still exists after the first breaker is closed, the first breaker is cut off to wait for maintenance. 2. The first breaker is tripped firstly when overcurrent occurs, then the load switches are tripped out without current at the last (other load switches are in a closing state), then the first breaker is superposed, if the fault occurs below the last load switch, the fault can be eliminated, otherwise, the fault current still exists after the first breaker is superposed, at the moment, the first breaker is tripped out again when overcurrent occurs, then the last load switch is tripped out without current, then the first breaker is reclosed again, and if the interphase short circuit occurs between the last load switch and the last load switch, the fault can be eliminated. And by parity of reasoning, the load switch is switched off under no current sequentially upwards until the fault is eliminated. During this operation, the power supply system is repeatedly subjected to large short-circuit current surges, which, if excessive, can cause damage to the lines and, in addition, can take a long time to clear the lines. 3. The circuit breakers with fault current tripping capability are configured on the circuit, when a fault occurs, all the circuit breakers are set to be tripped by overcurrent, then the circuit breakers are switched on from the first circuit breaker, and the circuit breakers are tripped by overcurrent, so that the fault is eliminated. If the first breaker is successfully switched on without overcurrent, the first breaker is switched off for overcurrent tripping for a period of time, and the second breaker is switched on in the period of time. If there is no over-current then the next is closed and so on. The scheme has complex logic and relatively complex operation. 4. Adopting a time step difference matching method: the method can isolate a fault area, but for a fault with a fault point close to the power supply, a power supply system has long time for tolerating short-circuit current and large impact on a power grid, and although a switch between the fault point and the power supply is cut off, an area behind the fault point cannot be supplied with power through a standby power supply because the fault point is not eliminated, namely the power grid cannot be self-healed. Self-healing is to control the power outage to a smaller area by turning off both switches at the fault point and supplying power to the area other than the area between the turned-off switches at both sides of the fault point using two power sources.
Disclosure of Invention
The invention aims to provide a method for processing interphase short circuit of a three-phase power system, which can cut off the nearest switches at two sides of an interphase short circuit fault point so as to cut off the short circuit fault and enable the system to self-heal, and has the advantages of convenient operation and strong practicability.
In order to achieve the purpose, the invention adopts the following technical scheme:
a three-phase power system interphase short circuit processing method is characterized in that a plurality of switches are arranged on a three-phase power system, the switches can detect current signals and voltage signals, and when an interphase short circuit fault occurs and short circuit current is generated, the processing is carried out according to the following steps:
s1: starting from the short-circuit current generation moment, tripping when a certain switch detects that the short-circuit current continues to a preset tripping time, wherein the preset tripping time of the switch close to the power supply side is preset to be longer than the preset tripping time of the switch far away from the power supply side;
s2: and the voltage signal is detected by the switch which does not detect the short-circuit current, and the voltage signal is not detected by a certain switch after the planned tripping time of the first switch at the upstream of the switch, wherein the upstream is the direction of counting the switches towards the power supply side, and the planned tripping time is the time when the first switch at the upstream of the switch is supposed to trip according to the preset tripping time length from the generation time of the short-circuit current.
Preferably, the voltage signal is a phase voltage signal between a certain phase line of the three-phase lines and the ground;
or the voltage signal is a line voltage signal between a certain two-phase line of the three-phase line;
or the voltage signal is 3U of the three-phase line 0 A voltage signal.
In the above-mentioned scheme, when the interphase short-circuit fault occurs, the fault current flows through the fault phase conductor between the fault point and the power supply, and the corresponding switch of the line can detect the fault current, and the closer to the fault point the more the switch isThe shorter the duration of the current to off trigger the trip, the closer the switch through which the fault current flows to the fault point must trip and break the current before the other switches capable of detecting the fault current. A phase voltage of a relatively earth on the three-phase line or a line voltage between the two lines or 3U 0 The voltage also changes and presents a unique voltage signal which does not disappear until the switch trips to cut off the fault current, and the voltage signal is distributed on the whole wire according to the principle that the wire potential is equal and does not disappear until the fault current is cut off. In the invention, timing is carried out from the moment when the interphase short-circuit fault generates the fault current, the time point (the time point is a moment on a time sequence from the moment when the interphase short-circuit fault generates the fault current signal) of the supposed tripping triggered by the current signal of each switch can be planned in advance according to the current duration condition triggering the tripping, and the time point is added with the mechanical action time consumed by the switch from the beginning to the complete tripping of the switch to cut off the current, so that the planned tripping moment of each switch can be obtained. The moment a switch trips according to the current condition, the first switch downstream of it (this switch is on the side of the fault point facing away from the power supply, so neither this switch nor the switches further downstream detect the fault current at all times) can no longer detect the voltage signal from that moment on, and if this trips, the expectation is achieved that the nearest switch on the back side of the fault point trips. Since each switch is planned with an assumed trip time in time series (these trip times are arranged in sequence in time series), the voltage condition for triggering the trip of a certain switch is set to be that no voltage signal can be detected after the assumed trip time of the first switch at the upstream, only the switch meets the condition, and the other switches at the downstream of the switch can detect the voltage signal after the planned trip time of the first switch at the upstream, so the switch can not trip.
Drawings
FIG. 1 is a schematic diagram of the relevant structure of a three-phase power system in the method of the present invention (the lines, switches and power supply to the right of the demarcation switch 14 are omitted by dashed lines);
FIG. 2 is a schematic diagram of an interphase short circuit simulation circuit;
FIG. 3 is a simulated line voltage variation curve of an interphase short-circuit (three lines represent line voltages at interphase AB, BC and CA respectively);
FIG. 4 is a simulated phase-to-phase short-circuited phase voltage variation (three lines each representing A, B, C phase voltages relative to ground);
FIG. 5 shows a simulated interphase short-circuit fault with 3U at the fault point grounded 0 Voltage change curve.
Detailed Description
The invention will be further illustrated by the following specific embodiments in conjunction with the accompanying drawings:
as shown in fig. 1, the three-phase power system includes a power source and a three-phase line 20, wherein a plurality of switches, such as switches 10, 11, 12, 13, etc., are disposed on the three-phase line 20, a demarcation switch 14 is used for separating the connection between the two power sources, and when the demarcation switch 14 is closed, the other power source can be used as a backup power source for supplying power.
Assuming that a phase-to-phase short circuit fault occurs in the BC two-phase at the point F, the method is as follows:
the presence of the short-circuit current signal is accompanied by a phase voltage signal between one phase line of the three-phase line and the ground, a line voltage signal between one two phase lines of the three-phase line, or 3U of the three-phase line 0 The voltage signal changes.
The switch has the capability of detecting the current duration and the voltage (only a current inductor and a voltage inductor are required to be arranged on the switch, and the current inductor and the voltage inductor are common in the field), and the trip setting can be carried out according to the current signal or the voltage signal. The preset tripping time of the switch close to the power supply side is set to be longer than the preset tripping time of the switch far away from the power supply side in advance, for example, the current time (namely the preset tripping time) of the switches 10, 11, 12 and 13 triggering tripping is respectively set to be 0 (namely short-circuit current is detected to be tripping), 100, 200 and 300 milliseconds, when the current lasts for 200 milliseconds, the switch 12 trips, the switches 10 and 11 cannot trip because no short-circuit current flows, and the switch 13 cannot trip because no current exists after the switch 12 trips, so that the switch (namely the switch 12) closest to a fault point F can be guaranteed to trip. As will be appreciated by those skilled in the art, the difference in the current durations at which the switch triggers a trip is greater than the time at which the switch trips, depending on the current duration.
In the presence of a short-circuit current, the section switches 10, 11, 12, 13 all detect a voltage signal, but only the switches that do not detect a short-circuit current are tripped according to the voltage condition in the logic setting, and the switches that have a short-circuit current flowing through them are not tripped according to the voltage condition.
In one embodiment, the voltage condition for the switch trip is set as follows:
when an inter-phase short-circuit fault occurs, a fault current is generated (at this time, a line voltage between two fault phases suddenly drops, and therefore, the line voltage can also be used as a time starting point for judging the occurrence of the short-circuit fault by a sensor) at a time point of 0ms and starting timing, the current duration difference is set to 100ms, a time point of 0ms is triggered and tripped by a fault current signal (namely, tripping is simultaneously carried out as long as the occurrence of the fault current is detected), the mechanical action time of the switch tripping is set to 50 ms (namely, it takes 50 ms for the switch to trip completely to switch off the cut-off current from the beginning), the time point of 50 ms is set for the switch 10 tripping, and so on, the time point of 150 ms for the switch 11 tripping, the time point of 250 ms for the switch 12, and the time point of 350 ms for the switch 13 (these time points are planning tripping time points, that are supposed to trip according to plan, in practice, which switch is to be tripped is to be considered, and the position of the fault point appears randomly), etc., assuming that the fault point F is located between the switches 12 and 11, the switch 12 is tripped at the time of 250 ms according to the current condition, the switch 11 can not detect the voltage signal any more after the 250 ms, and can be tripped accordingly, and the voltage condition for triggering the trip of the switch 10 is that the voltage signal can not be detected after the 150 ms (because the first switch upstream is the switch 11, and the time for tripping the switch 11 is the 150 ms), but according to the position of the current fault point F, the switch 11 can not be tripped according to the current condition, so that the voltage signal is left after the 150 ms, and thus the switch 10 can detect the voltage signal, and can not trip. The same applies to the other switches, so that this condition ensures that only the non-current switch closest to the fault point F trips, and the other non-current switches do not trip, and are independent of the specific position at which the fault point F randomly appears. Therefore, the voltage trip condition can be summarized as: switches which do not detect short-circuit current detect a voltage signal, and a switch trips without detecting a voltage signal after the planned tripping time of the first switch upstream of the switch. The upstream in the present invention means the direction of counting the switches in sequence while going toward the power source, and the downstream means the opposite direction.
The 10KV power supply system is subjected to interphase short circuit simulation in simulation software, and line voltage and phase voltage during pure interphase short circuit and 3U during interphase short circuit with grounding are simulated respectively 0 Voltage, it can be seen that after the switch upstream of the fault point is tripped, the voltage signals detected by the switch downstream of the fault point are obviously different, so that these voltage signals can be used as the criterion for tripping the downstream switch, and the analog line building interface is as shown in fig. 2.
Simulation example 1: 0.1S, BC phase short circuit, 0.25S, switch 1 disconnection, 0.3S, switch 2 disconnection, line voltage as shown in figure 3, and as can be seen from figure 3, before and after switch 1 disconnection, line voltage has obvious change, which can be used as the criterion of switch 2 tripping.
Simulation example 2: 0.1S, BC phase-to-phase short circuit, 0.25S, switch 1 off, 0.3S, switch 2 off, phase voltage as shown in figure 4, it can be seen from figure 4 that before and after switch 1 off, phase voltage has obvious change, which can be used as criterion for switch 2 tripping.
Simulation example 3: 0.1S, BC phase-to-phase short circuit is additionally grounded, 0.25S, the switch 1 is disconnected, 0.3S, the switch 2 is disconnected, and 3U0 voltage is shown in figure 5, as can be seen from figure 5, before and after the switch 1 is disconnected, 3U0 voltage has obvious change and can be used as a criterion of tripping of the switch 2.
The above embodiments are merely illustrative of the concept and implementation of the present invention, and are not restrictive, and technical solutions that are not substantially changed under the concept of the present invention are still within the scope of protection.
Claims (2)
1. A three-phase power system interphase short circuit processing method is provided, wherein a plurality of switches are arranged on the three-phase power system, and the switches can detect current signals and voltage signals, and is characterized in that: when an interphase short-circuit fault occurs, and thus a short-circuit current is generated, the method comprises the following steps:
s1: starting from the short-circuit current generation moment, tripping when a certain switch detects that the short-circuit current continues to a preset tripping time, wherein the preset tripping time of the switch close to the power supply side is preset to be longer than the preset tripping time of the switch far away from the power supply side;
s2: and the voltage signal is detected by the switch which does not detect the short-circuit current, and the voltage signal is not detected by a certain switch after the planned tripping time of the first switch at the upstream of the switch, wherein the upstream is the direction of counting the switches towards the power supply side, and the planned tripping time is the time when the first switch at the upstream of the switch is supposed to trip according to the preset tripping time length from the generation time of the short-circuit current.
2. A method of handling an inter-phase short circuit in a three-phase electric power system according to claim 1,
the voltage signal is a phase voltage signal between a certain phase line of the three-phase line and the ground;
or the voltage signal is a line voltage signal between a certain two-phase line of the three-phase line;
or the voltage signal is 3U of the three-phase line 0 A voltage signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210073737.0A CN115117863A (en) | 2022-01-21 | 2022-01-21 | Method for processing interphase short circuit of three-phase power system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210073737.0A CN115117863A (en) | 2022-01-21 | 2022-01-21 | Method for processing interphase short circuit of three-phase power system |
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| Publication Number | Publication Date |
|---|---|
| CN115117863A true CN115117863A (en) | 2022-09-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210073737.0A Pending CN115117863A (en) | 2022-01-21 | 2022-01-21 | Method for processing interphase short circuit of three-phase power system |
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| Country | Link |
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| CN (1) | CN115117863A (en) |
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- 2022-01-21 CN CN202210073737.0A patent/CN115117863A/en active Pending
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