CN115116507A - Integrated magnetic storage unit - Google Patents
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- CN115116507A CN115116507A CN202110284592.4A CN202110284592A CN115116507A CN 115116507 A CN115116507 A CN 115116507A CN 202110284592 A CN202110284592 A CN 202110284592A CN 115116507 A CN115116507 A CN 115116507A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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Abstract
本发明提供一种存算一体的磁性存储单元，包括：重金属层、位于重金属层表面的磁性隧道结以及磁性隧道结表面的电极，磁性隧道结包括：依次层叠设置的自由层、势垒层和参考层，所述自由层与所述重金属层相邻设置，所述重金属层与所述自由层之间的相互作用为自旋轨道矩及DMI效应；所述重金属层具有至少三个通电端口，包括两个输入端和一个控制端，两个所述输入端和所述控制端的状态共同决定所述重金属层电流方向，以进一步决定所述磁性隧道结的阻态信息。本发明能够充分利用SOT‑MRAM的物理特性进行存内计算。
The invention provides a magnetic storage unit with integrated storage and computing, comprising: a heavy metal layer, a magnetic tunnel junction located on the surface of the heavy metal layer, and an electrode on the surface of the magnetic tunnel junction. The magnetic tunnel junction includes: a free layer, a potential barrier layer and A reference layer, the free layer is disposed adjacent to the heavy metal layer, and the interaction between the heavy metal layer and the free layer is spin-orbit moment and DMI effect; the heavy metal layer has at least three power-on ports, It includes two input terminals and one control terminal. The states of the two input terminals and the control terminal jointly determine the current direction of the heavy metal layer, so as to further determine the resistance state information of the magnetic tunnel junction. The present invention can make full use of the physical properties of the SOT-MRAM to perform in-memory computing.
Description
技术领域technical field
本发明涉及磁性存储器技术领域，尤其涉及一种存算一体的磁性存储单元。The present invention relates to the technical field of magnetic memory, in particular to a magnetic storage unit integrating storage and computing.
背景技术Background technique
近年来，随着大数据和AI的发展，相关应用对计算能力的需求也随之提升。但传统冯诺依曼架构计算机计算和存储是分离的，数据的频繁调用和存储产生了大量的功耗，已经成了计算智能化的瓶颈。In recent years, with the development of big data and AI, the demand for computing power in related applications has also increased. However, traditional Von Neumann architecture computer computing and storage are separated, and frequent data recall and storage generate a lot of power consumption, which has become a bottleneck for computing intelligence.
存算一体架构被认为是解决目前冯诺依曼架构中存储墙和访存功耗墙问题的有效手段。存算一体架构中，存储单元直接具有逻辑计算能力，能够有效消除数据移动的延迟和功耗。The storage-computing integrated architecture is considered to be an effective means to solve the storage wall and memory access power wall problems in the current Von Neumann architecture. In the integrated storage and computing architecture, the storage unit directly has the logical computing capability, which can effectively eliminate the delay and power consumption of data movement.
自旋轨道转矩磁性存储器(SOT-MRAM)具有高写入速度、低功耗、高集成度、具有可编程逻辑、与CMOS兼容等特点，非常适合用来设计存算一体计算机。但目前还没有行之有效的实现存算一体的磁性存储单元。Spin-orbit torque magnetic memory (SOT-MRAM) has the characteristics of high writing speed, low power consumption, high integration, programmable logic, and CMOS compatibility. However, there is no effective magnetic storage unit that realizes the integration of storage and computing.
发明内容SUMMARY OF THE INVENTION
为解决上述问题，本发明提供了一种存算一体的磁性存储单元，能够充分利用SOT-MRAM的物理特性进行存内计算。In order to solve the above problems, the present invention provides a magnetic storage unit with integrated storage and computing, which can fully utilize the physical characteristics of SOT-MRAM to perform in-memory computing.
第一方面，本发明提供一种存算一体的磁性存储单元，包括：In a first aspect, the present invention provides a magnetic storage unit with integrated storage and computing, including:
重金属层；heavy metal layer;
位于所述重金属层表面的磁性隧道结，所述磁性隧道结包括：依次层叠设置的自由层、势垒层和参考层，所述自由层与所述重金属层相邻设置，所述重金属层与所述自由层之间的相互作用为自旋轨道矩及DMI效应；A magnetic tunnel junction located on the surface of the heavy metal layer, the magnetic tunnel junction includes: a free layer, a barrier layer and a reference layer that are stacked in sequence, the free layer is arranged adjacent to the heavy metal layer, and the heavy metal layer is adjacent to the heavy metal layer. The interaction between the free layers is spin-orbit moment and DMI effect;
电极，所述电极位于所述参考层的表面；an electrode, the electrode is located on the surface of the reference layer;
其中，所述重金属层具有至少三个通电端口，包括两个输入端和一个控制端，两个所述输入端和所述控制端的状态共同决定所述重金属层电流方向，以进一步决定所述磁性隧道结的阻态信息；Wherein, the heavy metal layer has at least three power-on ports, including two input ends and one control end, and the states of the two input ends and the control end jointly determine the current direction of the heavy metal layer to further determine the magnetic properties The resistance state information of the tunnel junction;
所述电极具有一个读取端，当读取所述磁性隧道结的阻态信息时，所述读取端输入读电压。The electrode has a read terminal, and when the resistance state information of the magnetic tunnel junction is read, a read voltage is input to the read terminal.
可选地，所述磁性隧道结的磁各向异性为垂直磁各向异性。Optionally, the magnetic anisotropy of the magnetic tunnel junction is perpendicular magnetic anisotropy.
可选地，所述重金属层的截面形状为Y形，且三边等长，夹角均为120°，两个所述输入端和所述控制端分别位于Y形重金属层的三端。Optionally, the cross-sectional shape of the heavy metal layer is Y-shaped, and the three sides are of equal length, and the included angles are all 120°, and the two input ends and the control end are respectively located at three ends of the Y-shaped heavy metal layer.
可选地，当所述控制端开路，Y形重金属层电流从一个输入端流向另一个输入端时，若电流方向为顺时针，则所述磁性隧道结为低阻态；若电流方向为逆时针，则所述磁性隧道结为高阻态；Optionally, when the control terminal is open and the Y-shaped heavy metal layer current flows from one input terminal to the other input terminal, if the current direction is clockwise, the magnetic tunnel junction is in a low resistance state; if the current direction is reverse Clockwise, the magnetic tunnel junction is in a high resistance state;
当Y形重金属层电流从三端中的任意两端流向另外一端时，所述磁性隧道结的阻态发生变化；When the current of the Y-shaped heavy metal layer flows from any two ends of the three ends to the other end, the resistance state of the magnetic tunnel junction changes;
当Y形重金属层电流从三端中的任意一端流向另外两端时，所述磁性隧道结的阻态保持不变。When the current of the Y-shaped heavy metal layer flows from any one of the three terminals to the other two, the resistance state of the magnetic tunnel junction remains unchanged.
可选地，所述自由层与所述重金属层的材料组合为Co/Pt、CoFe/Pt、CoFeB/Pt、Co/W、CoFe/W、CoFeB/W、Co/Ir、Co/Tb、CoFeB/Mo、CoFeB/Cr、CoFeB/Ta中的任意一种组合。Optionally, the material combination of the free layer and the heavy metal layer is Co/Pt, CoFe/Pt, CoFeB/Pt, Co/W, CoFe/W, CoFeB/W, Co/Ir, Co/Tb, CoFeB Any combination of /Mo, CoFeB/Cr, and CoFeB/Ta.
第二方面，本发明提供一种数据选择器，包括：如第一方面提供的存算一体的磁性存储单元、第一NMOS管以及第一PMOS管，所述重金属层的控制端接地，所述重金属层的一个输入端与所述第一NMOS管的漏极连接，所述第一NMOS管的源极输入高电平信号，所述重金属层的另一个输入端与所述第一PMOS管的漏极连接，所述第一PMOS管的源极输入高电平信号，所述第一NMOS管的栅极和所述第一PMOS管的栅极分别作为数据选择器的两个输入端。In a second aspect, the present invention provides a data selector, comprising: the magnetic storage unit with integrated storage and computing as provided in the first aspect, a first NMOS transistor and a first PMOS transistor, the control terminal of the heavy metal layer is grounded, and the One input end of the heavy metal layer is connected to the drain of the first NMOS transistor, the source electrode of the first NMOS transistor is input with a high level signal, and the other input end of the heavy metal layer is connected to the drain electrode of the first PMOS transistor. The drain is connected, the source of the first PMOS transistor is input with a high level signal, and the gate of the first NMOS transistor and the gate of the first PMOS transistor are respectively used as two input ends of the data selector.
第三方面，本发明提供一种全减器，包括：如第一方面提供的存算一体的磁性存储单元以及第二NMOS管，所述重金属层的控制端与所述第二NMOS管的漏极连接，所述第二NMOS管的源极输入高电平信号，所述第二NMOS管的栅极作为全减器的控制端，所述重金属层的两个输入端作为全减器的两个输入端。In a third aspect, the present invention provides a full subtractor, comprising: the magnetic storage unit with integrated storage and computing provided in the first aspect and a second NMOS transistor, the control terminal of the heavy metal layer and the drain of the second NMOS transistor The source of the second NMOS transistor is connected to a high-level signal, the gate of the second NMOS transistor is used as the control terminal of the full subtractor, and the two input terminals of the heavy metal layer are used as the two terminals of the full subtractor. an input.
第四方面，本发明提供一种全加器，包括：如第一方面提供的存算一体的磁性存储单元、第三NMOS管以及反相器，所述重金属层的控制端与所述第三NMOS管的漏极连接，所述第三NMOS管的源极输入高电平信号，所述第三NMOS管的栅极作为全加器的控制端，所述重金属层的一个输入端与所述反相器的输出端连接，所述重金属层的另一个输入端和所述反相器的输入端作为全加器的两个输入端。In a fourth aspect, the present invention provides a full adder, comprising: a magnetic storage unit with integrated storage and computing as provided in the first aspect, a third NMOS transistor and an inverter, the control terminal of the heavy metal layer and the third The drain of the NMOS transistor is connected, the source of the third NMOS transistor is input with a high-level signal, the gate of the third NMOS transistor is used as the control terminal of the full adder, and an input terminal of the heavy metal layer is connected to the The output end of the inverter is connected, and the other input end of the heavy metal layer and the input end of the inverter serve as two input ends of the full adder.
第五方面，本发明提供一种阵列结构，包括：行列分布的多个单元，其中每个单元包括如第一方面提供的存算一体的磁性存储单元、第四NMOS管、第五NMOS管、第六NMOS管、第七NMOS管及第八NMOS管，In a fifth aspect, the present invention provides an array structure, comprising: a plurality of units distributed in rows and columns, wherein each unit includes a magnetic storage unit integrated with storage and computing as provided in the first aspect, a fourth NMOS transistor, a fifth NMOS transistor, The sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube,
所述重金属层的一个输入端与所述第四NMOS管的漏极连接，所述第四NMOS管的栅极连接至字线CWL，所述第四NMOS管的源极连接至位线RBL；One input terminal of the heavy metal layer is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the word line CWL, and the source of the fourth NMOS transistor is connected to the bit line RBL;
所述重金属层的另一个输入端与所述第五NMOS管的源极连接，所述第五NMOS管的栅极连接至字线RWL，所述第五NMOS管的漏极连接至位线CBL；The other input terminal of the heavy metal layer is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the word line RWL, and the drain of the fifth NMOS transistor is connected to the bit line CBL ;
所述重金属层的控制端与所述第六NMOS管的漏极连接，所述第六NMOS管的栅极连接至字线CWWL，所述第六NMOS管的源极与所述第七NMOS管的漏极连接，所述第七NMOS管的栅极连接至字线RWWL，所述第七NMOS管的源极接地；The control terminal of the heavy metal layer is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the word line CWWL, and the source of the sixth NMOS transistor is connected to the seventh NMOS transistor The drain of the seventh NMOS transistor is connected to the word line RWWL, and the source of the seventh NMOS transistor is grounded;
所述重金属层的读取端与所述第八NMOS管的源极连接，所述第八NMOS管的栅极连接至字线WL，所述第八NMOS管的漏极连接至源线；The read terminal of the heavy metal layer is connected to the source of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to the word line WL, and the drain of the eighth NMOS transistor is connected to the source line;
其中，字线WL用于读取磁性隧道结的阻值，字线CWL和RWL分别控制目标列和目标行上磁性存储单元的通断，字线CWWL和RWWL分别控制目标列和目标行上磁性存储单元是否接地，位线CBL和RBL分别用来进行磁性存储单元两个输入端的数据输入，且源线SL电压为高电平。Among them, the word line WL is used to read the resistance value of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on-off of the magnetic memory cells on the target column and the target row, and the word lines CWWL and RWWL respectively control the magnetic memory cells on the target column and target row. Whether the memory cell is grounded, the bit lines CBL and RBL are respectively used for data input of the two input terminals of the magnetic memory cell, and the voltage of the source line SL is at a high level.
本发明提供的一种存算一体的磁性存储单元，能够充分利用SOT-MRAM的物理特性进行存内计算，具有SOT-MRAM高速、低功耗的特点，且无需外部磁场辅助，集成度较高。应用本发明的存算一体的磁性存储单元可以实现多种算术、逻辑计算，并可进一步构建出数据选择器、全减器、全加器、2bit乘法器等算术逻辑计算器件。The magnetic storage unit provided by the present invention can make full use of the physical characteristics of SOT-MRAM to perform in-memory computing, has the characteristics of high speed and low power consumption of SOT-MRAM, does not require external magnetic field assistance, and has a high degree of integration . The magnetic storage unit with integrated storage and calculation of the present invention can realize various arithmetic and logical calculations, and can further construct arithmetic and logical calculation devices such as data selectors, full subtractors, full adders, and 2-bit multipliers.
附图说明Description of drawings
图1为本发明一实施例提供的磁性存储单元的立体视图；FIG. 1 is a perspective view of a magnetic storage unit according to an embodiment of the present invention;
图2为对应图1所示磁性存储单元的侧视图；FIG. 2 is a side view corresponding to the magnetic storage unit shown in FIG. 1;
图3为本发明一实施例提供的磁性存储单元实现不同逻辑的示意图；FIG. 3 is a schematic diagram of implementing different logics in a magnetic memory cell according to an embodiment of the present invention;
图4为本发明一实施例提供的数据选择器的示意图；4 is a schematic diagram of a data selector provided by an embodiment of the present invention;
图5为本发明一实施例提供的全减器的示意图；5 is a schematic diagram of a total subtractor provided by an embodiment of the present invention;
图6为全减器进行减法运算的流程图；Fig. 6 is the flow chart that the full subtractor carries out the subtraction operation;
图7为本发明一实施例提供的全加器的示意图；7 is a schematic diagram of a full adder provided by an embodiment of the present invention;
图8为全加器进行加法运算的流程图；Fig. 8 is the flow chart that the full adder carries out addition operation;
图9为本发明一实施例提供的阵列结构示意图；FIG. 9 is a schematic diagram of an array structure according to an embodiment of the present invention;
图10为阵列结构进行2bit乘法运算示意图；10 is a schematic diagram of an array structure performing 2bit multiplication;
图11为n-bit乘法器计算流程示意图。FIG. 11 is a schematic diagram of the calculation flow of the n-bit multiplier.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
下面结合附图，对本发明的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.
实施例一Example 1
本发明实施例提供一种存算一体的磁性存储单元，如图1和图2所示，图1为磁性存储单元的立体视图，图2为磁性存储单元的侧视图。该磁性存储单元包括：重金属层101、位于重金属层101表面的磁性隧道结(MTJ)102以及磁性隧道结表面的电极103，磁性隧道结102至少包括从下至上依次层叠设置的自由层1021、势垒层1022和参考层1023，自由层1021与重金属层101相邻设置，重金属层101与自由层1021之间的相互作用为自旋轨道矩(SOT)及Dzyaloshinskii-Moriya Interaction(DMI)效应，电极103位于参考层1023的表面。其中，重金属层101具有至少三个通电端口，包括两个输入端A、B和一个控制端S，两个输入端A、B和控制端S的状态共同决定重金属层101电流方向，以进一步决定磁性隧道结102的阻态信息；另外电极103还具有一个读取端M，当读取磁性隧道结102的阻态信息时，读取端M输入读电压Vread。An embodiment of the present invention provides a magnetic storage unit with integrated storage and computing, as shown in FIG. 1 and FIG. 2 . FIG. 1 is a perspective view of the magnetic storage unit, and FIG. 2 is a side view of the magnetic storage unit. The magnetic storage unit includes: a
进一步地，在本实施例中，磁性隧道结102的磁各向异性为垂直磁各向异性。自由层1021的材料为Co,Fe,CoFe,CoFeB中的任一种，重金属层101的材料为Pt,W,Mo,Ir,Tb,Cr,Ta中的任一种。自由层1021与重金属层101的常用组合可以是Co/Pt,CoFe/Pt,CoFeB/Pt,Co/W,CoFe/W,CoFeB/W,Co/Ir,Co/Tb,CoFeB/Mo,CoFeB/Cr,CoFeB/Ta中的任意一种组合。Further, in this embodiment, the magnetic anisotropy of the
重金属层101可以有多种实现形式，例如重金属层101的截面形状可以设计成Y形，且三边等长，夹角均为120°，两个输入端A、B和控制端S分别位于Y形重金属层的三端。需要说明的是，三个通电端口可以任意定义为输入端或者控制端。The
图1所示的磁性存储单元，是一个四端口逻辑器件，磁性隧道结的阻态信息会随着重金属层通入电流的不同发生改变。具体地，当控制端S开路，Y形重金属层电流从一个输入端流向另一个输入端时，若电流方向为顺时针(此时从A到B)，则磁性隧道结为低阻态；若电流方向为逆时针(此时从B到A)，则磁性隧道结为高阻态。若三端都有电流通过，当Y形重金属层电流从三端中的任意两端流向另外一端时，磁性隧道结的阻态发生变化，即从低阻态变为高阻态，或者从高阻态变为低阻态；当Y形重金属层电流从三端中的任意一端流向另外两端时，磁性隧道结的阻态保持不变。The magnetic memory cell shown in FIG. 1 is a four-port logic device, and the resistance state information of the magnetic tunnel junction will change with the current passing through the heavy metal layer. Specifically, when the control terminal S is open and the Y-shaped heavy metal layer current flows from one input terminal to the other input terminal, if the current direction is clockwise (from A to B at this time), the magnetic tunnel junction is in a low resistance state; if If the current direction is counterclockwise (from B to A at this time), the magnetic tunnel junction is in a high resistance state. If there are currents passing through the three terminals, when the current of the Y-shaped heavy metal layer flows from any two ends of the three terminals to the other terminal, the resistance state of the magnetic tunnel junction changes, that is, from a low resistance state to a high resistance state, or from a high resistance state. The resistance state changes to a low resistance state; when the Y-shaped heavy metal layer current flows from any one of the three terminals to the other two, the resistance state of the magnetic tunnel junction remains unchanged.
基于上述阻值变化特性，本实施例的存算一体的磁性存储单元，可以实现多种逻辑计算。先作如下定义：重金属层两个输入端A、B的值用Ai和Bi表示，电压为0.表示逻辑“0”，电压为高电平Vdd表示逻辑“1”。控制端S的电压可以为0、Vdd或者开路。磁性隧道结当前存储的数据记为X i，磁性隧道结下一个存储的数据记为X i+1，Xi以及Xi+1表示磁性隧道结的电阻状态。本实施例中，0和1分别表示磁性隧道结的低阻态和高阻态。即，Xi＝0表示磁性隧道结当前低阻态，Xi＝1表示磁性隧道结当前高阻态。Xi+1＝0表示磁性隧道结写入后低阻态，Xi+1＝1表示磁性隧道结写入后高阻态。Based on the above resistance change characteristics, the magnetic storage unit with integrated storage and calculation in this embodiment can implement various logic calculations. First, the following definitions are made: the values of the two input terminals A and B of the heavy metal layer are represented by A i and B i , the voltage is 0. It represents logic "0", and the voltage is high level Vdd represents logic "1". The voltage of the control terminal S can be 0, Vdd or open circuit. The data currently stored in the magnetic tunnel junction is denoted as X i , the next data stored in the magnetic tunnel junction is denoted as Xi +1 , and Xi and Xi +1 represent the resistance states of the magnetic tunnel junction. In this embodiment, 0 and 1 represent the low resistance state and the high resistance state of the magnetic tunnel junction, respectively. That is, X i =0 represents the current low resistance state of the magnetic tunnel junction, and X i =1 represents the current high resistance state of the magnetic tunnel junction. X i+1 =0 represents a low resistance state of the magnetic tunnel junction after writing, and X i+1 =1 represents a high resistance state of the magnetic tunnel junction after writing.
逻辑计算1：如图3中(a)所示，当重金属层的控制端S开路，Xi为0和1时，磁性存储单元分别进行实质蕴含(IMP)和逆反蕴含(RNIMP)运算，其逻辑表达式可以表示为：Logic calculation 1: As shown in (a) of Figure 3, when the control terminal S of the heavy metal layer is open, and X i is 0 and 1, the magnetic memory cell performs substantial implication (IMP) and inverse implication (RNIMP) operations, respectively. A logical expression can be expressed as:
对应的真值表如表1所示。The corresponding truth table is shown in Table 1.
表1Table 1
逻辑计算2：如图3中的(b)所示，当重金属层的控制端S为高电平Vdd时，Xi为0和1时，分别进行异或(XOR)和同或(XNOR)运算，其逻辑表达式可以表示为：Logic calculation 2: As shown in (b) of Figure 3, when the control terminal S of the heavy metal layer is at a high level Vdd, and X i is 0 and 1, the exclusive OR (XOR) and the exclusive OR (XNOR) are performed respectively. operation, its logical expression can be expressed as:
对应的真值表如表2所示。The corresponding truth table is shown in Table 2.
表2Table 2
逻辑计算3：如图3中的(c)所示，当重金属层的控制端S接地时，Xi为0和1时，分别进行与(AND)和与非(NAND)运算，其逻辑表达式可以表示为：Logic calculation 3: As shown in (c) of Figure 3, when the control terminal S of the heavy metal layer is grounded, and Xi is 0 and 1, the AND and NAND operations are performed respectively. The logical expression The formula can be expressed as:
对应的真值表如表3所示。The corresponding truth table is shown in Table 3.
表3table 3
逻辑计算4：通过固定某一输入端的输入将三元逻辑简化为二元逻辑。如图3中的(d)所示，当控制端S开路，A为高电平Vdd时，可以实现与(AND)运算，其逻辑表达式可以表示为：Logic calculation 4: Simplify ternary logic into binary logic by fixing the input of a certain input terminal. As shown in (d) in Figure 3, when the control terminal S is open and A is a high level Vdd, the AND operation can be realized, and its logical expression can be expressed as:
Xi+1＝BiXi (4)X i+1 =B i X i (4)
对应的真值表如表4所示。The corresponding truth table is shown in Table 4.
表4Table 4
逻辑计算5：通过固定某一输入端的输入将三元逻辑简化为二元逻辑。如图3中的(e)所示，当控制端S接地，B为高电平Vdd时，可以实现异或(XOR)运算，其逻辑表达式可以表示为：Logic calculation 5: Simplify ternary logic into binary logic by fixing the input of a certain input terminal. As shown in (e) in Figure 3, when the control terminal S is grounded and B is at a high level Vdd, an exclusive-or (XOR) operation can be implemented, and its logical expression can be expressed as:
对应的真值表如表5所示。The corresponding truth table is shown in Table 5.
表5table 5
本发明实施例提供的一种存算一体的磁性存储单元，能够充分利用SOT-MRAM的物理特性进行存内计算，具有SOT-MRAM高速、低功耗的特点，且无需外部磁场辅助，集成度较高。应用本发明的存算一体的磁性存储单元可以实现多种算术、逻辑计算。A magnetic storage unit with integrated storage and computing provided by the embodiment of the present invention can make full use of the physical characteristics of SOT-MRAM to perform in-memory computing, has the characteristics of high speed and low power consumption of SOT-MRAM, and does not require external magnetic field assistance. higher. The magnetic storage unit with integrated storage and calculation of the present invention can realize various arithmetic and logical calculations.
以实施例一提供的存算一体的磁性存储单元为基础，还可以构建出多种算术逻辑计算器件。以下作具体描述。Based on the magnetic storage unit with integrated storage and computing provided in the first embodiment, a variety of arithmetic and logic computing devices can also be constructed. The following is a detailed description.
实施例二
本发明实施例提供一种数据选择器，可以参考图4，该数据选择器包括实施例一提供的存算一体的磁性存储单元、NMOS管NM1以及PMOS管PM1，重金属层的控制端S接地，重金属层的一个输入端A与NM1的漏极连接，NM1的源极输入高电平信号Vdd，重金属层的另一个输入端B与PM1的漏极连接，PM1的源极输入高电平信号Vdd，NM1的栅极C和PM1的栅极D分别作为数据选择器的两个输入端，磁性隧道结的阻态信息作为数据选择器的选择信号。An embodiment of the present invention provides a data selector. Referring to FIG. 4, the data selector includes the magnetic storage unit with integrated storage and computing provided in the first embodiment, an NMOS transistor NM1, and a PMOS transistor PM1, and the control terminal S of the heavy metal layer is grounded. One input terminal A of the heavy metal layer is connected to the drain of NM1, the source of NM1 is input with a high-level signal Vdd, the other input terminal B of the heavy metal layer is connected to the drain of PM1, and the source of PM1 is input with a high-level signal Vdd , the gate C of NM1 and the gate D of PM1 are respectively used as two input terminals of the data selector, and the resistance state information of the magnetic tunnel junction is used as the selection signal of the data selector.
两个输入端的数据依然还记为Ai和Bi，该数据选择器的逻辑表达式可以表示为：The data of the two input terminals are still denoted as A i and B i , and the logical expression of the data selector can be expressed as:
对应的真值表如表6所示。The corresponding truth table is shown in Table 6.
表6Table 6
实施例三Embodiment 3
本发明实施例提供一种全减器，可以参考图5，该全减器包括实施例一提供的存算一体的磁性存储单元以及NMOS管NM2，重金属层的控制端S与NM2的漏极连接，NM2的源极输入高电平信号Vdd，NM2的栅极作为全减器的控制端S1，重金属层的两个输入端A、B作为全减器的两个输入端。An embodiment of the present invention provides a full subtractor. Referring to FIG. 5, the full subtractor includes the magnetic storage unit with integrated storage and computing provided in the first embodiment and an NMOS transistor NM2. The control terminal S of the heavy metal layer is connected to the drain of NM2. , the source of NM2 inputs a high-level signal Vdd, the gate of NM2 is used as the control terminal S1 of the full subtractor, and the two input terminals A and B of the heavy metal layer are used as the two input terminals of the full subtractor.
控制端S1的0、1取值分别对应式(1)和式(2)的运算，如果A、B连续输入数据并读取MTJ的阻态X，其第i次操作的逻辑如下所示：The values of 0 and 1 of the control terminal S1 correspond to the operations of equations (1) and (2) respectively. If A and B continuously input data and read the resistance state X of the MTJ, the logic of the i-th operation is as follows:
使用该逻辑进行减法运算的流程如图6所示，是一种串行减法器。其中借位信息Ci会被存储在MTJ中，而差Di会在计算中被读取。The flow of the subtraction operation using this logic is shown in Figure 6, which is a serial subtractor. The borrow information Ci will be stored in the MTJ, and the difference Di will be read in the calculation.
实施例四
本发明实施例提供一种全加器，可以参考图7，该全加器包括实施例一提供的存算一体的磁性存储单元、NMOS管NM3以及反相器INV，重金属层的控制端S与NM3的漏极连接，NM3的源极输入高电平信号Vdd，NM3的栅极作为全加器的控制端S2，重金属层的输入端B与反相器INV的输出端连接，重金属层的另一个输入端A和反相器INV的输入端B2作为全加器的两个输入端。An embodiment of the present invention provides a full adder. Referring to FIG. 7 , the full adder includes the magnetic storage unit with integrated storage and calculation provided in the first embodiment, an NMOS transistor NM3, and an inverter INV. The control terminal S of the heavy metal layer is connected to The drain of NM3 is connected, the source of NM3 is input with a high-level signal Vdd, the gate of NM3 is used as the control terminal S2 of the full adder, the input terminal B of the heavy metal layer is connected to the output terminal of the inverter INV, and the other side of the heavy metal layer is connected. One input terminal A and the input terminal B2 of the inverter INV serve as two input terminals of the full adder.
控制端S2的0、1取值分别对应式(1)和式(2)的运算，如果A、B2连续输入数据并读取MTJ的阻态X，其第i次操作的逻辑如下所示：The values of 0 and 1 of the control terminal S2 correspond to the operations of equations (1) and (2) respectively. If A and B2 continuously input data and read the resistance state X of the MTJ, the logic of the i-th operation is as follows:
使用该逻辑进行加法运算的流程如图8所示，是一种串行加法器。其中进位信息Ci会被存储在MTJ中，而和Si会在计算中被读取。The flow of adding operation using this logic is shown in Figure 8, which is a serial adder. The carry information Ci will be stored in the MTJ, and the sum Si will be read in the calculation.
实施例五Embodiment 5
本发明实施例提供一种阵列结构，如图9所示，该阵列结构包括行列分布的多个单元，其中每个单元进一步包括实施例一提供的存算一体的磁性存储单元和5个NMOS管，记为NM4、NM5、NM6、NM7和NM8，重金属层的一个输入端A与NM4的漏极连接，NM4的栅极连接至字线CWL，NM4的源极连接至位线RBL；重金属层的另一个输入端B与NM5的源极连接，NM5的栅极连接至字线RWL，NM5的漏极连接至位线CBL；重金属层的控制端S与NM6的漏极连接，NM6的栅极连接至字线CWWL，NM6的源极与NM7的漏极连接，NM7的栅极连接至字线RWWL，NM7的源极接地；重金属层的读取端M与NM8的源极连接，NM8的栅极连接至字线WL，NM8的漏极连接至源线SL；An embodiment of the present invention provides an array structure. As shown in FIG. 9 , the array structure includes a plurality of units distributed in rows and columns, wherein each unit further includes the magnetic storage unit provided in the first embodiment and five NMOS transistors. , denoted as NM4, NM5, NM6, NM7 and NM8, one input terminal A of the heavy metal layer is connected to the drain of NM4, the gate of NM4 is connected to the word line CWL, and the source of NM4 is connected to the bit line RBL; The other input terminal B is connected to the source of NM5, the gate of NM5 is connected to the word line RWL, the drain of NM5 is connected to the bit line CBL; the control terminal S of the heavy metal layer is connected to the drain of NM6, and the gate of NM6 is connected to To the word line CWWL, the source of NM6 is connected to the drain of NM7, the gate of NM7 is connected to the word line RWWL, and the source of NM7 is grounded; the read end M of the heavy metal layer is connected to the source of NM8, and the gate of NM8 Connected to the word line WL, the drain of NM8 is connected to the source line SL;
其中，字线WL用于读取磁性隧道结的阻值，字线CWL和RWL分别控制目标列和目标行上磁性存储单元的通断，字线CWWL和RWWL分别控制目标列和目标行上磁性存储单元是否接地，位线CBL和RBL分别用来进行磁性存储单元两个输入端的数据输入，且源线SL电压为高电平信号Vdd。Among them, the word line WL is used to read the resistance value of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on-off of the magnetic memory cells on the target column and the target row, and the word lines CWWL and RWWL respectively control the magnetic memory cells on the target column and target row. Whether the memory cell is grounded or not, the bit lines CBL and RBL are respectively used for data input of the two input terminals of the magnetic memory cell, and the voltage of the source line SL is the high-level signal Vdd.
基于图9的阵列结构，可以实现2-bit的乘法运算。2-bit的乘法运算计算流程可以参考表7，可以通过包括初始化在内的三步流程计算2-bit乘法，其逻辑关系可以使用与(AND)和异或(XOR)运算表示为：Based on the array structure of FIG. 9, a 2-bit multiplication operation can be realized. For the calculation process of 2-bit multiplication, please refer to Table 7. The 2-bit multiplication can be calculated through a three-step process including initialization. The logical relationship can be expressed as: AND (AND) and XOR (XOR) operations:
表7Table 7
进行阵列计算时，需要先进行初始化，将所有X置为0。如图10所示，对2×2阵列进行2-bit乘法运算时，除了用于读取的字线，其余字线首先全部为高电平，四条行列位线分别输入a1、b1、a2、b2，则所有MTJ会进行公式(3)的与/异或运算，计算a1、b1、a2、b2两两乘积；然后第一条字线CWWL置低电平，四条行列位线分别输入1、1、a1b2(从运算后MTJ中读取)、a2b1(从运算后的MTJ中读取)，则四个MTJ分别进行不变、公式(5)、公式(3)、公式(4)的运算，计算结果为公式(9)中的乘积值，并存于MTJ中。When performing an array calculation, you need to initialize first and set all X to 0. As shown in Figure 10, when a 2-bit multiplication operation is performed on a 2×2 array, except for the word line used for reading, all the other word lines are first at high level, and the four row and column bit lines are input a1, b1, a2, b2, then all MTJs will perform the AND/XOR operation of formula (3) to calculate the product of a1, b1, a2, and b2; then the first word line CWWL is set to low level, and the four row and column bit lines are respectively
进一步地，基于2-bit乘法器和n-bit加法器，基于Vedic算法还可以实现n-bit乘法器。计算流程如图11所示。Further, based on a 2-bit multiplier and an n-bit adder, an n-bit multiplier can also be implemented based on the Vedic algorithm. The calculation process is shown in Figure 11.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
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