CN115116507A

CN115116507A - Integrated storage magnetic memory unit

Info

Publication number: CN115116507A
Application number: CN202110284592.4A
Authority: CN
Inventors: 石以诺; 迟克群; 李州; 冯向; 孟皓
Original assignee: Hikstor Technology Co Ltd
Current assignee: Hikstor Technology Co Ltd
Priority date: 2021-03-17
Filing date: 2021-03-17
Publication date: 2022-09-27

Abstract

The present invention provides an integrated magnetic memory cell, comprising: heavy metal layer, be located the electrode on the magnetic tunnel junction and the magnetic tunnel junction surface on heavy metal layer surface, the magnetic tunnel junction includes: the free layer, the barrier layer and the reference layer are sequentially stacked, the free layer is adjacent to the heavy metal layer, and the interaction between the heavy metal layer and the free layer is spin orbit torque and DMI effect; the heavy metal layer is provided with at least three power-on ports, the power-on ports comprise two input ends and a control end, and the states of the two input ends and the control end jointly determine the current direction of the heavy metal layer so as to further determine the resistance state information of the magnetic tunnel junction. The invention can fully utilize the physical characteristics of the SOT-MRAM to carry out the memory calculation.

Description

Integrated storage magnetic memory unit

Technical Field

The invention relates to the technical field of magnetic memories, in particular to a magnetic storage unit integrating storage and calculation.

Background

In recent years, with the development of big data and AI, the demand of related applications for computing power has also increased. However, the traditional von neumann architecture computer is separated from the computer, and the frequent calling and storage of data generates a large amount of power consumption, which has become a bottleneck of the intelligent computation.

The storage-computation-integrated architecture is considered to be an effective means for solving the problems of a storage wall and a memory access power consumption wall in the existing Von Neumann architecture. In the storage and computation integrated architecture, the storage unit directly has logic computation capability, and can effectively eliminate the delay and power consumption of data movement.

Spin-orbit torque magnetic memory (SOT-MRAM) has the characteristics of high writing speed, low power consumption, high integration, programmable logic, compatibility with CMOS and the like, and is very suitable for designing and storing an integrated computer. However, there is currently no practical way to implement a fully integrated magnetic memory cell.

Disclosure of Invention

To solve the above problems, the present invention provides an integrated storage magnetic memory cell capable of performing an in-memory calculation by making full use of the physical characteristics of an SOT-MRAM.

In a first aspect, the present invention provides a unified magnetic memory cell, comprising:

a heavy metal layer;

a magnetic tunnel junction located on a surface of the heavy metal layer, the magnetic tunnel junction comprising: the free layer, the barrier layer and the reference layer are sequentially stacked, the free layer is adjacent to the heavy metal layer, and the interaction between the heavy metal layer and the free layer is spin orbit torque and DMI effect;

an electrode located on a surface of the reference layer;

the heavy metal layer is provided with at least three power-on ports, the power-on ports comprise two input ends and a control end, and the states of the two input ends and the control end jointly determine the current direction of the heavy metal layer so as to further determine the resistance state information of the magnetic tunnel junction;

the electrode has a read terminal to which a read voltage is input when reading the resistance state information of the magnetic tunnel junction.

Optionally, the magnetic anisotropy of the magnetic tunnel junction is a perpendicular magnetic anisotropy.

Optionally, the cross-sectional shape of the heavy metal layer is Y-shaped, three sides of the heavy metal layer are equal in length, included angles of the two heavy metal layers are 120 °, and the two input ends and the control end are respectively located at three ends of the Y-shaped heavy metal layer.

Optionally, when the control terminal is open-circuited and a current of the Y-shaped heavy metal layer flows from one input terminal to the other input terminal, if the current direction is clockwise, the magnetic tunnel junction is in a low-resistance state; if the current direction is anticlockwise, the magnetic tunnel junction is in a high-resistance state;

when the current of the Y-shaped heavy metal layer flows from any two ends of the three ends to the other end, the resistance state of the magnetic tunnel junction is changed;

when the current of the Y-shaped heavy metal layer flows from any one of the three ends to the other two ends, the resistance state of the magnetic tunnel junction is kept unchanged.

Optionally, the material combination of the free layer and the heavy metal layer is any one combination of Co/Pt, CoFe/Pt, CoFeB/Pt, Co/W, CoFe/W, CoFeB/W, Co/Ir, Co/Tb, CoFeB/Mo, CoFeB/Cr and CoFeB/Ta.

In a second aspect, the present invention provides a data selector comprising: in the integrated magnetic memory unit, the first NMOS transistor, and the first PMOS transistor provided in the first aspect, the control end of the heavy metal layer is grounded, one input end of the heavy metal layer is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor inputs a high level signal, the other input end of the heavy metal layer is connected to the drain of the first PMOS transistor, the source of the first PMOS transistor inputs a high level signal, and the gate of the first NMOS transistor and the gate of the first PMOS transistor are respectively used as two input ends of a data selector.

In a third aspect, the present invention provides a full reducer comprising: in the integrated magnetic storage unit and the second NMOS transistor provided in the first aspect, the control end of the heavy metal layer is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor inputs a high level signal, the gate of the second NMOS transistor serves as the control end of the full-subtractor, and the two input ends of the heavy metal layer serve as the two input ends of the full-subtractor.

In a fourth aspect, the present invention provides a full adder, comprising: the integrated magnetic memory unit provided by the first aspect, the third NMOS transistor, and the phase inverter, wherein a control end of the heavy metal layer is connected to a drain of the third NMOS transistor, a source of the third NMOS transistor inputs a high level signal, a gate of the third NMOS transistor serves as a control end of a full adder, one input end of the heavy metal layer is connected to an output end of the phase inverter, and another input end of the heavy metal layer and an input end of the phase inverter serve as two input ends of the full adder.

In a fifth aspect, the present invention provides an array structure comprising: a plurality of cells arranged in rows and columns, wherein each cell comprises a unified magnetic memory cell as provided in the first aspect, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor,

one input end of the heavy metal layer is connected with a drain electrode of the fourth NMOS tube, a grid electrode of the fourth NMOS tube is connected to a word line CWL, and a source electrode of the fourth NMOS tube is connected to a bit line RBL;

the other input end of the heavy metal layer is connected with a source electrode of a fifth NMOS tube, a grid electrode of the fifth NMOS tube is connected to a word line RWL, and a drain electrode of the fifth NMOS tube is connected to a bit line CBL;

the control end of the heavy metal layer is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube is connected to a word line CWL, the source electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the seventh NMOS tube is connected to a word line RWL, and the source electrode of the seventh NMOS tube is grounded;

the reading end of the heavy metal layer is connected with the source electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is connected to a word line WL, and the drain electrode of the eighth NMOS tube is connected to a source line;

the word line WL is used for reading the resistance of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on-off of the magnetic memory cells in the target column and the target row, the word lines CWWL and RWWL respectively control whether the magnetic memory cells in the target column and the target row are grounded, the bit lines CBL and RBL are respectively used for data input of two input ends of the magnetic memory cells, and the source line SL voltage is high level.

The magnetic storage unit integrating storage and calculation can fully utilize the physical characteristics of the SOT-MRAM to carry out the storage calculation, has the characteristics of high speed and low power consumption of the SOT-MRAM, does not need external magnetic field assistance, and has higher integration level. The magnetic memory unit integrating storage and calculation can realize various arithmetic and logic calculations, and can further construct arithmetic and logic calculation devices such as a data selector, a full subtracter, a full adder, a 2bit multiplier and the like.

Drawings

FIG. 1 is a perspective view of a magnetic memory cell according to one embodiment of the present invention;

FIG. 2 is a side view of a magnetic memory cell corresponding to that shown in FIG. 1;

FIG. 3 is a diagram illustrating various logic implemented in a magnetic memory cell according to one embodiment of the present invention;

FIG. 4 is a diagram illustrating a data selector according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a full subtractor according to an embodiment of the present invention;

FIG. 6 is a flow chart of a subtraction operation performed by a full subtractor;

FIG. 7 is a schematic diagram of a full adder according to an embodiment of the present invention;

FIG. 8 is a flow chart of a full adder performing an addition operation;

FIG. 9 is a schematic diagram of an array structure according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a 2-bit multiplication operation performed on an array structure;

FIG. 11 is a schematic diagram of a calculation flow of an n-bit multiplier.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.

Example one

An embodiment of the present invention provides a magnetic memory cell with integrated storage, as shown in fig. 1 and fig. 2, fig. 1 is a perspective view of the magnetic memory cell, and fig. 2 is a side view of the magnetic memory cell. The magnetic storage cell includes: the Magnetic Tunnel Junction (MTJ) structure comprises a heavy metal layer 101, a Magnetic Tunnel Junction (MTJ)102 located on the surface of the heavy metal layer 101, and an electrode 103 located on the surface of the magnetic tunnel junction, wherein the magnetic tunnel junction 102 at least comprises a free layer 1021, a barrier layer 1022, and a reference layer 1023 which are sequentially stacked from bottom to top, the free layer 1021 and the heavy metal layer 101 are arranged adjacently, the Interaction between the heavy metal layer 101 and the free layer 1021 is Spin Orbit Torque (SOT) and Dzyaloshinski-Moriya Interaction (DMI) effect, and the electrode 103 is located on the surface of the reference layer 1023. The heavy metal layer 101 has at least three power-on ports, including two input terminals A, B and a control terminal S, and the states of the two input terminals A, B and the control terminal S together determine the current direction of the heavy metal layer 101, so as to further determine the resistance state information of the magnetic tunnel junction 102; the electrode 103 further has a read terminal M to which a read voltage Vread is inputted when reading the resistance state information of the magnetic tunnel junction 102.

Further, in the present embodiment, the magnetic anisotropy of the magnetic tunnel junction 102 is perpendicular magnetic anisotropy. The material of the free layer 1021 is any one of Co, Fe, CoFe and CoFeB, and the material of the heavy metal layer 101 is any one of Pt, W, Mo, Ir, Tb, Cr and Ta. A common combination of free layer 1021 and heavy metal layer 101 may be any one of Co/Pt, CoFe/Pt, CoFeB/Pt, Co/W, CoFe/W, CoFeB/W, Co/Ir, Co/Tb, CoFeB/Mo, CoFeB/Cr, CoFeB/Ta.

The heavy metal layer 101 may have various implementations, for example, the cross-sectional shape of the heavy metal layer 101 may be designed to be Y-shaped, three sides of the heavy metal layer are equal in length, the included angles are all 120 °, and the two input terminals A, B and the control terminal S are respectively located at three ends of the Y-shaped heavy metal layer. It should be noted that the three power-on ports can be arbitrarily defined as input terminals or control terminals.

The magnetic memory cell shown in fig. 1 is a four-port logic device, and the resistance state information of the magnetic tunnel junction changes with the current passing through the heavy metal layer. Specifically, when the control terminal S is open-circuited and the Y-shaped heavy metal layer current flows from one input terminal to the other input terminal, if the current direction is clockwise (from a to B at this time), the magnetic tunnel junction is in a low resistance state; if the current direction is counter-clockwise (from B to A at this time), the magnetic tunnel junction is in a high resistance state. If the current passes through the three ends, when the current of the Y-shaped heavy metal layer flows from any two ends of the three ends to the other end, the resistance state of the magnetic tunnel junction is changed, namely the resistance state is changed from the low resistance state to the high resistance state, or the resistance state is changed from the high resistance state to the low resistance state; when the current of the Y-shaped heavy metal layer flows from any one of the three ends to the other two ends, the resistance state of the magnetic tunnel junction is kept unchanged.

Based on the resistance variation characteristics, the integrated magnetic memory cell of the present embodiment can realize various logic calculations. The following definitions are made: the values of the two inputs A, B of the heavy metal layer are A _i And B _i The voltage is 0, indicating a logic "0", and the voltage is high Vdd, indicating a logic "1". The voltage at the control terminal S may be 0, Vdd, or open. The currently stored data of the magnetic tunnel junction is marked as X _i The next stored data of the magnetic tunnel junction is denoted as X _i+1 ，X _i And X _i+1 Representing the resistance state of the magnetic tunnel junction. In this embodiment, 0 and 1 represent the low resistance state and the high resistance state of the magnetic tunnel junction, respectively. I.e. X _i 0 denotes the current low resistance state of the magnetic tunnel junction, X _i 1 denotes the current high resistance state of the magnetic tunnel junction. X _i+1 0 denotes the low resistance state after magnetic tunnel junction writing, X _i+1 1 represents the high resistance state after magnetic tunnel junction writing.

Logic calculation 1: as shown in FIG. 3 (a), when the control terminal S of the heavy metal layer is open, X _i For 0 and 1, the magnetic storage unit performs the substantive Implication (IMP) and reverse implication (rnip) operations respectively, and the logical expression thereof can be expressed as:

the corresponding truth table is shown in table 1.

TABLE 1

Logic calculation 2: when the control terminal S of the heavy metal layer is at a high level Vdd, X is set as shown in FIG. 3 (b) _i For 0 and 1, exclusive or (XOR) and exclusive nor (XNOR) operations are performed, respectively, and the logical expression thereof can be expressed as:

the corresponding truth table is shown in table 2.

TABLE 2

Logic calculation 3: when the control terminal S of the heavy metal layer is grounded, X is connected to (c) in FIG. 3 _i At 0 AND 1, AND (AND) AND not (NAND) operations are performed, respectively, AND the logical expression thereof can be expressed as:

the corresponding truth table is shown in table 3.

TABLE 3

Logic calculation 4: the ternary logic is simplified into binary logic by fixing the input of one input end. As shown in (d) of fig. 3, when the control terminal S is open AND a is at the high level Vdd, AND (AND) operation can be implemented, AND its logical expression can be expressed as:

X _i+1 ＝B _i X _i (4)

the corresponding truth table is shown in table 4.

TABLE 4

X _i	B _i	X _i+1
			0	0	0
0	1	0
			1	0	0
1	1	1

Logic calculation 5: the ternary logic is simplified into binary logic by fixing the input of one input end. As shown in (e) of fig. 3, when the control terminal S is grounded and B is at a high level Vdd, an exclusive or (XOR) operation can be implemented, and its logical expression can be expressed as:

the corresponding truth table is shown in table 5.

TABLE 5

X _i	A _i	X _i+1
			0	0	0
0	1	1
			1	0	1
1	1	0

The magnetic storage unit integrating storage and calculation can fully utilize the physical characteristics of the SOT-MRAM to carry out the storage calculation, has the characteristics of high speed and low power consumption of the SOT-MRAM, does not need external magnetic field assistance, and has higher integration level. The magnetic storage unit integrating the storage and the calculation can realize various arithmetic and logic calculations.

Various arithmetic logic computing devices can be constructed on the basis of the magnetic storage unit for storing the computer in one embodiment. As described in detail below.

Example two

An embodiment of the present invention provides a data selector, which may refer to fig. 4, and the data selector includes an embodiment of the present invention, in which the integrated magnetic memory cell, an NMOS transistor NM1, and a PMOS transistor PM1 are provided, a control terminal S of the heavy metal layer is grounded, one input terminal a of the heavy metal layer is connected to a drain of NM1, a source of the NM1 inputs a high level signal Vdd, another input terminal B of the heavy metal layer is connected to a drain of PM1, a source of the PM1 inputs the high level signal Vdd, a gate C of NM1 and a gate D of PM1 are respectively used as two input terminals of the data selector, and resistance state information of the magnetic tunnel junction is used as a selection signal of the data selector.

The data of the two input ends are still marked as A _i And B _i The logical expression of the data selector can be expressed as:

the corresponding truth table is shown in table 6.

TABLE 6

EXAMPLE III

Referring to fig. 5, an embodiment of the present invention provides a full-subtractor, which includes the magnetic memory cell and an NMOS transistor NM2 integrated in one embodiment, a control terminal S of a heavy metal layer is connected to a drain of an NM2, a source of the NM2 inputs a high-level signal Vdd, a gate of the NM2 serves as a control terminal S1 of the full-subtractor, and two input terminals A, B of the heavy metal layer serve as two input terminals of the full-subtractor.

The values of 0 and 1 of the control terminal S1 correspond to the operations of the equations (1) and (2), respectively, and if A, B continuously inputs data and reads the resistance state X of the MTJ, the logic of the i-th operation is as follows:

the flow of subtraction using this logic is a serial subtractor as shown in fig. 6. Wherein the borrow information Ci is stored in the MTJ and the difference Di is read in the calculation.

Example four

Referring to fig. 7, the full adder according to an embodiment of the present invention includes the magnetic memory cell, an NMOS transistor NM3, and an inverter INV integrated together, where a control terminal S of a heavy metal layer is connected to a drain of the NM3, a source of the NM3 inputs a high level signal Vdd, a gate of the NM3 serves as a control terminal S2 of the full adder, an input terminal B of the heavy metal layer is connected to an output terminal of the inverter INV, and another input terminal a of the heavy metal layer and an input terminal B2 of the inverter INV serve as two input terminals of the full adder.

The values of 0 and 1 of the control terminal S2 correspond to the operations of the equations (1) and (2), respectively, and if A, B2 continuously inputs data and reads the resistance state X of the MTJ, the logic of the i-th operation is as follows:

the flow of addition using this logic is a serial adder as shown in fig. 8. Where carry information Ci is stored in the MTJ and sum Si is read in the calculation.

EXAMPLE five

An embodiment of the present invention provides an array structure, as shown in fig. 9, the array structure includes a plurality of cells arranged in rows and columns, wherein each cell further includes a magnetic memory cell and 5 NMOS transistors, denoted as NM4, NM5, NM6, NM7 and NM8, one input end a of the heavy metal layer is connected to the drain of NM4, the gate of NM4 is connected to the word line CWL, and the source of NM4 is connected to the bit line RBL; the other input terminal B of the heavy metal layer is connected to the source of NM5, the gate of NM5 is connected to word line RWL, and the drain of NM5 is connected to bit line CBL; the control end S of the heavy metal layer is connected with the drain of NM6, the gate of NM6 is connected to word line CWL, the source of NM6 is connected with the drain of NM7, the gate of NM7 is connected to word line RWL, and the source of NM7 is grounded; the reading end M of the heavy metal layer is connected with the source of NM8, the gate of NM8 is connected to a word line WL, and the drain of NM8 is connected to a source line SL;

the word line WL is used for reading the resistance of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on-off of the magnetic memory cells in the target column and the target row, the word lines CWWL and RWWL respectively control whether the magnetic memory cells in the target column and the target row are grounded, the bit lines CBL and RBL are respectively used for data input of two input ends of the magnetic memory cells, and the source line SL is a high-level signal Vdd.

Based on the array structure of FIG. 9, a 2-bit multiplication operation can be implemented. The 2-bit multiplication calculation process can refer to table 7, AND the 2-bit multiplication can be calculated through a three-step process including initialization, AND the logical relationship can be expressed as the sum (AND) AND exclusive or (XOR):

TABLE 7

When array calculation is performed, initialization needs to be performed first, and all xs are set to 0. As shown in FIG. 10, when 2-bit multiplication is performed on a2 × 2 array, all word lines except the word line for reading are high, and the four row and column bit lines are respectively input with a1, b1, a2 and b2, all MTJs will perform AND/XOR operation of formula (3) to calculate the product of a1, b1, a2 and b 2; then, the first word line CWWL is set low, and 1, a1b2 (read from the MTJ after operation), and a2b1 (read from the MTJ after operation) are input to the four row and column bit lines, respectively, so that the four MTJs perform the operations of the invariant, equation (5), equation (3), and equation (4), and the calculation result is the product value in equation (9) and is stored in the MTJ.

Furthermore, based on a 2-bit multiplier and an n-bit adder, an n-bit multiplier can be realized based on a Vedic algorithm. The calculation flow is shown in fig. 11.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A unified magnetic memory cell, comprising:

a heavy metal layer;

an electrode located on a surface of the reference layer;

2. The integrated magnetic memory cell of claim 1, wherein the magnetic anisotropy of the magnetic tunnel junction is a perpendicular magnetic anisotropy.

3. The integrated magnetic memory cell of claim 2, wherein the cross-sectional shape of the heavy metal layer is Y-shaped, three sides of the heavy metal layer are equally long, the included angles are 120 °, and the two input terminals and the control terminal are located at three ends of the Y-shaped heavy metal layer.

4. The monolithic magnetic memory cell of claim 3,

when the control end is open-circuited and the current of the Y-shaped heavy metal layer flows from one input end to the other input end, if the current direction is clockwise, the magnetic tunnel junction is in a low-resistance state; if the current direction is anticlockwise, the magnetic tunnel junction is in a high-resistance state;

5. The monolithic magnetic memory cell of claim 1 wherein the material combination of the free layer and the heavy metal layer is any one of Co/Pt, CoFe/Pt, CoFeB/Pt, Co/W, CoFe/W, CoFeB/W, Co/Ir, Co/Tb, CoFeB/Mo, CoFeB/Cr, and CoFeB/Ta.

6. A data selector, comprising: the integrated magnetic memory unit according to any one of claims 1 to 5, a first NMOS transistor and a first PMOS transistor, wherein a control terminal of the heavy metal layer is grounded, one input terminal of the heavy metal layer is connected to a drain of the first NMOS transistor, a source of the first NMOS transistor inputs a high level signal, another input terminal of the heavy metal layer is connected to a drain of the first PMOS transistor, a source of the first PMOS transistor inputs a high level signal, and a gate of the first NMOS transistor and a gate of the first PMOS transistor respectively serve as two input terminals of a data selector.

7. A full reducer, comprising: the integrated magnetic memory unit according to any of claims 1 to 5, and a second NMOS transistor, wherein a control terminal of the heavy metal layer is connected to a drain of the second NMOS transistor, a source of the second NMOS transistor inputs a high level signal, a gate of the second NMOS transistor serves as a control terminal of a full-subtractor, and two input terminals of the heavy metal layer serve as two input terminals of the full-subtractor.

8. A full adder, comprising: the integrated magnetic memory unit of any one of claims 1-5, a third NMOS transistor and an inverter, wherein a control terminal of the heavy metal layer is connected to a drain of the third NMOS transistor, a source of the third NMOS transistor inputs a high level signal, a gate of the third NMOS transistor serves as a control terminal of a full adder, one input terminal of the heavy metal layer is connected to an output terminal of the inverter, and the other input terminal of the heavy metal layer and an input terminal of the inverter serve as two input terminals of the full adder.

9. An array structure, comprising: a plurality of cells arranged in rows and columns, wherein each cell comprises a unified magnetic memory cell of any of claims 1-5, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor,

the reading end of the heavy metal layer is connected with the source electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is connected to a word line WL, and the drain electrode of the eighth NMOS tube is connected to the source line;