CN115115041A - Improved electronic synapse circuit and neural network based on ferroelectric field effect transistor - Google Patents

Improved electronic synapse circuit and neural network based on ferroelectric field effect transistor Download PDF

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CN115115041A
CN115115041A CN202210340931.0A CN202210340931A CN115115041A CN 115115041 A CN115115041 A CN 115115041A CN 202210340931 A CN202210340931 A CN 202210340931A CN 115115041 A CN115115041 A CN 115115041A
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receive
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张立宁
刘保良
陈旭辉
彭宝康
黄如
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Peking University Shenzhen Graduate School
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Abstract

A neural network circuit comprising a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of said electronic synapse circuits is configured to receive input and control signals from one pre-synaptic neuron circuit and to receive feedback signals of one post-synaptic neuron circuit; the electronic synapse circuit at least comprises a switch unit, an input unit and a weight calculation unit. The application also relates to an electronic system comprising a neural network circuit as described above and to an electronic device.

Description

Improved electronic synapse circuit based on ferroelectric field effect transistor and neural network
Technical Field
The present disclosure relates to the field of neural network circuit design, and more particularly, to an electronic synapse circuit and a neural network based on ferroelectric field effect transistors.
Background
With the rapid development of information technology industries such as artificial intelligence and big data, the requirements on the processing speed and performance of computers in social production and daily life of people are higher and higher. The amount of data that a computer needs to process increases exponentially, which puts unprecedented pressure on both data storage and computation. The most common computer architecture at present is the traditional von neumann architecture, which has the characteristics of separate storage and computation, and data needs to be frequently migrated between a storage unit and a computing unit, which not only greatly reduces the computing speed, but also greatly increases the computing power consumption.
In order to solve the problem of von Neumann architecture, a neural morphology calculation architecture method is provided based on bionics, and the neural science theory modeling is completed by simulating the connection mode of neurons and synapses in the brain, so that the complex calculation problem that high-speed processing cannot be performed in the traditional architecture is solved. The LIF neuron model is one of the most basic models commonly used in neuromorphic computational architectures, and its essence is to abstract neurons into capacitances, converting the way they communicate into action potentials and impulses. In the LIF neuron model, the electric potential of the input electrical signal of the neuron and the stability of the final output pulse are one of the cores that can improve the stability and processing speed of the neuron model.
As an emerging computational paradigm, if the behavior of neurons or synapses is simulated from the physical layer by a hardware circuit, it is expected that a neuromorphic computation with low power consumption and high computational performance can be realized. Therefore, selecting a reasonable calculation method and designing and building a hardware circuit are also important problems for realizing the calculation of the neuromorphy.
Disclosure of Invention
To solve the technical problems in the prior art, the present application proposes a neural network comprising a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from one pre-synaptic neuron circuit and to receive feedback signals of one post-synaptic neuron circuit; wherein the electronic synaptic electrical circuit comprises at least a switching unit, coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synaptic electrical circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit; an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive an input signal from the pre-synaptic neuron circuit under control of first and second feedback signals from the post-synaptic neuron circuit; a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the input signal and the second feedback signal from the input unit to update a channel resistance of the ferroelectric transistor.
In particular, the post-synaptic neuron circuit comprises a comparator having a positive input coupled to the switching unit of the electronic synapse circuit, a negative input configured to receive a preset constant signal, and an output coupled to the input unit of the electronic synapse circuit; a resistor coupled between a positive input of the comparator and a power supply; a capacitor coupled between a positive input of the comparator and ground; when the switching unit connects the post-synaptic neuron circuit and the electronic synapse circuit, and the ferroelectric transistor is turned on, a voltage at a positive input terminal of the comparator decreases, and when the voltage decreases below the predetermined constant signal, the comparator is configured to output the first and second feedback signals.
In particular, the switching unit comprises a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the positive input of the comparator, and a second electrode coupled to the first electrode of the mosfet.
In particular, the input cell includes a second transistor having a control electrode configured to receive the first feedback signal, a first electrode configured to receive the input signal, and a second electrode coupled to the control electrode of the ferroelectric transistor; a third transistor of a type complementary to the second transistor having a control electrode configured to receive the first feedback signal, a first electrode coupled to ground, and a second electrode coupled to the control electrode of the ferroelectric transistor; a fourth transistor of the same type as the second transistor having a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.
In particular, a control electrode of the ferroelectric transistor is configured to receive the input signal, and a second electrode of the ferroelectric transistor is configured to receive the second feedback signal; the control signal and the input signal have the same period, the effective level of the input signal is gradually reduced from a first preset amplitude value in the first half of the effective level pulse time, the effective level of the input signal is gradually reduced from a second preset amplitude value in the second half of the effective level pulse time, and the second preset amplitude value is larger than the first preset amplitude value.
In particular, the amplitude of the effective level of the first feedback signal is greater than the second preset amplitude.
In particular, the effective level amplitude of the second feedback signal is greater than the first preset amplitude and smaller than the second preset amplitude.
An electronic synaptic electrical circuit configured to receive input and control signals from a pre-synaptic neuron circuit and to receive a feedback signal from a post-synaptic neuron circuit; wherein the electronic synaptic electrical circuit comprises at least a switching unit, coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synaptic electrical circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit; an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive an input signal from the pre-synaptic neuron circuit under control of first and second feedback signals from the post-synaptic neuron circuit; a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the input signal and the second feedback signal from the input unit to update a channel resistance of the ferroelectric transistor.
In particular, the switching unit of the electronic synapse circuit comprises a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the input of the post-synaptic neuron, and a second electrode coupled to the first electrode of the ferroelectric field effect transistor.
In particular, the input cell of the electronic synapse circuit comprises a second transistor having a control electrode configured to receive the first feedback signal, a first electrode configured to receive the input signal, and a second electrode coupled to the control electrode of the ferroelectric transistor; a third transistor of a type complementary to the second transistor, having a control electrode configured to receive the first feedback signal, having a first electrode coupled to ground, and a second electrode coupled to the control electrode of the ferroelectric transistor; a fourth transistor of the same type as the second transistor having a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.
In particular, a control electrode of the ferroelectric transistor in the electronic synapse circuit as described above is configured to receive the input signal, and a second electrode of the ferroelectric transistor is configured to receive the second feedback signal; the control signal and the second input signal have the same period; the effective level of the input signal is gradually reduced from a first preset amplitude value in the first half of the effective level pulse time, and the effective level of the first input signal is gradually reduced from a second preset amplitude value in the second half of the effective level pulse time, wherein the second preset amplitude value is larger than the first preset amplitude value.
In particular, the amplitude of the active level of the first feedback signal in the electronic synapse circuit is larger than the second predetermined amplitude.
In particular, the amplitude of the active level of the second feedback signal in the electronic synapse circuit is greater than the first predetermined amplitude and less than the second predetermined amplitude.
The present application also proposes an electronic system comprising a neural network as described above.
The application also proposes an electronic device comprising a neural network as described above.
By adopting the scheme of the application, on one hand, the advantages of low power consumption and high calculation performance can be obtained because the scheme simulates the neuron from the physical structure of the circuit; on one hand, the STDP mechanism is used for optimizing the signal transmission of the neuron morphological circuit, so that the time consumed by circuit processing can be further shortened. The ferroelectric field effect transistor used in the circuit design can reduce the power consumption of the circuit again through the characteristics of the nonvolatile characteristic and the like, and the processing speed is improved. The electronic synapse circuit provided by the application uses fewer transistors, and can be applied to a neural network to reduce the chip area on a large scale. The novel neural network structure provided by the scheme has positive significance for promoting the development of the neuromorphic circuit.
Drawings
Preferred embodiments of the present application will now be described in further detail with reference to the accompanying drawings, in which:
FIG. 1 is a diagram illustrating a neural network model according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an STDP mechanism characteristic of an electronic synapse;
FIG. 3A is a schematic diagram of an electronic synapse circuit and a portion of a post-synaptic neuron circuit in accordance with an embodiment of the present application;
FIG. 3B is a timing diagram illustrating the operation of the circuit shown in FIG. 3A;
FIG. 4 is a graph illustrating normalized conductance versus time for an electronic synapse circuit in accordance with an embodiment of the present application.
Detailed Description
In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the present application can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the application. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. For the connection between the units in the drawings, for convenience of description only, it means that at least the units at both ends of the connection are in communication with each other, and is not intended to limit the inability of communication between the units that are not connected. The number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the outputs provided, and is not intended to limit the communication between the two units to signals only as shown in the figure.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.
A transistor may refer to a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT). When the transistor is a field effect transistor, the transistor can be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, an organic transistor, or the like, depending on the channel material. An N-type transistor and a P-type transistor can be classified according to whether carriers are electrons or holes. The control electrode refers to a grid electrode of the field effect transistor, the first electrode can be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode can be a source electrode or a drain electrode of the field effect transistor; when the transistor is a bipolar transistor, the control electrode of the transistor refers to a base electrode of the bipolar transistor, the first electrode may be a collector or an emitter of the bipolar transistor, and the corresponding second electrode may be an emitter or a collector of the bipolar transistor.
In the following detailed description, the active level may be a high level or a low level depending on the circuit. In the following embodiments, for the sake of understanding, a high level is described as an active level, and a low level is described as an inactive level.
In the following detailed description, for the sake of understanding, a level at which the potential is 0 is described as a low level, and hereinafter, the ground potential is the same as the potential of the low level.
In a traditional computer architecture, a device is divided into a computing unit and a storage unit, the computing unit is required to be called to compute data to be processed after one-time computation is completed, and then a computation result is stored in the storage unit. In the face of larger data and more complex calculation processes, the conventional computer architecture needs to split the calculation process into a plurality of simple calculations, repeat the above steps for a plurality of times, generate a plurality of intermediate values before obtaining a final calculation result and store the intermediate values into a storage unit, and call the intermediate values to complete the calculation of the final result during calculation.
The artificial neural network (hereinafter referred to as neural network) provided by the application can effectively simplify the complex calculation process and can avoid the problems caused by calculation separation.
Fig. 1 is a schematic diagram of a neural network model according to an embodiment of the present application. In a neural network, a plurality of nodes, also called neurons, are included, and two neurons may be connected by an electronic synapse. Synapses transmit electrical signals from electronic pre-synaptic neurons to post-synaptic neurons, the path of transmission depending on the weight of the electronic synapse between the neurons. A higher weight represents a tighter connection between two neurons.
As shown in fig. 1, according to an embodiment of the present application, a neuron in a neural network may be connected to a plurality of neurons, and two neurons may be connected and transmit signals through an electronic synapse. The computation to be completed can be converted into a plurality of loop computations in the neural network, and a single computation process can be converted into a process of transmitting signals from an initial neuron set by a user in the neural network, and routing the signals to a plurality of neurons and electronic synapses and finally transmitting the signals to a target neuron set by the user. The neural network automatically adjusts the weight between the neurons based on a preset learning mechanism, so that the calculation process of different problems is realized.
Each electronic synapse may receive signals from at least one neuron (referred to as a pre-synaptic neuron with respect to the synapse) and/or may transmit signals to at least one neuron (referred to as a post-synaptic neuron with respect to the synapse).
FIG. 2 is a diagram illustrating the STDP learning mechanism of an electronic synapse. Wherein, the time Δ t of the horizontal axis represents the time difference between the time when the post-synaptic neuron emits the signal and the time when the pre-synaptic neuron emits the signal, and the time Δ W of the vertical axis represents the weight change rate of the electronic synapse. As can be seen from fig. 2, for such an electronic synapse, when Δ t is positive, the rate of change of the weight of the electronic synapse decreases with increasing Δ t.
To prepare an electronic synapse having an STDP learning mechanism characteristic curve as described above, an electronic synapse circuit is provided. In particular, such electronic synapse circuits comprise ferroelectric transistors (fefets).
With the development of semiconductor device technology, some new devices having adjustable resistance and nonvolatile characteristics are proposed, including resistive random access memories, phase change memories, ferroelectric transistors (fefets), and the like. Among them, fefets have advantages of low power consumption and high operation speed, and thus have received extensive attention from the scientific research and industrial fields.
The FeFET is a novel transistor with a layer of ferroelectric material added between a grid electrode and a grid oxide layer of a traditional MOSFET, and the magnitude of the electric charge induced on the grid oxide layer can be modulated by changing the amplitude and the duration of the voltage applied to the grid electrode of the FeFET, so that the threshold voltage and the channel resistance of the FeFET can be changed. When a specific voltage is applied to the gate source of the FeFET, the electric dipole formed in the crystal structure of the ferroelectric material is kept consistent with the direction of the electric field, and the above-mentioned conduction characteristic thereof is not changed even if the gate voltage is removed, and the electric dipole formed in the crystal structure of the ferroelectric material is kept in such a polarized state even after the electric field is removed, so that the threshold voltage and channel resistance of the FeFET are kept unchanged until the gate source voltage thereof is changed to set the threshold voltage and channel resistance thereof again.
FIG. 3A is a schematic diagram illustrating an electronic synapse circuit and a portion of a post-synaptic neuron circuit in accordance with an embodiment of the present application. FIG. 3B is a timing diagram illustrating the operation of the circuit shown in FIG. 3A.
As shown in FIG. 3A, the electronic synaptic electrical circuit 20 is coupled to its post-synaptic neuron circuit 30, while the electronic synaptic electrical circuit 20 is also coupled to a pre-synaptic neuron circuit (not shown). According to an embodiment, the pre-synaptic neuron circuit may have a similar circuit structure as the post-synaptic neuron circuit.
According to one embodiment, each neuron circuit may emit at least four signals, including IP _1 and CL _1, when emitting signals, which may be provided to the rear neuron circuit as input signals and control signals by the post synapses; the four signals also include FB _1 and FB _2, which may be provided as feedback signals to pre-synapses connected between the neuron circuit and preceding neuron circuits. Here, "front" or "rear" refers to a case where the signal transmission path inputted by the user is relatively closer to the most initial neuron circuit and is referred to as "front", and a case where the signal transmission path is relatively farther from the most initial neuron circuit and is referred to as "rear".
For a particular electronic synaptic circuit, CL _1 provides a control signal to the pre-synaptic neuron circuit that determines the connection status of the electronic synaptic circuit to the post-synaptic neuron circuit. IP _1 is an input signal provided by the presynaptic neuron circuit and determines an updated value of the electronic synaptic circuit weight. The feedback signals FB _1 and FB _2 are provided by the post-synaptic neuron circuit and determine the timing for modifying the current weight of the electronic synapse circuit to an updated value, and the magnitude of FB _2 also determines the updated value of the weight of the electronic synapse circuit.
According to one embodiment, as shown in fig. 3A, the electronic synapse circuit 20 may comprise at least a switching unit 201, an input unit 202 and a weight calculation unit 203.
According to an embodiment, the switch unit 201 may comprise at least, for example, an NMOS transistor M21, the gate of which may be configured to receive the control signal CL _1 from the pre-synaptic neuron circuit. As shown in FIG. 3B, CL _1 includes a plurality of high-level long pulses, and when CL _1 is high, the electronic synapse circuit 20 is activated and the electrical connection to the post-synaptic neuron circuit 30 is made.
According to one embodiment, the input unit 202 may include at least, for example, NMOS transistors M23 and M25, and a PMOS transistor M24.
According to an embodiment, the drain of M23 may be configured to receive an input signal IP _1 from one pre-synaptic neuron circuit, the source may be coupled to weight calculation unit 203, and the gate may be configured to receive a feedback signal FB _1 from a post-synaptic neuron circuit.
According to an embodiment, the source of M24 may be coupled to the source of M23 and weight calculation unit 203, its drain may be grounded, and its gate may be configured to receive feedback signal FB _1 from the post-synaptic neuron circuit.
According to an embodiment, the source of M25 may be configured to receive a feedback signal FB _2 from a post-synaptic neuron circuit, the drain may be coupled to the weight calculation unit 203, and the gate may be configured to receive a control signal CL _1 from a pre-synaptic neuron circuit.
According to one embodiment, the weight calculation unit 203 may include at least a FeFET transistor M22. According to one embodiment, the gate of M22 may be coupled to the source of M23 and the source of M24, the source of M22 may be coupled to the drain of M25, and the drain of M22 may be coupled to the source of M21.
As shown in fig. 3A, a neuron circuit, such as the post-synaptic neuron circuit 30, may comprise at least a comparator 301, a resistor 302, and a capacitor 303. The positive input of the comparator 301 may be coupled to the electronic synapse circuit 20 (e.g., may be coupled to the drain of the transistor M21) and also coupled to a power source via a resistor 302. The negative input of the comparator 301 is configured to receive a preset threshold voltage Vth. Once the positive input voltage Vout of the comparator 301 is lower than the negative input voltage Vth, the neuron outputs an output signal Y (including FB _1 and FB _2, and CL _1 'and IP _ 1' provided to its rear neuron).
According to an embodiment of the present application, the post-synaptic neuron circuit 30 may further include a signal processing unit 304 configured to process the output signal Y to output the feedback signals FB _1 and FB _2, ensure that the output feedback signals FB _2 and FB _1 are emitted simultaneously, the duration of the active level is the same, and the amplitude of FB _1 is smaller than the amplitude of FB _2, and the amplitude of the high level of FB _2 is controlled within a range that meets the requirement of the circuit design.
According to an embodiment of the present application, device parameters such as gate length, doping concentration, and gate insulating layer thickness of M21, M22, M23, M24, and M25 are not limited, and can be adjusted according to actual needs.
According to one embodiment, as shown in fig. 3B, when Vout is higher than Vth, the post-synaptic neuron circuit does not output the signal Y, and therefore FB _1 and FB _2 are also low. In this case, the transistor M23 in the input cell 201 is turned off, the transistor M24 is turned on, and if CL _1 is at a high level, M25 is turned on, the drain of M25 receives a low level of FB _2, which corresponds to the gate and source of the FeFET transistor M22 being grounded. In this case, the threshold voltage and channel resistance of the FeFET transistor M22 are unchanged. According to one embodiment, M22 may remain on when the gate-source voltage is 0.
When CL _1 goes high, the charge on capacitor 303 is drained through the path of M22 in the electronic synapse circuit. When Vout decreases to a level lower than Vth, the post-synaptic neuron circuit 30 emits signals Y, FB _1 and FB _2 jumping to high levels.
According to one embodiment, a neuron circuit has a plurality of preceding electronic synapse circuits coupled thereto. When any of these electronic synapse circuits is first able to lower Vout to a level below Vth, the neuron circuit will transmit a signal Y, and all of the preceding electronic synapse circuits coupled thereto will receive high levels of FB _1 and FB _ 2.
However, if Vout cannot drop below Vth through bleeding during one high pulse of CL _1, and other preceding electronic synapse circuits do not achieve this, the power supply will continue to charge capacitor 303 after CL _1 goes high, and again bleed off the charge in capacitor 303 when the next high CL _1 comes. Over several bleeds or integrations, it is possible to achieve the goal of Vout dropping to a level below Vth.
During CL _1 being high, M21 and M25 are conducting. When FB _1 and FB _2 go high temporarily, M24 is turned off, M23 is turned on, M23 provides IP _1 to the gate of M22, and M25 provides FB _2 to the source of M22, so that the threshold voltage and channel resistance of M22 are changed, and the weight of the electronic synapse circuit is updated. Of course, as described above, the arrival of the high levels of FB _1 and FB _2 may be caused by the electronic synapse circuits themselves, or by other electronic synapse circuits coupled to the neuron circuit 30. But no matter which electronic synapse circuit fires, the neuron circuit 30 emits FB _1 and FB _2, so that the weights of all the preceding electronic synapse circuits coupled thereto change.
According to the embodiment of the application, since the time when each electronic synapse circuit receives the input signal IP _1 provided by the pre-synaptic neuron may be different, the threshold voltage and the channel resistance change value of M22 in each electronic synapse circuit are different, the changed weight value of each electronic synapse circuit may be different, or the threshold voltage and the channel resistance of the FeFET transistor may be set to different values. But regardless of which electronic synapse circuit fires, the neuron circuit 30 transmits FB _1 and FB _2, and thus the weights of all the preceding electronic synapse circuits coupled thereto may change.
When the control signal CL _1 goes high continuously or temporarily again, the weight updated electronic synapse circuit 20 will drain the charge in the capacitor 303 with an updated channel resistance.
To achieve the electronic synapse properties shown in FIG. 2, according to one embodiment, for the circuit shown in FIG. 3A, as shown in FIG. 3B, in each clock cycle, the duration of the high level Vhh of CL _1 completely coincides with the pulse time period of the high level of IP _1, or CL _1 is the same as the period of IP _ 1. According to one embodiment, the high level maximum values of CL _1 and IP _1 may be different. According to different embodiments, the maximum high level of CL _1 may be greater than the maximum high level of IP _1, or may be less than or equal to the maximum high level of IP _ 1.
According to one embodiment, during the first half of the high-level pulse period, the amplitude of the high level of IP _1 is gradually decreased from the first preset amplitude V1 over time, the slope of which may ensure that the electronic synapse has substantially the same characteristic as the synapse in the third quadrant of FIG. 2; during the second half of the period of the IP _1 high pulse, the amplitude of the IP _1 high pulse first jumps from the low level to the second predetermined amplitude V2 and gradually decreases with time, with a slope that ensures that the electronic synapse has substantially the same characteristic as the synapse in the first quadrant of FIG. 2. According to one embodiment V1 is less than V2.
The first half of the time and the second half of the time herein may be the same or different time periods, according to different embodiments.
According to one embodiment, in order to satisfy the turn-on rule of M23 and M25, the FB _1 high level pulse amplitude, i.e., Vhh, should be greater than the maximum value of the amplitude of the high level pulse of IP _1, i.e., the second preset amplitude V2, so that M23 may be turned on; the FB _2 high-level pulse amplitude, V3, should be greater than the first preset amplitude V1 of IP _1 and less than the minimum value of IP _1 in the second half of the high-level pulse time period to ensure that substantially the same electronic synaptic property curve as shown in FIG. 2 is achieved.
FIG. 4 is a graph illustrating normalized conductance versus time for an electronic synapse circuit in accordance with an embodiment of the present application. As shown in fig. 4, Δ t on the horizontal axis is a time difference between a time when the post-synaptic neuron emits the signal Y and a preset time (the preset time is a time when two previous and next segments in the IP _1 high-level pulse time period are connected, or a time when two previous and next pulses in the IP _1 high-level pulse time period are switched) (Δ t may be calculated relative to other times, but a generated variation curve is different from fig. 4, and a mechanism of the characteristic curve shown in fig. 2 cannot be realized). The AwWW on the vertical axis represents the percent change in conductivity of M22 in the electronic synapse circuit. In order to enable the curve to be more visual, the change curve of the conductivity is normalized according to delta t.
If the high levels of FB _1 and FB _2 fall in the second half of the high-level pulse period of IP _1, Δ t is positive, IP _1 is positive at this stage and gradually decreases from the second preset amplitude V2, the conductance of M22 (and the corresponding rate of change of the weight of the electronic synapse) decreases with increasing Δ t (the rate of change of the weight of the electronic synapse positively correlates with the conductance of M22). If the high levels of FB _1 and FB _2 fall in the first half of the high level pulse period of IP _1, Δ t is negative, during which IP _1 is positive and gradually decreases from the first preset amplitude V1, the conductance of M22 and the rate of change of the weight of the corresponding electronic synapse become smaller as Δ t increases. The magnitude of the conductance change of M22 is affected by the maximum magnitude of the high level of IP _ 1.
Of course, different input and control signals may be used depending on the STDP mechanism curve of the different electronic synapses.
According to the scheme, the memory characteristic and the nonvolatile characteristic of the FeFET are utilized, the FeFET is applied to an electronic synapse, the threshold voltage and the channel resistance of the FeFET are set by adjusting the voltage value applied to the grid electrode of the FeFET, so that the specific weight of the synapse is set, the circuit design can be simplified to a certain extent, and the functions of a plurality of elements can be realized. Meanwhile, due to the advantages of low power consumption and high running speed, the power consumption of the circuit and the equipment can be further reduced, and the running efficiency is improved. The method is applied to the network design of the neuromorphic calculation, and the neuromorphic calculation with low power consumption and high calculation performance can be realized.
In the calculation and optimization process, the circuit does not need to store the calculated weight and the intermediate value of other input signals, and does not need to call the intermediate value again before the next calculation, so that the use times of the circuit is reduced, the calculation speed is improved, and the power consumption of the circuit is reduced.
The electronic synapse circuit provided by the application uses fewer transistors, and can be applied to a neural network to reduce the chip area on a large scale.
The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.

Claims (15)

1. A neural network, comprising:
a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of said electronic synapse circuits is configured to receive input and control signals from one pre-synaptic neuron circuit and to receive feedback signals of one post-synaptic neuron circuit;
wherein the electronic synapse circuit comprises at least:
a switching unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synapse circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit;
an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive an input signal from the pre-synaptic neuron circuit under control of first and second feedback signals from the post-synaptic neuron circuit;
a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the input signal and the second feedback signal from the input unit to update a channel resistance of the ferroelectric transistor.
2. The neural network of claim 1, wherein
The post-synaptic neuron circuit comprises at least:
a comparator having a positive input coupled to a switching unit of the electronic synapse circuit, a negative input configured to receive a preset constant signal, an output coupled to an input unit of the electronic synapse circuit;
a resistor coupled between a positive input of the comparator and a power supply;
a capacitor coupled between a positive input of the comparator and ground;
when the switch unit connects the post-synaptic neuron circuit and the electronic synapse circuit, an
The ferroelectric transistor is turned on, a voltage at a positive input terminal of the comparator decreases, and when the voltage decreases below the preset constant signal, the comparator is configured to output the first and second feedback signals.
3. The neural network of claim 2, wherein the switching unit includes at least a first transistor having a control electrode configured to receive the control signal, a first electrode coupled to the positive input of the comparator, and a second electrode coupled to the first electrode of the FEFET.
4. The neural network of claim 3, wherein the input units include at least,
a second transistor having a control electrode configured to receive the first feedback signal, a first electrode configured to receive the input signal, and a second electrode coupled to the control electrode of the ferroelectric transistor;
a third transistor of a type complementary to the second transistor, having a control electrode configured to receive the first feedback signal, having a first electrode coupled to ground, and a second electrode coupled to the control electrode of the ferroelectric transistor;
a fourth transistor of the same type as the second transistor, having a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.
5. The neural network of any one of claims 1-4, wherein a control electrode of the ferroelectric transistor is configured to receive the input signal, a second electrode of the ferroelectric transistor is configured to receive the second feedback signal;
the control signal and the input signal have the same period;
the effective level of the input signal is gradually reduced from a first preset amplitude value in the first half of the pulse time of the effective level;
and the effective level of the input signal is gradually reduced from a second preset amplitude value in the second half of the pulse time of the effective level, wherein the second preset amplitude value is larger than the first preset amplitude value.
6. The neural network of claim 5, wherein the magnitude of the active level of the first feedback signal is greater than the second predetermined magnitude.
7. The neural network of claim 5 or 6, wherein the magnitude of the active level of the second feedback signal is greater than the first predetermined magnitude and less than the second predetermined magnitude.
8. An electronic synaptic electrical circuit configured to receive input and control signals from a pre-synaptic neuron circuit and to receive feedback signals from a post-synaptic neuron circuit;
wherein the electronic synapse circuit comprises at least:
a switching unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to control a connection state of the electronic synapse circuit with the post-synaptic neuron circuit under the influence of a control signal from the pre-synaptic neuron circuit;
an input unit coupled to the pre-synaptic neuron circuit and the post-synaptic neuron circuit, configured to receive an input signal from the pre-synaptic neuron circuit under control of first and second feedback signals from the post-synaptic neuron circuit;
a weight calculation unit coupled between the switching unit and ground and coupled with the input unit, the weight calculation unit including at least a ferroelectric transistor configured to receive the input signal and the second feedback signal from the input unit to update a channel resistance of the ferroelectric transistor.
9. An electronic synapse circuit as claimed in claim 8 wherein said switching unit comprises at least a first transistor having a control electrode configured to receive said control signal, a first electrode coupled to an input of said post-synaptic neuron, and a second electrode coupled to a first electrode of said ferroelectric field effect transistor.
10. The electronic synapse circuit of claim 9 wherein said input cells comprise at least,
a second transistor having a control electrode configured to receive the first feedback signal, a first electrode configured to receive the input signal, and a second electrode coupled to the control electrode of the ferroelectric transistor;
a third transistor of a type complementary to the second transistor, having a control electrode configured to receive the first feedback signal, having a first electrode coupled to ground, and a second electrode coupled to the control electrode of the ferroelectric transistor;
a fourth transistor of the same type as the second transistor having a control electrode configured to receive the control signal, a first electrode coupled to the second electrode of the ferroelectric transistor, and a second electrode configured to receive the second feedback signal.
11. The electronic synapse circuit of any of claims 8-10 wherein a control electrode of said ferroelectric transistor is configured to receive said input signal, a second electrode of said ferroelectric transistor is configured to receive said second feedback signal;
the control signal and the input signal have the same period;
the effective level of the input signal is gradually reduced from a first preset amplitude value in the first half of the pulse time of the effective level;
and the effective level of the input signal is gradually reduced from a second preset amplitude value in the second half of the pulse time of the effective level, wherein the second preset amplitude value is larger than the first preset amplitude value.
12. The electronic synapse circuit of claim 11 wherein an active level amplitude of said first feedback signal is greater than said second preset amplitude.
13. An electronic synaptic electrical circuit according to claim 11 or 12, wherein the magnitude of the active level of said second feedback signal is greater than said first predetermined magnitude and less than said second predetermined magnitude.
14. An electronic system comprising a neural network as claimed in any one of claims 1 to 7.
15. An electronic device comprising a neural network as claimed in any one of claims 1 to 7.
CN202210340931.0A 2022-03-28 2022-03-28 Improved electronic synapse circuit and neural network based on ferroelectric field effect transistor Pending CN115115041A (en)

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