CN115114210B

CN115114210B - PCIe resource expansion device for Altra max central processing unit

Info

Publication number: CN115114210B
Application number: CN202210461425.7A
Authority: CN
Inventors: 张世强; 李岩; 刘圣金
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2023-07-14
Anticipated expiration: 2042-04-28
Also published as: CN115114210A

Abstract

The invention discloses an Altra max central processing unit PCIe resource expansion device and a server. Comprising the following steps: the first interface, the second interface and the third interface on the first high-order signal connecting part lead out high eight bits of three groups of PCIe signals; the fourth interface, the fifth interface and the sixth interface of the first low-order signal connecting part lead out the low eight bits of the three groups of PCIe signals; and the first RISER card comprising a first PCIe x16 interface, a second PCIEx16 interface and a third PCIe x16 interface is adopted, the three low-eight-bit slots of the PCIe x16 interface are not connected with the fourth interface, the fifth interface and the sixth interface respectively, and the first interface, the second interface and the third interface are detachably connected with the high-eight-bit slots of the three PCIe x16 interfaces respectively by using a first cable, a second cable and a third cable. According to the scheme, the low-order signals are fixed, the high-order signals are flexibly changed, and the CPU resources are expanded to the greatest extent.

Description

PCIe resource expansion device for Altra max central processing unit

Technical Field

The invention relates to the field of servers, in particular to an Altra max central processing unit PCIe resource expansion device and a server.

Background

The Ampere platform processor is taken as a brand-new platform, is the platform with the highest kernel density in the industry at present, and the server based on the Ampere platform processor provides excellent performance and expandability for various application environments. In particular, an Ampere platform Altra max CPU (Central Processing Uni, central processing unit) supports PCIe x16 configuration, and a designed server has functions and reduced power consumption, and is favored in abundant resources and flexible configuration. At present, the Ampere platform server altra max is flexible to extend outwards, PCIe resources of the same server are different in utilization rate, and based on the CPU server main board design, PCIe resources are required to be considered deeply for reasonable utilization. The server based on the CPU can directly draw out and access PCIe equipment to expand corresponding functions, and can also expand PCIe resources in the form of leading out to a connector and connecting an RISER card through a cable, so that challenges are presented on how to utilize the resources on the basis of various configurations.

Currently, an Ampere platform server altra max CPU externally supports 6 RCAs such as RCA 2-RCA 7 and the like for expanding PCIe resources, and PCIe [ D0:D15] resources of each RCA support X16, X8+X8, X8+X4, X4+X4, but do not support the resource allocation of X4+X4 +X8. Specifically, the unsupported configuration is divided into two application cases: one is that when the high order of RCA is applied to the X8 device, the low order 8 cannot be applied to the x4+x4 device, for example, the low order 8 cannot be applied to the NVMe hard disk extended with x4+x4; another case is that when the lower 8 bits are applied to an X4+ X4 extended NVMe hard disk, the upper 8 bits of RCA cannot support the X8 PCIe device. In the case of multiple configuration applications of a server, many cases are affected by this unsupported configuration, so that individual interface resources cannot be extended, and thus the function extension is limited. The CPU server based on the Ampere platform altra max needs careful consideration of PCIe resource allocation on the design of a main board, and the situation that the same server cannot realize various configurations and the individual configuration functions are limited due to unreasonable resource allocation easily occurs when the PCIe resource allocation is considered.

Disclosure of Invention

In view of the foregoing, it is necessary to provide an apparatus and a server for expanding PCIe resources of an Altra max cpu.

According to a first aspect of the present invention, there is provided an Altra max central processor PCIe resource expansion device, the device comprising:

the first high-order signal connection part comprises a first interface, a second interface and a third interface which are arranged on the server mainboard, wherein the first interface is connected with the high-order eight bits of a first PCIe signal of the Altra max central processor, the second interface is connected with the high-order eight bits of a second PCIe signal of the Altra max central processor, and the third interface is connected with the high-order eight bits of a third PCIe signal of the Altra max central processor;

the first low-order signal connection part comprises a fourth interface, a fifth interface and a sixth interface, wherein the fourth interface is connected with the low-order eight bits of the first PCIe signal, the fifth interface is connected with the low-order eight bits of the second PCIe signal, and the sixth interface is connected with the low-order eight bits of the third PCIe signal;

a first RISER card comprising a first PCIe x16 interface, a second PCIe x16 interface, and a third PCIe x16 interface, wherein the fourth interface inserts low octets of the first PCIe x16 interface, the fifth interface inserts low octets of the second PCIe x16 interface, and the sixth interface inserts low octets of the third PCIe x16 interface;

the high-speed cable comprises a first cable, a second cable and a third cable, wherein the first cable is used for detachably connecting the first interface with the high-eight-bit slot of the first PCIe x16 interface, the second cable is used for detachably connecting the second interface with the high-eight-bit slot of the second PCIe x16 interface, and the third cable is used for detachably connecting the third interface with the high-eight-bit slot of the third PCIe x16 interface.

In some embodiments, the apparatus further comprises:

the second high-order signal connection part comprises a seventh interface, an eighth interface and a ninth interface which are arranged on the server mainboard, wherein the seventh interface is connected with the high-order eighth bit of the fourth PCIe signal of the Altra max central processor, the eighth interface is connected with the high-order eighth bit of the fifth PCIe signal of the Altra max central processor, and the ninth interface is connected with the high-order eighth bit of the sixth PCIe signal of the Altra max central processor;

a second low-order signal connection portion including a tenth interface, an eleventh interface, and a twelfth interface, the tenth interface being connected with the low-order bits of the fourth PCIe signal, the eleventh interface being connected with the low-order bits of the fifth PCIe signal, the twelfth interface being connected with the low-order bits of the sixth PCIe signal;

a second RISER card comprising a fourth PCIe x16 interface, a fifth PCIe x16 interface, and a sixth PCIe x16 interface, the tenth interface inserted into a low octet slot of the fourth PCIe x16 interface, the eleventh interface inserted into a low octet slot of the fifth PCIe x16 interface, and the twelfth interface inserted into a low octet slot of the sixth PCIe x16 interface;

the device comprises a fourth cable, a fifth cable and a sixth cable, wherein the fourth cable is used for detachably connecting the seventh interface with the high-eight-bit slot of the fourth PCIe x16 interface, the fifth cable is used for detachably connecting the eighth interface with the high-eight-bit slot of the fifth PCIe x16 interface, and the sixth cable is used for detachably connecting the ninth interface with the high-eight-bit slot of the sixth PCIe x16 interface.

In some embodiments, one of the fourth interface, the fifth interface, and the sixth interface is a PCIe x8 connector, and the remaining two are an upper octet and a lower octet, respectively, of one PCIe x16 connector.

In some embodiments, the first interface, the second interface, and the third interface are all Slimline x8 interfaces.

In some embodiments, one of the tenth, eleventh, and twelfth interfaces is a PCIe x8 connector, and the remaining two are an upper octet and a lower octet, respectively, of one PCIe x16 connector.

In some embodiments, the seventh interface, the eighth interface, and the ninth interface are all Slimline x8 interfaces.

In some embodiments, the Altra max central processor is piggybacked with an amp platform.

In some embodiments, when a first cable does not connect the first interface with the high octets of the first PCIe x16 interface, the first cable is used to connect the first interface with two PCIe x4 interfaces or with one PCIe x8 interface;

when a second cable does not connect the second interface with the high octet slot of the second PCIe x16 interface, the second cable is used to connect the second interface with two PCIe x4 interfaces or with one PCIe x8 interface;

when the third cable does not connect the third interface with the high octets of the third PCIe x16 interface, the third cable is used to connect the third interface with two PCIe x4 interfaces or with one PCIe x8 interface.

In some embodiments, when a fourth cable is not connecting the seventh interface with the high octets of the fourth PCIe x16 interface, the fourth cable is used to connect the seventh interface with two PCIe x4 interfaces or with one PCIe x8 interface;

when a fifth cable does not connect the eighth interface with the high octet slot of the fifth PCIe x16 interface, the fifth cable is configured to connect the eighth interface with two PCIe x4 interfaces or with one PCIe x8 interface;

when the sixth cable does not connect the ninth interface with the high octet slot of the sixth PCIe x16 interface, the sixth cable is used to connect the ninth interface with two PCIe x4 interfaces or with one PCIe x8 interface.

According to a second aspect of the present invention, there is also provided a server comprising an Altra max CPU that extends PCIe resources using the apparatus described above.

The Altra max central processing unit PCIe resource expansion device and the server have at least the following beneficial technical effects: the low-order signal is fixed, the high-order signal is convenient and flexible to modify, the situation that an Altra max CPU does not support X4+X4+X8 application is avoided, meanwhile, CPU resources are expanded to the greatest extent, the maximum selection and configuration requirements of Altra max server PCIe X16/X8 resources are realized, and the resource utilization rate of an Ampere platform server is expanded to the greatest extent.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an apparatus for PCIe resource expansion of an Altra max cpu according to an embodiment of the present invention;

fig. 2 is a schematic connection diagram of a first high-order signal connection portion and an Altra max cpu according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a connection between a first low-level signal connection portion and an Altra max CPU according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of signal connection of a first RISER card according to one embodiment of the present invention;

fig. 5 is a schematic diagram of an interconnection block diagram of an intra-PCIe resource expansion device for six-group PCIe signal expansion provided by another embodiment of the present invention.

[ reference numerals description ]

100: an Altra max CPU;

rac2_h: the upper eight bits of the first PCIe signal; rac2_l: the low eight bits of the first PCIe signal; rac3_h: the upper eight bits of the second PCIe signal; rac3_l: the lower eight bits of the second PCIe signal; rac4_h: the upper eight bits of the third PCIe signal; rac4_l: the lower eight bits of the third PCIe signal; rac5_h: the upper eight bits of the fourth PCIe signal; rac5_l: the lower eight bits of the fourth PCIe signal; rac6_h: the upper eight bits of the fifth PCIe signal; rac6_l: the lower eight bits of the fifth PCIe signal; rac7_h: the upper eight bits of the sixth PCIe signal; rac7_l: the lower eight bits of the sixth PCIe signal;

200: a first high-order signal connection part; 201: a first interface; 202: a second interface; 203: a third interface;

300: first low-order signal connection portion: 301: a fourth interface; 302: a fifth interface; 303: a sixth interface;

400: a first RISER card; 401: a first PCIe x16 interface; 402 first PCIe x16 interface: 403: a third PCIe x16 interface;

500: a second high-order signal connection part; 501: a seventh interface; 502: an eighth interface; 503: a ninth interface;

600: second low-order signal connection portion: 601: a tenth interface; 602: an eleventh interface; 603: a twelfth interface;

700: a second RISER card; 701: a fourth PCIe x16 interface; 702 fifth PCIe x16 interface: 703: a sixth PCIe x16 interface;

cable1: a first cable; cable2: a second cable; cable3: a third cable; cable4: a fourth cable; cable5: a fifth cable; cable6: and a sixth cable.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. Furthermore, the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In some embodiments, referring to fig. 1, the present embodiment provides an apparatus for expanding PCIe resources of an Altra max cpu, where the apparatus includes:

a first high-order signal connection part 200, which comprises a first interface 201, a second interface 202 and a third interface 203 which are arranged on a server main board, wherein the first interface 201 is connected with a high-order eight bit rac2_h of a first PCIe signal of the Altra max central processor 100, the second interface 202 is connected with a high-order eight bit rac3_h of a second PCIe signal of the Altra max central processor 100, and the third interface 203 is connected with a high-order eight bit rac4_h of a third PCIe signal of the Altra max central processor 100; fig. 2 shows a schematic connection diagram of the first high-level signal connection portion 200 and the Altra max cpu 100;

a first low-order signal connection unit 300, including a fourth interface 301, a fifth interface 302, and a sixth interface 303, where the fourth interface 301 is connected to a low-order octant rac2_l of the first PCIe signal, the fifth interface 302 is connected to a low-order octant rac3_l of the second PCIe signal, and the sixth interface 303 is connected to a low-order octant rac4_l of the third PCIe signal; fig. 3 shows a schematic connection diagram of the first low-level signal connection portion 300 and the Altra max cpu 100;

a first RISER card 400, the first RISER card 400 comprising a first PCIe x16 interface 401, a second PCIe x16 interface 402, and a third PCIe x16 interface 403, the fourth interface 301 inserted into a low octet of the first PCIe x16 interface 401, the fifth interface 302 inserted into a low octet of the second PCIe x16 interface 402, and the sixth interface 303 inserted into a low octet of the third PCIe x16 interface 403; fig. 4 shows a schematic diagram of connection between the first RISER card 400 and other signals;

a first Cable1, a second Cable2 and a third Cable3, where the first Cable1 is used to detachably connect the first interface 201 with the high-eight slot of the first PCIe x16 interface 401, the second Cable2 is configured to detachably connect the second interface 202 to the high-octet slot of the second PCIe x16 interface 402, and the third Cable2 is configured to detachably connect the third interface 203 to the high-octet slot of the third PCIe x16 interface 403.

The Altra max central processing unit PCIe resource expansion device has at least the following beneficial technical effects: the low-order signal is fixed, the high-order signal is convenient and flexible to modify, the situation that an Altra max CPU does not support X4+X4+X8 application is avoided, meanwhile, CPU resources are expanded to the greatest extent, the maximum selection and configuration requirements of Altra max server PCIe X16/X8 resources are realized, and the resource utilization rate of an Ampere platform server is expanded to the greatest extent.

In some embodiments, referring to fig. 1 and 5, the apparatus further includes:

a second high-order signal connection part 500, including a seventh interface 501, an eighth interface 502 and a ninth interface 503, which are disposed on the server motherboard, wherein the seventh interface 501 is connected with the high-order eighth rac5_h of the fourth PCIe signal of the Altra max central processor 100, the eighth interface 502 is connected with the high-order eighth rac6_h of the fifth PCIe signal of the Altra max central processor 100, and the ninth interface 503 is connected with the high-order eighth rac7_h of the sixth PCIe signal of the Altra max central processor 100;

a second low-order signal connection part 600, including a tenth interface 601, an eleventh interface 602, and a twelfth interface 603, wherein the tenth interface 601 is connected to the low-order eighth-bit rac5_l of the fourth PCIe signal, the eleventh interface 602 is connected to the low-order eighth-bit rac6_l of the fifth PCIe signal, and the twelfth interface 603 is connected to the low-order eighth-bit rac7_l of the sixth PCIe signal;

a second RISER card 700, the second RISER card 700 comprising a fourth PCIe x16 interface 701, a fifth PCIe x16 interface 702, and a sixth PCIe x16 interface 703, the tenth interface 601 inserting the low octet of the fourth PCIe x16 interface 701, the eleventh interface 602 inserting the low octet of the fifth PCIe x16 interface 702, the twelfth interface 603 inserting the low octet of the sixth PCIe x16 interface 703;

fourth Cable4, fifth Cable5 and sixth Cable5, fourth Cable4 is used for connecting with the seventh interface 501 and the high-eight bit slot of the fourth PCIe x16 interface 701 in a detachable manner, fifth Cable4 is used for connecting with the eighth interface 502 and the high-eight bit slot of the fifth PCIe x16 interface 702 in a detachable manner, and sixth Cable6 is used for connecting with the ninth interface 503 and the high-eight bit slot of the sixth PCIe x16 interface 703 in a detachable manner.

In some embodiments, referring to fig. 1 and 5, one of the fourth interface 301, the fifth interface 302 and the sixth interface 303 is a PCIe x8 connector, and the remaining two are an upper octet slot and a lower octet slot of one PCIe x16 connector, respectively.

In some embodiments, referring to fig. 1 and 5, the first interface 201, the second interface 202, and the third interface 203 are all Slimline x8 interfaces.

In some embodiments, referring to fig. 1 and 5, one of the tenth interface 601, the eleventh interface 602, and the twelfth interface 603 is a PCIe x8 connector, and the remaining two are an upper octet slot and a lower octet slot of one PCIe x16 connector, respectively.

In some embodiments, referring to fig. 1 and 5, the seventh interface 501, the eighth interface 502 and the ninth interface 503 are all Slimline x8 interfaces.

In some embodiments, referring to fig. 1 and 5, the Altra max cpu 100 is configured to implement an Ampere platform.

In some embodiments, referring to fig. 1 and 5, when the first Cable1 does not connect the first interface 201 with the high-octet slot of the first PCIe x16 interface 401, the first Cable1 is used to connect the first interface 201 with two PCIe x4 interfaces or one PCIe x8 interface;

when the second Cable does not have Cable2 to connect the second interface 202 with the high octets of the second PCIe x16 interface 402, the second Cable2 is configured to connect the second interface 202 with two PCIe x4 interfaces or with one PCIe x8 interface;

when the third Cable3 does not connect the third interface 203 with the high octets of the third PCIe x16 interface 403, the third Cable3 is configured to connect the third interface 203 with two PCIe x4 interfaces or with one PCIe x8 interface.

In some embodiments, referring to fig. 1 and 5, when the fourth Cable4 does not connect the seventh interface 501 to the high-octet slot of the fourth PCIe x16 interface 701, the fourth Cable4 is configured to connect the seventh interface 501 to two PCIe x4 interfaces or to one PCIe x8 interface;

when the fifth Cable5 does not connect the eighth interface 502 with the high octets of the fifth PCIe x16 interface 702, the fifth Cable4 is configured to connect the eighth interface 502 with two PCIe x4 interfaces or with one PCIe x8 interface;

when the sixth Cable6 does not connect the ninth interface 503 with the high octets of the sixth PCIe x16 interface 703, the sixth Cable6 is configured to connect the ninth interface 503 with two PCIe x4 interfaces or with one PCIe x8 interface.

In still another embodiment, in order to facilitate understanding of the technical solution of the present invention, please refer to fig. 5, in which an example of setting up an AMPERE platform by applying to an Altra max CPU server is shown below, specifically, the PCIe resource expansion device for an Altra max CPU provided in this embodiment includes 13 parts, which are respectively: an Altra max main processor 1, a PCIe x16 slot interface 2, a PCIe x8 slot interface 3, a Slimline x8 interface 4, a Slimline x8 interface 5, a Slimline x8 interface 6,3*PCIe x16 Riser7,PCIe x16 slot interface 8, a PCIe x8 slot interface 9, a Slimline x8 interface 10, a Slimline x8 interface 11 and a Slimline x8 interface 12,3*PCIe x16 Riser13; with the use of every 3 RCA port resources combined together, RCA2, RCA3, RCA4 are combined together and the Riser card is plugged to extend 3 PCIe slots, RCA5, RCA6, RCA7 are combined together and another 1 Riser card is plugged to extend another 3 PCIe slots. The method for designing the 3-path PCIe x16 slot of the Riser card extension is characterized in that low-order signals are provided by 1 PCIe x16 interface and 1 PCIe x8 interface, RCA2_L, RCA3_L, RCA4_L, RCA5_L, RCA6_L and RCA7_L low-order signal resource curing x8 forms are used for avoiding the application of x4+x4+x8 and simultaneously adopting a single CPU maximum expansion PCIe x16/x8 interface scheme. By fixing the low-order signals and conveniently and flexibly modifying the high-order signals, the situation that an Altra max CPU does not support the application condition of X4+X4+X8 is avoided, simultaneously, CPU resources are expanded to the greatest extent, the maximum selection and configuration requirements of the Altra max server PCIe X16/X8 resources of the Ampere platform are realized, and the resource utilization rate of the Ampere platform server is expanded to the greatest extent.

The function and connection relationship of the parts are described in detail below:

the Altra max main processor 1 adopts an Ampere platform Altra max processor and is a platform core device. In this embodiment, the Altra max host processor 1 is connected to the PCIe x16 slot interface 2, and provides the rca2_ L, RCA3_l signal required by the PCIe x16 slot interface 2 to extend the signal to the outside; the external expansion RCA4_L signal is connected with a PCIe x8 slot interface 3; the RCA2_H signal is extended outwards by connecting with the Slimline x8 interface 4; the RCA3_H signal is extended outwards by connecting with a Slimline x8 interface 5; the RCA4_H signal is extended outwards by connecting with a Slimline x8 interface 6; the RCA 5-L, RCA-L signal required by the PCIe x16 slot interface 8 is provided for external expansion signals by being connected with the PCIe x16 slot interface 8; the external expansion RCA7_L signal is connected with a PCIe x8 slot interface 9; connected with the Slimline x8 interface 10, the RCA5_H signal is extended outwards; the RCA6_H signal is extended outwards by connecting with a Slimline x8 interface 5; connected to the Slimline x8 interface 6, the rca7_h signal is extended externally.

The PCIe x16 slot interface 2 is a standard PCIe x16 slot connector, is connected to the Altra max processor 1, and is responsible for leading out the rca2_ L, RCA3_l signal of the Altra max processor 1. The PCIe x16 slot interface 8 and the PCIe x16 slot interface 2 are standard PCIe x16 slot connectors, are connected with the Altra max processor 1, and are responsible for leading out rca5_ L, RCA6_l signals of the Altra max processor 1.

The PCIe x8 slot interface 3 is a standard PCIe x8 slot connector, is connected to the Altra max processor 1, and is responsible for leading out the rca4_l signal of the Altra max processor 1. The PCIe x8 slot interface 8 and the PCIe x8 slot interface 3 are standard PCIe x8 slot connectors, and are connected with the Altra max processor 1 to be responsible for leading out RCA7_L signals of the Altra max processor 1. The rca2_ L, RCA3_ L, RCA4 _4_ L, RCA5_ L, RCA6_ L, RCA7_l ports of the Altra max processor 1 are all fixed set to the x8 state, all the lower 8 bits that are eventually all connected to PCIe x16 slots.

The PCIe x16 slot interface 2 and the PCIe x8 slot interface 3 are aligned on the motherboard end as shown in fig. 3, and these 2 connectors can be inserted with 3*PCIe x16 Riser7, and the low 8-bit signals of the PCIe x16 standard slots of 3 paths of slots 0,1 and 2 are extended outwards.

The PCIe x16 slot interface 8 and the PCIe x8 slot interface 9 are also aligned on the main board end, the 2 connectors can be inserted with 3*PCIe x16 Riser13, and 3 paths of PCIe x16 standard slot low 8-bit signals of

slots

3,4 and 5 are externally expanded.

The Slimline x8 interface 4, the Slimline x8 interface 5 and the Slimline x6 interface 6 are Slimline connectors, are connected with the Altra max processor 1 and are responsible for leading out RCA2_ H, RCA3_ H, RCA _H signals of the Altra max processor 1.

The Slimline x8 interface 10, the Slimline x8 interface 11 and the Slimline x6 interface 12 are Slimline connectors, are connected with the Altra max processor 1, and are responsible for leading out RCA5_ H, RCA6_ H, RCA7_H signals of the Altra max processor 1.

3*PCIe x16 Riser7 is a custom designed RISER card, please refer to fig. 4, which has 3 golden fingers such as a power golden finger, a PCIe x16 golden finger, a PCIe x8 golden finger, 3 sliding interfaces and 3 standard PCIe x16 connectors, 3*PCIe x16 Riser7 is used for expanding 3 PCIe x16 slots. 3*PCIe x16 Riser7 in this embodiment is interconnected with the power interface, PCIe x16 slot interface 2 and PCIe x8 slot interface 3. The power golden finger provides power for 3 standard PCIe x16 slots P12V, P3V3 and P3V3_AUX. The lower 8 bits of the PCIe x16 golden finger provide a SLOT0 SLOT PCIe x16 signal lower 8 bits signal and the upper 8 bits of the PCIe x16 golden finger provide a SLOT1 SLOT PCIe x16 signal lower 8 bits signal. The PCIe x8 gold finger provides a SLOT2 SLOT PCIe x16 signal low 8 bits signal. The 3 SLOT interfaces provide SLOT0, SLOT1, SLOT2 SLOTs PCIe x16 signals high 8 bits signals, respectively.

3*PCIe x16 Riser13 and 3*PCIe x16 Riser7. 3*PCIe x16 Riser13 in this embodiment is interconnected with the power interface, PCIe x16 slot interface 8 and PCIe x8 slot interface 9. The power golden finger provides power for 3 standard PCIe x16 slots P12V, P3V3 and P3V3_AUX. The lower 8 bits of the PCIe x16 golden finger provide a SLOT0 SLOT PCIe x16 signal lower 8 bits signal and the upper 8 bits of the PCIe x16 golden finger provide a SLOT1 SLOT PCIe x16 signal lower 8 bits signal. The PCIe x8 gold finger provides a SLOT2 SLOT PCIe x16 signal low 8 bits signal. The 3 SLOT interfaces provide SLOT0, SLOT1, SLOT2 SLOTs PCIe x16 signals high 8 bits signals, respectively.

The principle of the device is as follows: the method comprises the steps that a Riser card suitable for an Altra max processor is designed independently, each 3 RCA port resources of the Altra max processor 1 are designed together in a combined mode, RCA2, RCA3 and RCA4 are combined together and 3*PCIe x16 Riser7 are inserted in pairs, and 3-standard PCIe x16 slot positions slot0, slot1 and slot2 are expanded; RCA5, RCA6, RCA7 are combined together and inserted in 3*PCIe x16 Riser13 pairs, extended 3-way mark PCIe x16 slot bits slot3, slot4, slot5.

Because Altra max processor 1 does not support x4+x4+x8, i.e., the lower bits in the application process of the upper bits x8 do not support x4+x4, or the upper bits in the application process of x4+x4 do not support x8 design, the split situation is avoided in the design application. Because the PCIe devices of x8 are wider than the ports of the x4 devices, the same number of x8 occupy more port resources than x4, the multi-port application resources of the x8 devices are easier to be limited, the configuration of the low-order x4+x4 is more reasonable to be sacrificed when the 2 conditions are combined, and the embodiment focuses on supporting the x8 devices.

The lower 8 bits of the RCA resource signals rca2_l, rca3_ L, RCA4_ L, RCA5 _3525_ L, RCA6_ L, RCA7_l of the Altra max processor 1 are all fixedly set to the "01" state, i.e. all lower 8 bits of the RCA are fixedly designed to PCIe x8. The high 8-bit RCA resource signals RCA2_H and RCA3_ H, RCA4_ H, RCA _ H, RCA6_ H, RCA _ H, RCA7_H of the Altra max processor 1 are led out by using a Slimline connector, the high 8-bit RCA signal can realize the application of an X16/X8/X4+ X4 port through an Slimline cable, the design also strengthens the resources of the X4+ X4 device, the selection of various configuration applications is facilitated, and the configuration supported by the device is shown in the table 1.

TABLE 1 PCIe resource configuration supported by Altra max processor

In the application of the X16 port, the RCA2, RCA3 and RCA4 high-8-bit signals of the Altra max processor 1 are connected to 3*PCIe x16 Riser7 through a Slimline cable, and at the moment, the configuration signals DIS_BP_RISER and DIS_X8_X16 of RCA_H are set to be '00', so that 3 PCIe X16 slots such as slot0, slot1 and slot2 can be expanded; the RCA5, RCA6 and RCA7 high-8-bit signals of the Altra max processor 1 are connected to 3*PCIe x16 Riser13 through a Slimline cable, so that 3 PCIe x16 slots such as slot3, slot4 and slot5 can be expanded, and the design can realize the design of expanding the maximum number of PCIe x16 ports by a single CPU of the Altra max processor.

In the X8 port application, RCA2, RCA3, RCA4 resource high 8-bit signals of the Altra max processor 1 are connected to a Riser card or other interface card of the X8 device through a Slimline cable, and at this time, the configuration signals of dis_bp_riser and dis_x8_x16 of rca_h are set to "01", and the RCA2-7 high-bit signals can expand 6 PCIe X8 slots. In addition, the invention 3*PCIe x16 Riser7 and 3*PCIe x16 Riser13 supports x8 devices to use under the condition that each PCIe x16 slot bit is not connected with a signal, and the total of high and low bit expansion can realize 12 PCIe x8 slots, so that the application condition realizes the design of the maximum number of the PCIe x8 ports of the CPU expansion.

In the application of the X4+x4 port, the RCA2, RCA3 and RCA4 resource high 8-bit signals of the Altra max processor 1 are connected to the Nvme hard disk backboard of the X4+x4 or other interface cards through a Slimline cable, the configuration signals of dis_bp_riser and dis_x8_x16 of the rca_h are set to be 11, and the RCA2-7 high-bit signals can extend the 12-bit Nvme hard disk or 12 PCIe X4 devices, so that the situation already covers the use requirements of multiple configurations of the server X4 devices.

The PCIe resource expansion device for the Altra max central processing unit of the embodiment has the following beneficial effects: (1) The PCIe resource is expanded to realize the maximum bandwidth design of each RCA interface PCIe X16, and the embarrassing scene that only the resources configured as X8+ X4+ X4 can meet the application is avoided; (2) The designed Altra max CPU server is flexibly switched with each RCA port resource X16/X8/X4, meanwhile, the occurrence of the configuration of X4+ X4+ X8 can be avoided, PCIe X16 and X8 ports are expanded to the greatest extent, and a single CPU can realize the expansion of 6X 16 ports/12X 8 ports/12X 4 ports of the Altra max CPU server; (3) The method can realize the maximum configuration requirement of PCIe resources of single-path/double-path PCIe resources of the Ampere platform server, has the advantage of flexible configuration, greatly improves the performance and practicability of the Ampere platform server, and improves the competitiveness of products.

In some implementations, the present invention also provides a server comprising an Altra max CPU 100, the Altra max CPU 100 extending PCIe resources using the apparatus described above.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. An Altra max central processor PCIe resource expansion device, said device comprising:

the first cable is used for detachably connecting the first interface with the high-eight-bit slot of the first PCIe x16 interface, the second cable is used for detachably connecting the second interface with the high-eight-bit slot of the second PCIe x16 interface, and the third cable is used for detachably connecting the third interface with the high-eight-bit slot of the third PCIe x16 interface;

when a first cable does not connect the first interface with the high-octet slot of the first PCIe x16 interface, the first cable is used for connecting the first interface with two PCIe x4 interfaces or one PCIe x8 interface;

2. The apparatus of claim 1, wherein the apparatus further comprises:

3. The apparatus of claim 1, wherein one of the fourth interface, the fifth interface, and the sixth interface is a PCIe x8 connector and the remaining two are an upper octet and a lower octet, respectively, of one PCIe x16 connector.

4. The apparatus of claim 1, wherein the first interface, the second interface, and the third interface are Slimline x8 interfaces.

5. The apparatus of claim 2, wherein one of the tenth interface, the eleventh interface, and the twelfth interface is a PCIe x8 connector and the remaining two are an upper octet and a lower octet, respectively, of one PCIe x16 connector.

6. The apparatus of claim 2, wherein the seventh interface, the eighth interface, and the ninth interface are Slimline x8 interfaces.

7. The apparatus of claim 1, wherein the Altra max cpu is configured to host an amp ere platform.

8. The apparatus of claim 2, wherein when a fourth cable does not connect the seventh interface with an upper octet of the fourth PCIe x16 interface, the fourth cable is to connect the seventh interface with two PCIe x4 interfaces or with one PCIe x8 interface;

9. A server comprising an Altra max central processor that extends PCIe resources using the apparatus of any one of claims 1-8.