CN115113447A - Array substrate and display panel - Google Patents
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- CN115113447A CN115113447A CN202210747644.1A CN202210747644A CN115113447A CN 115113447 A CN115113447 A CN 115113447A CN 202210747644 A CN202210747644 A CN 202210747644A CN 115113447 A CN115113447 A CN 115113447A
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- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 239000010409 thin film Substances 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 13
- 239000011148 porous material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 56
- 239000004973 liquid crystal related substance Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application provides an array substrate and a display panel, and relates to the technical field of display, wherein the array substrate comprises a common electrode layer, a middle layer and a conductive film which are sequentially arranged, a first signal line is arranged in the conductive film, a second signal line is arranged in the common electrode layer, and input signals of the first signal line and the second signal line are the same. The intermediate layer is provided with at least one through hole, and the first signal line and the second signal line are electrically connected through the through hole. This application passes through hole electric connection with the first signal line in the conductive film and the second signal line in the common electrode layer to solve the problem of display panel high-power consumption.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
With the continuous development of liquid crystal display screens, people are pursuing low-power-consumption and high-precision liquid crystal display screens, and low power consumption means that the electric energy consumed by the liquid crystal display screens is small. The power consumption of the lcd is generally related to the load in the display panel (e.g., the resistance and capacitance in the display panel), and the larger the load, the more power is consumed correspondingly.
Disclosure of Invention
In order to solve the above problem, the present application provides an array substrate and a display panel, which can reduce power consumption of the display panel.
In a first aspect, the application provides an array substrate, which comprises a common electrode layer, an intermediate layer and a conductive film, wherein the common electrode layer, the intermediate layer and the conductive film are sequentially arranged, a first signal line is arranged in the conductive film, a second signal line is arranged in the common electrode layer, and input signals of the first signal line and the second signal line are the same. The intermediate layer is provided with at least one through hole, and the first signal line and the second signal line are electrically connected through the through hole.
The application provides an array substrate, through set up the through-hole on the intermediate level to pass through-hole electric connection with the first signal line in the conducting film and the second signal line in the common electrode layer, make the resistance of first signal line and the resistance load of second signal line parallelly connected, reduced the total resistance load of two signal lines, thereby reduced the electric energy that array substrate consumed, and then reduced the consumption of the display panel who uses this array substrate. And the first signal line and the second signal line can be connected in a punching mode at the middle layer of the array substrate, more wiring lines do not need to be arranged on the surface of the array substrate, and the flatness of the surface of the array substrate is ensured.
In a possible design manner, the array substrate includes a plurality of pixel units arranged in an array, each pixel unit includes three sub-pixel units, and a through hole is provided in a region of the intermediate layer corresponding to each sub-pixel unit.
In a possible design manner, the array substrate includes a plurality of pixel units arranged in an array, each pixel unit includes three sub-pixel units, and a through hole is provided in an area of the middle layer corresponding to one of the sub-pixel units.
In one possible design, the sub-pixel unit provided with the through hole is a blue sub-pixel unit.
In a possible design manner, the array substrate further includes a plurality of data lines and a plurality of scan lines, the plurality of data lines and the plurality of scan lines intersect to define a plurality of sub-pixel units, the first signal line is a shielding signal line disposed above the data line, and the second signal line is a common electrode line.
In one possible design, the sub-pixel unit includes a thin film transistor and a pixel electrode, and the thin film transistor includes a gate electrode connected to the scan line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. In the area corresponding to the sub-pixel unit, the through hole is arranged on the side of the pixel electrode far away from the thin film transistor.
In one possible design, a side of the second signal line away from the pixel electrode is provided with a connecting portion protruding toward the gate line, and the through hole is disposed on the connecting portion.
In one possible design, the through hole is disposed away from the data line connected to the thin film transistor in the region corresponding to the sub-pixel unit. The first signal line is arranged on one data line adjacent to the data line connected with the thin film transistor and is electrically connected with the second signal line through the through hole.
In one possible design, the aperture of the through-hole is less than 20 microns.
In a second aspect, the present application further provides a display panel produced from the array substrate of the first aspect or any optional manner of the first aspect.
The construction of the present application and other objects and advantages thereof will be apparent from the following detailed description taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a display panel structure according to an embodiment of the present application;
fig. 2 is a first schematic view of an array substrate structure provided in an embodiment of the present application;
fig. 3 is a schematic view of a structure of an array substrate provided in the embodiment of the present application;
fig. 4 is a circuit diagram of a first signal line provided in an embodiment of the present application;
fig. 5 is a circuit schematic diagram of another first signal line provided in the embodiment of the present application;
fig. 6 is a circuit schematic diagram of still another first signal line provided in the embodiment of the present application;
fig. 7 is a schematic structural diagram of a sub-pixel unit provided in the embodiment of the present application.
Wherein, in the figures, the respective reference numerals:
1, an array substrate;
101, a glass substrate;
102, a common electrode layer; 1021, a second signal line;
103, an intermediate layer; 1031, a first insulating layer; 1032, a second insulating layer; 1033, a color resist layer; 1034, an organic planarization layer;
104, a conductive film; 1041, a first signal line;
105, a data line;
106, a scan line;
2, a liquid crystal layer;
3, a counter substrate;
4, a sub-pixel unit;
5, a thin film transistor; 501, a grid electrode; 502, a source; 503, a drain electrode;
6, pixel electrodes;
and 7, a connecting part.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description of the present application, it is to be understood that the terms "inner", "outer", "upper", "bottom", "front", "rear", and the like, if any, refer to an orientation or positional relationship, if any, that is solely for convenience in describing and simplifying the present application, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be taken as limiting the present application.
Currently, as shown in fig. 1, a liquid crystal display panel generally includes an array substrate 1, also referred to as a Thin Film Transistor (TFT) substrate 1, a liquid crystal layer 2, and a counter substrate 3, wherein the liquid crystal layer 2 is disposed between the array substrate 1 and the counter substrate 3. The opposite substrate 3 may be a Color filter substrate provided with a Color Filter (CF), or may be a substrate without a Color filter (in this case, the Color filter is disposed on the array substrate).
After the driving voltage is applied to the array substrate 1 and the opposite substrate 3, an electric field is formed between the array substrate 1 and the opposite substrate 3 to deflect the liquid crystal molecules, so that when light passes through the liquid crystal display panel, different light transmittances can be presented through the deflection of the liquid crystal molecules. By adjusting the electric field force between the array substrate 1 and the opposite substrate 3, the deflection angle of the liquid crystal molecules is adjusted, so that the liquid crystal layer 2 can accurately control the polarization direction of light.
As shown in fig. 2, the array substrate 1 generally includes: a glass substrate (i.e., a base substrate) 101, a common electrode layer 102, an intermediate layer 103, and a conductive film 104. It is understood that, in the manufacturing process of the liquid crystal display panel, a color-resist layer 1033 may be further disposed in the intermediate layer 103 by the COA technique. The intermediate layer 103 in this case may include a first insulating layer 1031 such as an amorphous silicon insulating layer (Gate SiNx α Si, GI), and a second insulating layer 1032 such as a silicon nitride insulating protective layer (PV), a color resist layer 1033, and an organic planarization layer (PFA) 1034, as shown in fig. 2. A metal layer, such as a source/drain electrode and a data line, is provided between the first insulating layer 1031 and the second insulating layer 1032. The color resist layer 1033 includes Red (R), Green (G), and Blue (B) color resists arranged in an array.
The conductive film 104 includes a plurality of pixel electrodes (respectively corresponding to each color resistor in the color resistor layer 1033, or respectively corresponding to each color resistor on the color filter substrate), and the plurality of pixel electrodes receive a driving voltage through a data line to form a driving electric field with a common electrode layer on the opposite substrate 3, so as to drive liquid crystal molecules above the pixel electrodes to deflect. And the pixel electrode and the common electrode layer on the glass substrate 101 may be coupled to form a storage capacitor, and when the data line is disconnected (i.e. the scan line in the display panel receives a low level signal and the data line stops inputting a driving voltage to the pixel electrode), the storage capacitor may discharge to enable the pixel electrode and the common electrode layer on the opposite substrate 3 to form an electric field, so as to enable the liquid crystal molecules to keep deflecting.
Due to the voltage on the data line, an electric field may be formed between the data line and the common electrode layer on the opposite substrate 3 in the region except the pixel electrode on the array substrate 1, so that the liquid crystal molecules above the data line are deflected, thereby generating light leakage. Therefore, a shield signal line DBS COM (data line BM Less common) signal line is generally prepared above the data line disposed in the array substrate 1 by a black matrix (DBS) free technology above the data line, and the DBS COM signal line is disposed in the conductive film 104. The voltage on the DBS COM signal line is controlled to be consistent with the voltage of the common electrode layer on the opposite side substrate 3, so that the voltage difference between the DBS COM signal line and the common electrode layer on the opposite side substrate 3 is zero, liquid crystal molecules above the DBS COM signal line are always kept in an undeflected state, and the problem that when the voltage difference exists between the data line and the common electrode layer on the opposite side substrate 3, the liquid crystal molecules above the data line deflect to generate light leakage is solved.
The common electrode layer 102 is provided with sub-common electrodes corresponding to the pixel electrodes in the conductive film 104, the sub-common electrodes are connected through Array Common (ACOM) signal lines, and receive external voltage through the ACOM signal lines, so that the corresponding pixel electrodes and the common electrodes are coupled to form storage capacitors. When the data line is disconnected (i.e. the scan line in the display panel receives a low-level signal and the data line stops inputting the driving voltage to the pixel electrode), the storage capacitor may provide the driving voltage to the pixel electrode by discharging.
When the display panel works, the storage capacitor is repeatedly charged and discharged, and current is generated in the charging and discharging process. When current flows through the ACOM signal line and the DBS COM signal line, the display panel has a certain power consumption due to the resistances of the ACOM signal line and the DBS COM signal line. Therefore, the application provides an array substrate and a display panel, and the power consumption of the display panel is reduced by reducing the resistance loads on the ACOM signal line and the DBS COM signal line.
An array substrate and a display panel provided by the present application are exemplarily described below with reference to the accompanying drawings.
Example one
As shown in fig. 3, for the array substrate 1 provided by the present application, the array substrate 1 includes a glass substrate 101, a common electrode layer 102, an intermediate layer 103, and a conductive film 104, which are sequentially disposed in a thickness direction, a first signal line 1041 is disposed in the conductive film 104, and a second signal line 1021 is disposed in the common electrode layer 102. The first signal line 1041 and the second signal line 1021 can be electrically connected through the through hole by providing the through hole on the intermediate layer 103.
The first signal line 1041 and the second signal line 1021 may be any two independent signal lines with the same input signal in the array substrate 1. The first signal line 1041 may be a shield signal line disposed above the data line, for example, the DBS COM signal line described above, and the second signal line may be a common electrode line, for example, the ACOM signal line described above. It is worth mentioning that the size of the through hole is far smaller than that of the sub-pixel unit, so that the influence on the light emitting effect of the sub-pixel unit in the using process and the display effect of the display panel when the size of the through hole is larger than that of the sub-pixel unit is avoided. For example, the size of the through hole may be set to be between several micrometers and tens of micrometers, which is less than twenty micrometers, and the size of the through hole is not particularly limited and may be designed according to the use scenario.
That is, in the array substrate 1 provided in the present application, two signal lines that are independent of each other and have the same input signal are connected to each other through the through hole provided in the intermediate layer, so that the resistance of the first signal line 1041 is connected in parallel with the resistance load of the second signal line 1021, thereby reducing the total resistance load of the two signals, and further reducing the power consumption of the display panel using the array substrate 1. The first signal line 1041 and the second signal line 1021 can be electrically connected by punching the middle layer 103 of the array substrate 1, and more wires do not need to be arranged on the surface of the array substrate, so that the flatness of the surface of the array substrate 1 is ensured.
It is understood that the array substrate 1 includes a display area, and the first signal line 1041 and the second signal line 1021 are provided with traces in the display area (hereinafter referred to as display area traces) and also provided with traces at the periphery of the display area (hereinafter referred to as peripheral traces). It is assumed that the resistive loads of the first signal line 1041 and the second signal line 1021 are divided according to the resolution of the display area, the display area routing, and the peripheral area routing. The resistive load on the peripheral trace of the first signal line 1041 is R1, and the resistive load on the peripheral trace of the second signal line 1021 is R2. If the resolution of the display area is X × Y, that is, the display area includes X × Y pixel units, each pixel unit includes three sub-pixel units (i.e., a red sub-pixel unit, a blue sub-pixel unit, and a green sub-pixel unit). The resistive load of the first signal line 1041 on the trace in each sub-pixel unit is R3, and the resistive load of the second signal line 1021 on the trace in each sub-pixel unit is R4.
It is understood that when the first signal line 1041 and the second signal line 1021 are not connected, as shown in the equivalent circuit of fig. 4, the respective resistive loads on the first signal line 1041 are connected in series, and the total resistive load R5 of the first signal line 1041 is:
R 5 ＝3*X*Y*R 3 +R 1
the respective resistive loads on the second signal line 1021 are connected in series, and the total resistive load R6 of the second signal line 1021 is:
R 6 ＝3*X*Y*R 4 +R 2
at this time, the total resistive load R7 on the first signal line 1041 and the second signal line 1021 is:
R 7 ＝3*X*Y(R 3 +R 4 )+R 1 +R 2
after the first signal line 1041 and the second signal line 1021 are connected through the vias, assuming that the vias are disposed on the middle layer 103 corresponding to each sub-pixel unit, and the traces of the first signal line 1041 and the second signal line 1021 in each sub-pixel unit are connected through the corresponding vias, the equivalent circuit diagram can be as shown in fig. 5, that is, the resistive loads R3 and R4 on the traces of the first signal line 1041 and the second signal line 1021 in each sub-pixel unit are connected in parallel, so that the total resistive load R8 on the first signal line 1041 and the second signal line 1021 is:
the total resistive load of the first signal line 1041 and the second signal line 1021 connected in this application is reduced compared to the total resistive load when the first signal line 1041 and the second signal line 1021 are not connected:
as shown in the above formula, the total resistive load of the first signal line 1041 and the second signal line 1021 in the array substrate 1 provided by the present application is smaller than the total resistive load when the first signal line 1041 and the second signal line 1021 are not connected, so that the total resistive load of the two signal lines is reduced by connecting the resistance of the first signal line 1041 and the resistive load of the second signal line 1021 in parallel, thereby reducing the electric energy consumed by the array substrate, and further reducing the power consumption of the display panel using the array substrate.
In one example, a via may be provided in a region of the intermediate layer 103 corresponding to one of the sub-pixel units, i.e., an equivalent circuit diagram of a resistive load may be as shown in fig. 6.
Optionally, in order to reduce the manufacturing complexity and improve the yield of the array substrate 1, a through hole may be disposed in a region of the intermediate layer 103 corresponding to a first sub-pixel unit of the plurality of pixel units.
It is understood that the plurality of pixel units may be pixel units in one area of the array substrate 1, or may be all pixel units in the array substrate 1, which is not specifically limited in this application.
For example, the first sub-pixel element may be a blue sub-pixel element. Since the transmittance of the blue sub-pixel unit is the smallest, the through holes are formed on the intermediate layer 103 corresponding to the blue sub-pixel unit, so that the influence on the array substrate 13 is the smallest, that is, the yield of the array substrate 1 is improved. The equivalent circuit diagram of the resistive load can be as shown in fig. 6, and the total resistive load R9 on the first signal line 1041 and the second signal line 1021 is:
compared to the total resistive load when the first signal line 1041 and the second signal line 1021 are not connected, the total resistive load of the first signal line 1041 and the second signal line 1021 connected in the present application is reduced by:
in one example, the array substrate 1 further includes a plurality of data lines 105 and a plurality of scan lines 106, and the plurality of data lines 105 and the plurality of scan lines 106 intersect to define a plurality of sub-pixel units 5. In the plurality of sub-pixel units 4 defined by the plurality of data lines 105 and the plurality of scan lines 106 crossing each other, each sub-pixel unit 4 may include a Thin Film Transistor (TFT) 5 and a pixel electrode 6 as shown in fig. 7. The thin film transistor 5 includes a gate electrode 501 connected to a scan line, a source electrode 502 connected to the data line 105, and a drain electrode 503 connected to the pixel electrode 5.
In this example, the through hole may be provided in the sub-pixel unit 4 on the side of the pixel electrode 6 remote from the thin film transistor 5.
Alternatively, in the corresponding sub-pixel unit region, a side of the second signal line 1021 remote from the pixel electrode 6 is provided with a connection portion 7 protruding toward the gate line, and a through hole may be provided on the connection portion 7. It is to be understood that the scanning line 106 is a signal line for controlling the gate electrode 501 of the thin film transistor 5, and thus may be referred to as a gate line. As shown in fig. 7, a through hole is disposed on the connecting portion 7, and the first signal line 1041 is electrically connected to the second signal line 1021 through the through hole.
In order to facilitate the provision of the protruding connecting portion 6 on the side of the second signal line 1021 remote from the pixel electrode 6, the gate line may be configured as shown in fig. 7, and the position of the gate line corresponding to the connecting portion 7 is protruded (i.e. bent) to provide a receiving space for the connecting portion 7, so as to avoid the influence on the control of the gate 501 of the tft 5 caused by the provision of the through hole after the connecting portion 7 is overlapped with the gate line.
Optionally, in the corresponding sub-pixel unit region, the through hole may also be disposed away from the data line 105 connected to the thin film transistor 5, at this time, the first signal line 1041 may be disposed on an adjacent data line 105 of the data line 105 connected to the thin film transistor 5, and the second signal line 1021 may be electrically connected to the first signal line 1041 through the through hole.
Alternatively, the through hole may be provided in an edge region of the display area, for example, in a pixel unit near the non-display area. It is to be understood that, when the through holes are provided at the edge positions, the through holes may be provided in the corresponding intermediate layer 103 in each sub-pixel unit 4 at the edge positions, or the through holes may be provided only in the corresponding intermediate layer 103 in any one sub-pixel unit 4 at the edge positions. The number of through holes provided at the edge position is not limited here.
It can be understood that the through holes are formed in the middle layer 103 corresponding to any one of the sub-pixel units 4 in the edge position, which reduces the complexity of manufacturing the through holes, and the through holes do not need to be formed in the display area, so that the yield of the display area, that is, the yield of the array substrate 1, is improved.
Alternatively, the through hole may be provided in a middle region of the display region.
Example two
The present application further provides a display panel, which includes the array substrate 1 according to the first embodiment.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate comprises a common electrode layer, an intermediate layer and a conductive film which are sequentially arranged, and is characterized in that a first signal line is arranged in the conductive film, a second signal line is arranged in the common electrode layer, and input signals of the first signal line and the second signal line are the same; the middle layer is provided with at least one through hole, and the first signal line and the second signal line are electrically connected through the through hole.
2. The array substrate of claim 1, wherein the array substrate comprises a plurality of pixel units arranged in an array, each pixel unit comprises three sub-pixel units, and the through hole is disposed in a region of the middle layer corresponding to each sub-pixel unit.
3. The array substrate of claim 1, wherein the array substrate comprises a plurality of pixel units arranged in an array, each pixel unit comprises three sub-pixel units, and the through hole is disposed in a region of the middle layer corresponding to one of the sub-pixel units.
4. The array substrate of claim 3, wherein the sub-pixel unit provided with the through hole is a blue sub-pixel unit.
5. The array substrate according to any one of claims 2 and 3, wherein the array substrate further comprises a plurality of data lines and a plurality of scan lines, the plurality of data lines and the plurality of scan lines intersecting to define a plurality of the sub-pixel units; the first signal line is a shielding signal line arranged above the data line, and the second signal line is a common electrode line.
6. The array substrate of claim 5, wherein the sub-pixel unit comprises a thin film transistor and a pixel electrode, the thin film transistor comprises a gate electrode connected with the scan line, a source electrode connected with the data line, and a drain electrode connected with the pixel electrode; in the area corresponding to the sub-pixel unit, the through hole is arranged on one side of the pixel electrode, which is far away from the thin film transistor.
7. The array substrate of claim 6, wherein a side of the second signal line away from the pixel electrode is provided with a connection portion protruding toward the gate line, and the through hole is provided on the connection portion.
8. The array substrate of claim 6, wherein the through hole is disposed away from the data line connected to the thin film transistor in a region corresponding to the sub-pixel unit;
the first signal line is arranged on an adjacent data line of the data lines connected with the thin film transistor and is electrically connected with the second signal line through the through hole.
9. The array substrate of any of claims 1-3, wherein the through-holes have a pore size of less than 20 microns.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN202210747644.1A CN115113447A (en) | 2022-06-29 | 2022-06-29 | Array substrate and display panel |
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| CN202210747644.1A CN115113447A (en) | 2022-06-29 | 2022-06-29 | Array substrate and display panel |
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| CN203883006U (en) * | 2014-06-12 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104460163A (en) * | 2014-12-25 | 2015-03-25 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105185791A (en) * | 2015-09-28 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN110082970A (en) * | 2019-04-09 | 2019-08-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN112925141A (en) * | 2021-01-29 | 2021-06-08 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN114415433A (en) * | 2022-03-14 | 2022-04-29 | 惠科股份有限公司 | Array substrate, display panel and display device |
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| CN203883006U (en) * | 2014-06-12 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN105185791A (en) * | 2015-09-28 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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