CN115101612B - High-speed PIN detector of double multiple quantum wells of silicon-based - Google Patents
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Abstract
A composite PIN detector structure of silicon-based double multi-quantum well comprises a P+ (1) - (4) region, an N+ (1) - (3) region, a deep N-well DNW and three layers of Si/Si 0.3 Ge 0.7 Strain quantum well, three-layer Si/Si 0.4 Ge 0.6 Strained quantum wells, intrinsic layers P-EPI and P-type substrates P-SUB. The deep N-well DNW divides the detector into a working diode and a shielding diode, increases the area for absorbing photons, shields slow diffusion carriers from the deep of the substrate, and improves the response speed. The P region and the N region of the finger are inserted to form a transverse electric field, so that the area of a depletion region is expanded, and photon absorption of a near surface is improved. The carrier transit distance is reduced. Three-layer Si/Si 0.3 Ge 0.7 The strained quantum well 1 confines carriers in a well in a lateral electric field with higher carrier mobility, three layers of Si/Si 0.4 Ge 0.6 The hole potential well formed by the strain quantum well 2 not only neutralizes most of slow diffusion electrons, but also limits the movement of the slow diffusion holes, thereby greatly improving the response speed of the device. The invention has higher responsivity and shorter response time while considering mechanical stability.
Description
Technical Field
The invention belongs to the technical field of semiconductor photoelectric detectors, relates to the technical field of silicon-based semiconductor PIN photoelectric detectors, and in particular relates to a silicon-based dual multi-quantum well high-speed PIN detector which can be suitable for high-speed detection application.
Background
With the development of optical communication technology, as a key receiving end device of an optical fiber communication system, a photodetector is developing towards high responsivity, wide frequency spectrum, high integration and high speed. In particular, with the increasing data capacity of optical communication systems, it is required to have a higher-speed photodetector at the receiving end to detect the optical signal. Meanwhile, in the existing optical wireless network, an integratable high-speed detector is also required to achieve high frequency of electromagnetic wave signals and maximum transmission of information capacity. In addition, the response speed of the photoelectric detector is also highly required in the communication data center and the microwave photonics research.
Among the many photodetectors, common detector materials are silicon and group III-V materials. Because of the higher process complexity, higher manufacturing cost of III-V materials, and difficulty in integration with CMOS circuitry. And the Si process is more mature and has low cost, and particularly, the integration level of the Si-based device and the CMOS system is higher. Silicon-based planar detectors are often the preferred choice in optoelectronic integrated systems.
In order to make the device better for high-speed detection applications, photodetectors have been developed in various structures such as APD photodetectors, spatially modulated photodetectors, micro-nano pore structure detectors, and the like. However, APD photodetectors have the inherent disadvantages of being noisy and having too high an operating voltage due to the presence of avalanche effects, which are difficult to integrate in CMOS systems. The spatial modulation type photoelectric detector has small responsivity due to the fact that the output photocurrent is the current difference between the light receiving diode and the light not receiving diode. The response wavelength of the micro-nano pore structure detector is sensitive to the light incident angle and the period size of the microstructure, and the actual detection is limited. The PIN photoelectric detector has no limitation, and the intrinsic I layer increases the area of the photon absorption area, so that the responsivity is ensured. And the response speed of the PIN photoelectric detector is faster because the carrier drift speed in the depletion region is faster than the diffusion speed of the diffusion region. Along with the maturity of HV-CMOS technology, the integration of the detection array and the CMOS system is realized, so that the PIN structure is selected as a basic structure to carry out the optimal design of the device.
To achieve high performance detection of silicon-based PIN detectors, several important issues are faced. Since the silicon forbidden bandwidth is 1.12eV, the cut-off wavelength of the silicon material is 1.1 μm. This limits the absorption of photons by the detector in the near infrared band. And the carrier mobility of silicon is low, which affects the response speed of the device. More importantly, since the monolithically integrated PIN detector adopts a planar vertical structure, the light absorption direction is the same as the carrier transport direction, which results in the phenomenon that the reduction of the transit distance is at the expense of light absorption, and the responsivity and the response speed are mutually restricted. These are all the problems that need to be solved in order to realize high-responsiveness and high-speed detection by the PIN detector which is integrated in a single chip.
Disclosure of Invention
The invention aims to solve the defect of the response time of the conventional PIN photoelectric detector, and provides a silicon-based double multi-quantum well high-speed PIN detector.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a high-speed PIN detector of silicon-based double multi-quantum well is characterized in that: the detector sequentially comprises a P-substrate P-SUB and Si/Si from bottom to top 0.4 Ge 0.6 A strain quantum well, a P-type intrinsic layer P-EPI and a deep N-well DNW;
the upper layer of the detector is transversely provided with a P+ (1) region, an N+ (1) region, a P+ (2) region, an N+ (2) region, a P+ (3) region, an N+ (3) region and a P+ (4) region in sequence, wherein the N+ (1) region, the P+ (2) region, the N+ (2) region, the P+ (3) region and the N+ (3) region are positioned in a deep N-well DNW;
Si/Si 0.3 Ge 0.7 the strained quantum well through deep N-well DNW is connected with a P+ (1) region, an N+ (1) region, a P+ (2) region, an N+ (2) region, a P+ (3) region, an N+ (3) region and a P+ (4) region in sequence.
Compared with the prior art, the invention has the beneficial effects that:
1. the deep N-well DNW divides a single PIN structure into a plurality of absorption region structures, namely, PD1, PD5 and PD8, forming a plurality of depletion regions, increasing the area of photoelectric conversion. The two P+ regions and the three N+ regions alternately arranged in the deep N well DNW form four absorption regions PD4, PD6, PD7 and PD9, so that the photon absorption area is increased. Compared with a PIN photoelectric detector with a traditional structure, the responsivity of the device is increased from 0.53A/W to 0.85A/W.
2. The deep N well DNW and the interdigital well region divide the PIN detector into working diodes PD4-PD9 at the upper end and a shielding diode PD1 at the lower end, so that slow diffusion carrier components generated in the deep part of the substrate are eliminated, and the components of fast carriers in the output photocurrent are increased. The inter-digitated well region inside the deep N-well DNW can reach the inter-digitated electrode faster due to the shorter distance of the lateral depletion region and the shorter carrier transit time. Compared with a PIN photoelectric detector with a common structure, the response time of the device is shortened from 312.05ps to 132.18ps.
3. Three layers of Si/Si in the middle of the finger well region 0.3 Ge 0.7 The strain multiple quantum well can form high-density two-dimensional carrier gas in which carriers are bound due to the finite field effect of the quantum well, so that the movement of the carriers is more concentrated, and Si 0.3 Ge 0.7 The carrier mobility of the device is higher than that of Si, so that a fast drift channel is formed in the interpolation well region, and the response time of the device is reduced.
4. Three layers of Si/Si at the bottom of the intrinsic I layer 0.4 Ge 0.6 The strained multiple quantum well forms an I-type quantum well, and can localize a large number of holes to form a hole potential well. Holes in the potential well are continuously recombined with slow diffusion electrons generated in the deep part of the substrate, the slow diffusion holes generated in the deep part of the substrate are blocked by using a deep potential barrier, the slow diffusion electrons and the slow diffusion holes in the output photocurrent are reduced, all optimization terms are combined, and finally the response time of the device is shortened to 68.27ps from 312.05ps, and the response speed is 4.57 times of the original response speed.
5. The adoption of multiple layers of high germanium components in the double multi-quantum well enables the response cut-off wavelength of the PIN photoelectric detector to be widened from 1100nm to 1812.5nm, so that the device has the near infrared wide-spectrum detection capability.
Drawings
FIG. 1 is a schematic diagram of a high-speed PIN detector with silicon-based double multi-quantum wells;
FIG. 2 is a diagram showing the connection of electrodes in a high-responsivity output mode provided by the invention;
FIG. 3 is a diagram showing the connection of electrodes in a high-speed output mode according to the present invention;
FIG. 4 is a detailed view of the structure of strained quantum wells (1) and (2) provided by the present invention;
FIG. 5 is a graph of the response provided by the present invention as a function of deep N-well DNW concentration;
FIG. 6 is a graph of the response provided by the present invention as a function of intrinsic layer P-EPI concentration;
FIG. 7 is a graph showing the response of the present invention as a function of the thickness of the intrinsic layer P-EPI;
FIG. 8 shows the response time and strain level as a function of Si provided by the present invention 1-x Ge x A graph of the variation of the medium Ge composition;
fig. 9 is a graph of response time and strain magnitude as a function of the number of quantum well layers provided by the present invention.
FIG. 10 is a graph comparing spectral response curves of a dual multi-quantum well PIN detector provided by the invention with a conventional normal PIN detector;
fig. 11 is a graph comparing response time curves of a dual multi-quantum well PIN detector provided by the invention and a conventional common PIN detector.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the invention, the deep N-well DNW divides the detector into the working diode and the shielding diode, thereby increasing the area for absorbing photons, shielding slow diffusion carriers from the deep part of the substrate and improving the response speed. The P region and the N region of the finger are inserted to form a transverse electric field, so that the area of a depletion region is expanded, and photon absorption of a near surface is improved. The carrier transit distance is reduced. Three-layer Si/Si 0.3 Ge 0.7 The strained quantum well 1 confines carriers in a well in a lateral electric field with higher carrier mobility, three layers of Si/Si 0.4 Ge 0.6 The hole potential well formed by the strain quantum well 2 not only neutralizes most of slow diffusion electrons, but also limits the movement of the slow diffusion holes, thereby greatly improving the response speed of the device. The inventionThe method has the advantages of high response and short response time while considering mechanical stability.
The first embodiment is as follows: the embodiment describes a silicon-based dual multi-quantum well high-speed PIN detector, which sequentially comprises a P-type substrate P-SUB and Si/Si from bottom to top 0.4 Ge 0.6 A strained quantum well 2, a P-type intrinsic layer P-EPI and a deep N-well DNW;
the upper layer of the detector is provided with a P+ (1) region, an N+ (1) region, a P+ (2) region, an N+ (2) region, a P+ (3) region, an N+ (3) region and a P+ (4) region in sequence in the transverse direction (width direction), wherein the N+ (1) region, the P+ (2) region, the N+ (2) region, the P+ (3) region and the N+ (3) region are positioned in a deep N well DNW;
Si/Si 0.3 Ge 0.7 the strained quantum well 1 is connected to the p+ (1), n+ (1), p+ (2), n+ (2), p+ (3), n+ (3) and p+ (4) regions in this order through the deep N-well DNW.
The second embodiment is as follows: the high-speed PIN detector with silicon-based double multiple quantum wells of the first embodiment has the widths of the P+ (1) region and the P+ (4) region of 0.5um-1um, the depths of the P+ (1) region and the P+ (4) region of 0.2um-0.25um, the doping types of the P-type doping and the doping concentration of 1 multiplied by 10 18 cm -3 -1×10 19 cm -3 . The depths of the P+ (1) region and the P+ (4) region are adjusted according to the DNW depth of the deep N well, so that the area of the vertical depletion region is as large as possible, and the light absorption area is increased. The doping concentration is chosen to be heavily doped to ensure good contact with the electrode.
And a third specific embodiment: the high-speed PIN detector with silicon-based double multi-quantum wells in one embodiment, wherein the DNW width of the deep N-well is 9.5um, the DNW depth is 0.3um-0.5um, the doping type is N-type doping, and the doping concentration is 5×10 15 cm -3 -1×10 16 cm -3 . The deep N well DNW and the P-type intrinsic layer P-EPI form a diode PD1, two part depletion regions of a PN junction and a PIN junction are formed, and the responsivity is improved. The device is divided into an upper working diode PD4-PD9 and a lower shielding diode PD1, and slow diffusion carrier components generated in the deep part of the substrate are eliminated. The component of the fast carrier in the output photocurrent is increased, and the response time of the device is shortened. The depth of the deep N-well DNW is based on the depletion region and the intrinsic layer I layer thicknessAnd the adjustment is carried out, so that the depletion region fills the whole intrinsic I layer as much as possible, and the light absorption area is increased. The doping concentration is chosen according to fig. 5 for parameters with shorter response times while ensuring high responsivity.
The specific embodiment IV is as follows: the high-speed PIN detector with silicon-based double multiple quantum wells of the embodiment of the invention is characterized in that the width of the P+ (2) region and the P+ (3) region inside the deep N-well DNW is 0.5um-1um, the depth is 0.2um-0.25um, the doping type is P-type doping, and the doping concentration is 1×10 18 cm -3 -1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The N+ (1), N+ (2) and N+ (3) regions have widths of 0.5um-1um, depths of 0.2um-0.25um, doping type of N-type doping, and doping concentration of 1×10 18 cm -3 -1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And the spacing between the N+ (1) region, the P+ (2) region, the N+ (2) region, the P+ (3) region and the N+ (3) region is 1um to 1.5um. The alternating formation of the diodes PD4, PD6, PD7, and PD9 with each other, respectively, reduces the drift distance of carriers and thus shortens the response time. And forms diodes PD5 and PD8 with the deep N-well DNW. Increasing the area of the depletion region in turn increases the absorption of photons, especially at the near surface of the device, improving the responsivity of the device. The depths of the p+ (2) region, the p+ (3) region, the n+ (1) region, the n+ (2) region, and the n+ (3) region are selected as in embodiment three.
Fifth embodiment: the silicon-based dual-multi-quantum-well high-speed PIN detector in one embodiment 0.3 Ge 0.7 The distance between the strain quantum well 1 and the surface of the detector is 0.1um-0.2um, and a three-layer periodic structure (three-layer Si/Si is adopted 0.3 Ge 0.7 Structure), ge is 0.7, si and Si 0.3 Ge 0.7 The thickness of (2) is 5nm-10nm, and the width is 11um; the Si/Si 0.3 Ge 0.7 The strained quantum well 1 is designed as Si and Si 0.3 Ge 0.7 And a three-layer periodic structure which grows alternately. So that the carriers are bound to form a high-density two-dimensional carrier gas therein, and the combination of the interdigital trap structure enables the movement of the carriers to be more concentrated and does not need to cross the potential barrier. Due to Si 0.3 Ge 0.7 The carrier mobility is higher and so the response time of the device is reduced. Si/Si 0.3 Ge 0.7 The composition of the strained quantum well 1 is selected according to fig. 8, the number of layers is selected according to fig. 9, and the response time is smaller for the case of ensuring good mechanical stability. Si and Si 0.3 Ge 0.7 The thickness is selected to be within the wavelength of the electron Debroil, so that the quantum confinement effect of the quantum well is ensured. Si/Si 0.3 Ge 0.7 The distance between the strain quantum well 1 and the surface of the detector is set to ensure that a carrier rapid drift channel formed by the strain quantum well is in a transverse depletion region.
Specific embodiment six: the high-speed PIN detector with silicon-based double multiple quantum wells of the embodiment of the invention, wherein the thickness of the intrinsic layer P-EPI is 2um-3um, the doping type is P-type doping, and the doping concentration is 1×10 15 cm -3 -5×10 15 cm -3 . The intrinsic layer P-EPI is an intrinsic absorption layer which is epitaxially grown on the P substrate P-SUB, so that photon absorption area of the device is increased, and responsivity of the detector is improved. And the drift motion duty ratio of carriers is increased, and the response time of the detector is shortened. The doping concentration of the intrinsic layer P-EPI is chosen according to fig. 6, the thickness is chosen according to fig. 7, a parameter that has a shorter response time while ensuring a high responsivity.
Seventh embodiment: the high-speed PIN detector of the silicon-based double multi-quantum well of the embodiment one comprises the following components in percentage by weight 0.4 Ge 0.6 The distance between the strain quantum well 2 and the surface of the detector is 2.15um, a three-layer periodic structure is adopted, the component of Ge is 0.6, the thickness of Si is 12nm-15nm, and Si 0.4 Ge 0.6 Is 5nm to 10nm thick; the Si/Si 0.4 Ge 0.6 The strained quantum well 2 is designed as Si and Si 0.4 Ge 0.6 The composition of germanium in the silicon-germanium alloy is selected to be 0.6, and the width of the silicon-germanium alloy and the germanium is 11um. And forming a hole potential well, recombining full-diffused electrons from the substrate, blocking the full-diffused holes and electrons from the substrate by a high barrier of the quantum well, and reducing slow-diffused electrons and slow-diffused holes in the output photocurrent so as to improve the response speed of the device. Si/Si 0.4 Ge 0.6 The composition of the strained quantum well 2 is selected according to FIG. 8, the number of layers is selected according to FIG. 9, in order to ensure good mechanical stabilityLower, response time smaller parameters. Si/Si 0.3 Ge 0.7 The distance between the strained quantum well 1 and the detector surface is selected according to the deep N-well DNW and the intrinsic layer thickness, so that the area of the depletion region is as large as possible, and the area for absorbing light is increased. Si has a thickness greater than the Debroglie wavelength of electrons to reduce the wave function coupling between barrier wells, si 0.4 Ge 0.6 The thickness of the well layer is smaller than the Debroglie wavelength to ensure the quantum confinement effect of the well layer.
Eighth embodiment: the high-speed PIN detector with silicon-based double multi-quantum wells of the first embodiment, wherein the P-type substrate has P-type doping with concentration of 5×10 18 cm -3 -5×10 19 cm -3 The substrate concentration is chosen to be 4 orders of magnitude greater than the intrinsic layer, reducing on-resistance to some extent.
Example 1:
program operating environment: windows 10, COMSOL5.5;
referring to fig. 1-9, an embodiment of the present invention provides a silicon-based dual multi-quantum well composite PIN detector structure, with an overall dimension of 11um long, 50um wide, and 3.2um high; the detector structure sequentially comprises an upper layer of P+ (1) region and P+ (4) region from top to bottom, a deep N-well DNW, wherein the interior of the deep N-well DNW is provided with a P+ (2) region, a P+ (3) region, an N+ (1) region, an N+ (2) region and an N+ (3) region, and three layers of Si/Si 0.3 Ge 0.7 The strain quantum well 1 penetrates through the deep N well DNW, the P-EPI of the P-type intrinsic layer below the upper layer and the three layers Si/Si 0.4 Ge 0.6 The strained quantum well 2, p-SUB. The detector structure comprises a P-type substrate P-SUB, a P-type intrinsic layer P-EPI on the P-type substrate, and three layers of P-doped Si/Si at the bottom of the intrinsic I layer 0.4 Ge 0.6 The strain multi-quantum well 2, a deep N-well DNW on the top of the intrinsic layer, two P+ regions and three N+ regions alternately arranged in the deep N-well DNW in an inserting finger mode, two P+ regions on the left side and the right side of the deep N-well DNW, and three layers of P-doped Si/Si in the middle of the P+ regions and the N+ regions 0.3 Ge 0.7 Strained multiple quantum well 1.
P-substrate P-SUB with doping concentration of 1×10 19 cm -3 . Epitaxially grown 2.2um P-type intrinsic layer P-EPI on substrate with doping concentration of 5×10 15 cm -3 Plays a role inIncreasing the photon absorption area. P-doped Si/Si of three layers at the bottom of the intrinsic I layer 0.4 Ge 0.6 Strained multiple quantum well 2, wherein the Si layer has a thickness of 15nm, si 0.4 Ge 0.6 The thickness of the layer is 10nm, slow diffusion electrons at the hole potential well recombination boundary are formed, and movement of the slow diffusion holes and electrons is limited to shorten the response time. Deep N-well DNW on top of intrinsic layer with width of 9.5um, depth of 0.38um, doping concentration of 5×10 15 cm -3 The slow diffusion carriers from the deep part of the substrate are shielded, the area of a depletion region is increased, and the photoelectric response of the device is improved. The P+ (2) region and the P+ (3) region, the N+ (1) region, the N+ (2) region and the N+ (3) region which are alternately arranged in the deep N-well DNW, the width of each well region is 0.5um, the depth is 0.25um, and the doping concentration is 1 multiplied by 10 19 cm -3 The interval between the two electrodes is 1.5um, so that a transverse depletion region is formed, and accelerated carriers are collected by the interdigital electrodes. The P+ (1) region and the P+ (4) region on the left and right sides of the deep N-well DNW. Each well region has a width of 0.5um and a depth of 0.25um. Three layers of P-doped Si/Si 0.2um from the detector surface 0.3 Ge 0.7 Strained multiple quantum well, wherein Si layer and Si 0.3 Ge 0.7 The thickness of the layer is 10nm, a carrier rapid drift channel with local effect is formed, and the response time is shortened.
Referring to fig. 2 and 3, there are provided electrode connection methods for a high-speed output mode and a high-responsivity output mode of a silicon-based dual multi-quantum well compound PIN detector structure, respectively. In FIG. 2, the N+ (1) region, the N+ (2) region and the N+ (3) region are connected with 5V reverse voltage to ensure the reverse bias operation of the diode, the P+ (1) region and the P+ (4) region are grounded, partial slow photo-generated carriers which are not shielded by the deep N well DNW are led out through a ground wire by leading out the ground, the P+ (2) region and the P+ (3) region are led out to be connected with an anode, and the fast photocurrent between the upper transverse electrode and the fast photocurrent of the PD4-PD9 after the lower shielding are output, so that the response time of the device is shortened. In fig. 3, the n+ (1), n+ (2) and n+ (3) regions are connected with 5V reverse voltage to ensure the reverse bias operation of the diode. And leading out the P+ (1) - (4) regions to be connected with the anode, and outputting all photocurrents of the shielded and unshielded PD1-PD9, so as to increase the responsivity of the device.
Referring to fig. 5 and 6, the calculation formula of the depletion region can be seen as follows:
wherein the charge quantity q is 1.6X10 -19 C，V D For the contact potential difference, the Boltzmann constant κ was 1.38X10 -23 J.K, temperature T of 300K, N A And N D The doping concentrations of the P region and the N region of the PN junction are respectively the intrinsic carrier concentration N i 1.5X10 10 cm -3 ，X D For depletion region width, the relative permittivity ε of silicon at room temperature was 11.9, and vacuum permittivity ε 0 8.85×10 -14 F/cm, reverse bias V was 5V.
As the doping concentration of the P and N regions increases, the width of the depletion region gradually decreases, which in turn results in reduced absorption of photons and lower responsivity, but as the depletion region decreases, the carrier transit distance decreases, resulting in a decrease in response time. The effect of the deep N-well DNW and intrinsic layer P-EPI doping concentration on detector responsivity and response time is therefore compromised, where the deep N-well DNW doping concentration is chosen to be 5X 10N-type doping 15 cm -3 The P-EPI doping concentration of the intrinsic layer is 5×10 of the P-type doping 15 cm -3 . The responsivity of the detector in the high responsivity output mode is improved from 0.42A/W to 0.85A/W. The response time in the high speed output mode is shortened from 316.49ps to 130.96ps.
Referring to fig. 1, the calculation from the depletion region calculation formula can be performed,
Ln＝LI-XD-L-L Q
wherein L is n To mask the depth of the N-well, 0.38um, L is calculated I Depth of intrinsic I layer, X D L is the free Cheng Yaowei nm of electrons in silicon, L is the width of the depletion region Q Is the total thickness of the well layer and the barrier layer in the multiple quantum well. This results in an underlying strained quantum well junctionIs configured at the edge of the fast diffusion region and at the top of the slow diffusion region. The whole intrinsic I layer is a depletion region, so that slow diffusion electrons are shielded under the condition of not reducing photon absorption area, and response time is shortened.
Referring to fig. 7, as the intrinsic layer thickness increases, the increase in the area of the intrinsic layer that absorbs photons results in an increase in responsivity, and similarly, an increase in the carrier transit distance results in an increase in response time, with the effect of the intrinsic layer thickness on the detector responsivity and response time being compromised, where the intrinsic layer thickness is selected to be 2.2um.
Referring to fig. 4 and 8, the fitting relation of the valence band order to the Ge composition due to the strained quantum well:
ΔE v ＝0.74·x
wherein x is a component of Ge, ΔE v Is the valence band offset. As the Ge composition increases, the valence band order of the two quantum wells increases, resulting in an enhancement of quantum confinement. The number of local carriers in the fast drift channel is increased by the strain quantum well 1, the number of local holes in the strain quantum well 2 is more, and the recombination of slow diffusion electrons is increased. And thus has a stronger effect on shortening the response time. From Si and Si 1-x Ge x The lattice mismatch and the pre-strain matrix of the alloy are known,
wherein esp is Si and Si 1-x Ge x Lattice mismatch of alpha Si1-xGex Is Si (Si) 1-x Ge x Lattice constant, alpha Si Is the lattice constant of Si. Epsilon is its pre-strain matrix. As the Ge composition increases, the lattice mismatch between adjacent periodically strained quantum wells increases, resulting in an increase in stress and thus strain. It is contemplated that the strain of the device in the engineering should be less than 5% of the device. Therefore, according to FIGS. 5 and 6, response time and stress are applied according to Ge compositionThe effect of the varying size is more preferably selected such that the Ge composition of the strained quantum well 1 is 0.7 and the Ge composition of the strained quantum well 2 is 0.6.
Referring to fig. 9, as the number of quantum well layers increases, localized carriers gradually accumulate, and the strained quantum wells (1) and (2) are also made more effective in shortening the response time. But the stress is gradually accumulated to generate misfit dislocation, so that the influence of the number of quantum well layers on the response time and the strain is considered, and the strain of the device is ensured to be less than 5%. More preferably, both strained quantum wells 1 and 2 are selected as 3-layer structures.
Referring to fig. 10 and 11, the cut-off wavelength of the composite PIN structure of the silicon-based double multi-quantum well is 1812.5nm, so that the effect of expanding the frequency spectrum width is achieved. The responsiveness is improved from 0.42A/W to 0.85A/W of the common structure, and the response time is shortened from 312.05ps to 68.27ps.
In this embodiment, the composite PIN structure of the silicon-based dual multi-quantum well is applied to the photodetector, and the response time and the responsivity of the composite structure and the dual-strain quantum well structure are optimized, so that two selectable modes of high responsivity and high-speed output are provided, and the composite PIN structure has good mechanical stability. The performance of the photodetector is very good.
The foregoing is merely illustrative embodiments of the present invention, and the present invention is not limited thereto, and any changes or substitutions that may be easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention.
Claims (8)
1. A high-speed PIN detector of silicon-based double multi-quantum well is characterized in that: the detector sequentially comprises a P-substrate P-SUB and Si/Si from bottom to top 0.4 Ge 0.6 A strain quantum well (2), a P-type intrinsic layer P-EPI and a deep N-well DNW;
the upper layer of the detector is transversely provided with a P+ (1) region, an N+ (1) region, a P+ (2) region, an N+ (2) region, a P+ (3) region, an N+ (3) region and a P+ (4) region in sequence, wherein the N+ (1) region, the P+ (2) region, the N+ (2) region, the P+ (3) region and the N+ (3) region are positioned in a deep N-well DNW, and the P+ (1) region and the P+ (4) region are positioned in a P-type intrinsic layer P-EPI;
Si/Si 0.3 Ge 0.7 the strained quantum well (1) is connected with the P+ (1), N+ (1), P+ (2), N+ (2), P+ (3), N+ (3) and P+ (4) regions in sequence through the deep N-well DNW.
2. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the width of the P+ (1) region and the P+ (4) region is 0.5um-1um, the depth is 0.2um-0.25um, the doping type is P-type doping, and the doping concentration is 1 multiplied by 10 18 cm -3 -1×10 19 cm -3 。
3. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the width of the DNW of the deep N well is 9.5um, the depth is 0.3um-0.5um, the doping type is N-type doping, and the doping concentration is 5 multiplied by 10 15 cm -3 -1×10 16 cm -3 。
4. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the width of the P+ (2) region and the P+ (3) region in the deep N-well DNW is 0.5um-1um, the depth is 0.2um-0.25um, the doping type is P-type doping, and the doping concentration is 1 multiplied by 10 18 cm -3 -1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The N+ (1), N+ (2) and N+ (3) regions have widths of 0.5um-1um, depths of 0.2um-0.25um, doping type of N-type doping, and doping concentration of 1×10 18 cm -3 -1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And the spacing between the N+ (1) region, the P+ (2) region, the N+ (2) region, the P+ (3) region and the N+ (3) region is 1um to 1.5um.
5. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: si/Si 0.3 Ge 0.7 The distance between the strain quantum well (1) and the surface of the detector is 0.1um-0.2um, and a three-layer periodic structure is adopted, si and Si 0.3 Ge 0.7 The thickness of (2) is 5nm-10nm and the width is 11um.
6. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the thickness of the intrinsic layer P-EPI is 2um-3um, the doping type is P-type doping, and the doping concentration is 1 multiplied by 10 15 cm -3 -5×10 15 cm -3 。
7. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the Si/Si 0.4 Ge 0.6 The distance between the strain quantum well (2) and the surface of the detector is 2.15um, a three-layer periodic structure is adopted, the thickness of Si is 12nm-15nm, and the thickness of Si is 0.4 Ge 0.6 The thickness of (2) is 5nm-10nm, and the width of both is 11um.
8. A silicon-based dual multi-quantum well high-speed PIN detector according to claim 1, wherein: the P-SUB doping type of the P-type substrate is P-type doping with the concentration of 5 multiplied by 10 18 cm -3 -5×10 19 cm -3 The substrate concentration is chosen to be 4 orders of magnitude greater than the intrinsic layer.
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| CN108538865A (en) * | 2018-04-27 | 2018-09-14 | 电子科技大学 | A kind of three photodetector of silicon substrate |
| CN111384196A (en) * | 2018-12-28 | 2020-07-07 | 哈尔滨工大华生电子有限公司 | Si/Si-based1-xGexQuantum well APD |
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| CN103872168A (en) * | 2014-03-06 | 2014-06-18 | 中国电子科技集团公司第三十八研究所 | Photoelectric detector for use in silicon-based photoelectric integrated circuit chip and manufacturing method thereof |
| CN108538865A (en) * | 2018-04-27 | 2018-09-14 | 电子科技大学 | A kind of three photodetector of silicon substrate |
| CN111384196A (en) * | 2018-12-28 | 2020-07-07 | 哈尔滨工大华生电子有限公司 | Si/Si-based1-xGexQuantum well APD |
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