CN115101010A - Display panel and display device - Google Patents

Abstract

The application provides a display panel and a display device. The display panel comprises a first display area and a second display area, the second display area is provided with a plurality of pixel units in an array mode, each pixel unit corresponds to one driving circuit, each row of pixel units are connected with the driving circuits through the same data line, the first display area comprises a transition area, the second display area comprises a hole digging area, each pixel unit comprises a second pixel unit located in the hole digging area, and the second pixel unit is connected with the driving circuits of the transition area; the data line comprises a first wiring, a patch cord and a second wiring, the first wiring is located in the second display area and bypasses the hole digging area, the second wiring is located in the transition area, the patch cord is connected with the first wiring and the second wiring respectively, and the connection position of the patch cord and the first wiring is located outside the hole digging area. This application will be able to avoid the data line to avoid causing mutual interference in normal pixel district roll-out, has promoted display panel's luminance homogeneity simultaneously.

Description

Display panel and display device

Technical Field

The present application relates to the field of display, and in particular, to a display panel and a display device.

Background

In order to improve the screen occupation ratio and the aesthetic degree of the Display device, more and more Display devices adopt an under-screen Camera (FDC) technology, and the FDC technology is to cancel an opening reserved for a front Camera on a screen and place the front Camera under the screen. However, when the front camera is disposed under the screen, in order to reduce the light from the screen to the outside entering the camera under the screen, the pixel circuits corresponding to the pixel units in the FDC hole are usually moved to the transition areas at both sides. And the data signals (data) are transversely wound to the transition region in the normal display region below the FDC hole and are connected with the pixel circuits corresponding to the pixel units in the FDC hole, and after signal writing is finished, the data signals are wound back to the pixels in the original row from the upper frame so as to finish signal writing to circuits above the FDC hole. However, the data signal routing is too long, which results in too large load, which is likely to cause poor dark fringe of the FDC hole region, and the data signal routing interferes with the pixel circuit in the normal display region.

Disclosure of Invention

In view of the foregoing, the present application provides a display panel and a display device.

The display panel of the embodiment of the application comprises a first display area and a second display area which are adjacent;

the second display area array is provided with a plurality of pixel units, each pixel unit corresponds to one driving circuit, each column of pixel units is connected with the driving circuit through the same data line, and the data line is used for providing data signals for the driving circuit;

the first display area comprises a transition area, the second display area comprises a hole digging area, the transition area is positioned on two sides of the hole digging area, the pixel unit comprises a second pixel unit positioned in the hole digging area, and the second pixel unit is connected with the driving circuit of the transition area;

the data line comprises a first wiring, a patch cord and a second wiring, the first wiring is located in the second display area and bypasses the hole digging area, the second wiring is located in the transition area, the patch cord is respectively connected with the first wiring and the second wiring, and the joint of the patch cord and the first wiring is located outside the hole digging area.

In some embodiments, the first trace and the patch cord are formed on different layers, and the patch cord is connected to the first trace through a via hole.

In some embodiments, the patch cord and the second trace are formed on different layers, and the patch cord is connected to the second trace through a via.

In some embodiments, the first trace and the second trace are formed on the same layer.

In some embodiments, the display panel includes a substrate, a driving layer, and a pixel layer, which are sequentially stacked, the data line and the driving circuit are formed on the driving layer, and the pixel unit is formed on the pixel layer;

the driving layer comprises a first conductive layer and a second conductive layer, the first wire and the second wire are formed on the second conductive layer, and the patch cord is formed on the first conductive layer.

In some embodiments, the driving layer further comprises:

a buffer layer on the substrate

The first insulating layer is positioned on the buffer layer and far away from the substrate base plate;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the first flat layer is positioned on one side, far away from the substrate, of the second insulating layer;

the second flat layer is positioned on one side, away from the substrate base plate, of the first flat layer;

the first conductive layer is located between the second insulating layer and the first flat layer, and the second conductive layer is located between the first flat layer and the second flat layer.

In some embodiments, the driving circuit is formed in the driving layer, and the driving circuit includes:

a driving transistor and a storage capacitor, the driving transistor including:

a first active layer on the substrate base plate;

the first grid electrode is positioned on one side, far away from the substrate, of the first active layer;

the first insulating layer is positioned on one side, far away from the substrate, of the first grid electrode;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the source electrode and the drain electrode are positioned on one side, far away from the substrate, of the second insulating layer and are electrically connected to the first active layer;

a storage capacitor, comprising:

the first electrode plate is positioned on the same layer as the first grid electrode; and

a second electrode plate located between the first insulating layer and the second insulating layer.

The pixel unit includes:

in some embodiments, a first electrode electrically connected to the source electrode;

the functional layer is positioned on one side of the first electrode, which is far away from the substrate;

and the second electrode is positioned on one side of the functional layer away from the substrate.

In some implementations, the pixel layer includes a pixel defining layer, a support layer, and an encapsulation layer that define the pixel cells.

In some embodiments, the patch cords of each of the data lines are equal in length.

In some embodiments, the spacing between the patch cords of adjacent data lines is equal.

In some embodiments, the first direction is the same as a column arrangement direction of the second pixel unit, and the second direction is the same as a row arrangement direction of the second pixel unit.

In some embodiments, the cored-out region is circular.

The display device provided by the embodiment of the application comprises the display panel of the embodiment.

In the display panel and the display device in this application, first walk the line through the data line that corresponds second pixel unit and be located the second display area and walk around digging the hole district, and walk the line setting at the transition district with the second, the rethread patchcord is digging the hole district outer junction first walk the line and is connected the second that is located the transition district and walk the line, avoided the data line to avoid rolling out at normal pixel district and causing mutual interference, display panel's luminance homogeneity has been promoted simultaneously, avoided the data line to avoid rolling out at first display area and causing mutual interference with first display area, and simultaneously, the length of data line can be effectively reduced, thereby avoid leading to the load too big because of the data line overlength, display panel's luminance homogeneity has been promoted, in addition, need not to account for the space of frame, display panel's screen occupation ratio has further been promoted.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic plan view of a display panel according to an embodiment of the present application.

FIG. 2 is an enlarged partial schematic view of some embodiments at II in FIG. 1.

FIG. 3 is an enlarged partial schematic view of certain embodiments at II in FIG. 1.

FIG. 4 is an enlarged partial schematic view of certain embodiments at II in FIG. 1.

Fig. 5 is an enlarged partial schematic view of some embodiments at V in fig. 2.

Fig. 6 is a schematic cross-sectional view of certain embodiments at VI in fig. 5.

Fig. 7 is a schematic cross-sectional view of certain embodiments at VII in fig. 1.

Fig. 8 is a schematic cross-sectional view of some embodiments at point VIII in fig. 4.

Description of the main element symbols:

the display device 100, the display panel 10, the first display area 11, the transition area 111, the second display area 12, the hole-digging area 121, the first pixel unit 311, and the second pixel unit 312;

the data line 15, the first wire 151, the patch cord 152 and the second wire 153;

a substrate 110, a driving layer 120, an active layer 1201, a gate dielectric layer 1202, a first insulating layer 1203, a second insulating layer 1204, a first flat layer 1205, a second flat layer 1206, a first conductive layer 1207, a second conductive layer 1208, a driving circuit 21, a driving transistor T0, a first active layer 1211, a first gate 1212, a source 1213, a drain 1214, a storage capacitor C1, a first electrode plate 1215, and a second electrode plate 1216;

a pixel layer 130, a pixel unit 31, a first pixel unit 311, a second pixel unit 312, a first electrode 131, a functional layer 132, a second electrode 133, a pixel defining layer 134, a supporting layer 135, an encapsulation layer 136, a first organic layer 1361, a second organic layer 1362;

and transparent conducting wires ITO.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Referring to fig. 1 to 4, the present disclosure provides a display panel 10, where the display panel 10 includes a first display area 11 and a second display area 12 adjacent to the first display area 11. The second display area 12 is provided with a plurality of pixel units 31 in an array, each pixel unit 31 corresponds to one driving circuit 21, each column of pixel units 31 is connected with the same data line 15 through the driving circuit 21, and the data line 15 is used for providing data signals to the driving circuit 21.

The first display area 11 comprises a transition area 111, the second display area 12 comprises a hole digging area 121, the transition area 111 is positioned at two sides of the hole digging area 121, the pixel unit 31 comprises a second pixel unit 312 positioned in the hole digging area 11, and the second pixel unit 312 is connected with the driving circuit 21 of the transition area 11;

the data line 15 includes a first trace 151, a patch cord 152 and a second trace 153, the first trace 151 is located in the second display area 12 and bypasses the hole digging area 121, the second trace 153 is located in the transition area 111, the patch cord 152 is connected to the first trace 151 and the second trace 153 respectively, and a connection position of the patch cord 152 and the first trace 151 is located outside the hole digging area 121.

The present application also provides a display device 100, and the display panel 10 provided in the embodiment of the present application can be applied to the display device 100 of the embodiment of the present application, that is, the display device 100 of the embodiment of the present application can display an image by the display panel 10 of the embodiment of the present application.

In the display panel 10 and the display device 100 of the embodiment of the application, the first wire 151 of the data line 15 corresponding to the second pixel unit 312 is located in the second display area 12 and bypasses the perforated area 121, the second wire 153 is disposed in the transition area 111, and the first wire 151 and the second wire 153 located in the transition area 121 are connected to the edge of the perforated area 121 through the transfer wire 152, so as to avoid mutual interference caused by the data line 15 turning out in the normal display area, improve the brightness uniformity of the display panel 10, avoid mutual interference caused by the data line 15 turning out in the first display area 11 and the first display area 11, and simultaneously, effectively reduce the length of the data line 15, thereby avoiding an overload caused by the data line 15 being too long, improve the brightness uniformity of the display panel 10, and improve the refresh rate of the display panel 10, and in addition, the space of the upper frame is not required to be occupied, and the screen occupation ratio of the display panel 10 is further improved.

With reference to fig. 1 to 8, the following description is provided with reference to the specific structures of the display panel 10 and the display device 100.

In some embodiments, the display device 100 may be a display device 100 capable of displaying images, such as a smart phone, a tablet computer, a smart band, a virtual reality device, a personal data terminal, a notebook computer, etc., but is not limited thereto, for example, in this embodiment, the display device 100 may be a mobile phone adopting an off-screen camera technology.

The display device 100 further includes an optical element disposed in the display panel 10, and the optical element may include, but is not limited to, a camera, an infrared sensor, a fingerprint sensor, and other photosensitive elements.

The display panel 10 may be an OLED display panel 10. The display panel 10 includes a display region formed with a plurality of pixel units 31, a plurality of driving circuits 21, and a plurality of data lines 15.

With further reference to fig. 1, a plurality of pixel units 31 are arranged in an array to form a plurality of rows and a plurality of columns. The pixel units 31 and the driving circuits 21 are multiple, one driving circuit 21 is correspondingly arranged on each pixel unit 31, the driving circuits 21 are used for driving the pixel units 31 to emit light, and the data lines 15 are sequentially arranged in the display area. The number of the data lines 15 is equal to the number of columns of the pixel units 31, that is, each column of the pixel units 31 is connected to the same data line 15 through the corresponding driving circuit 21. The data line 15 is used to transmit a data signal to the driving circuit 21 to make the driving circuit 21 drive the corresponding pixel unit 31 to emit light.

Further, the display area may be divided into a first display area 11 and a second display area 12, wherein the first display area 11 is adjacent to the second display area 12, for example, the first display area 11 may be located on both sides of the second display area 12, and the first display area 11 includes a transition area 111, the second display area 12 includes a hole-digging area 121, the transition area 111 is located on both sides of the hole-digging area 121, the hole-digging area 121 may be an under-screen image-capturing area, and the optical element is disposed in the hole-digging area 121. The hole digging region 121 may be a circle, a square, a drop, an ellipse, or other regular or irregular image, that is, the specific shape of the hole digging region 121 is not limited, and in this embodiment, the hole digging region 121 may be described as a circle, and the diameter of the hole digging region 121 is smaller than the width of the second display region 12.

The pixel unit 31 includes a first pixel unit 311 arranged in an array outside the cutout region 121 in the second display region 12 and a second pixel unit 312 arranged in an array in the cutout region 121. The driving circuits 21 corresponding to the first pixel units 31 are disposed in the second display region 12 except the cut-out regions 121, and the driving circuits 21 corresponding to the second pixel units 312 are disposed in the transition regions 111 in the first display regions 11 on both sides, that is, the driving circuits 21 are not disposed in the cut-out regions 121. It can be understood that, since the optical element is disposed in the hole digging region 121, if the driving circuit 21 is disposed in the hole digging region 121, the external light is blocked and transmitted to the optical element, so that the optical element cannot work normally. Therefore, the driving circuits 21 corresponding to the second pixel unit 312 are disposed in the transition regions 111 on both sides of the dug region 121.

With further reference to fig. 2, the data line 15 includes a first trace 151, a patch cord 152 and a second trace 153.

The first wires 151 of the data lines 15 are sequentially arranged in the second display area 12 along the second direction, and are all at least partially disposed around the transition area 111, the second wires 153 are located in the transition area 111, at least a portion of the first wires 151 are parallel to the second wires 153 and extend along the first direction, the patch cord 152 extends along the second direction, the first direction and the second direction can be perpendicular, that is, at least a portion of the first wires 151 and the patch cord 152 are disposed perpendicular. It should be noted that the first direction may be a column direction (or a vertical direction) of the pixel unit, and the second direction may be a row direction (or a horizontal direction) of the pixel unit.

The first wire 151 is used for connecting the driving circuit 21 of the first pixel unit 311, and the second wire 153 is used for connecting the driving circuit 21 corresponding to the second pixel unit 312. The patch cord 152 is a patch cord connecting the first trace 151 and the second trace 153, that is, the first trace 151 is connected to the second trace 153 in the transition region 111 through the patch cord 152.

Furthermore, the first wire 151 and the patch cord 152 are switched in the second display area 12 outside the hole 121, so as to prevent the data line 15 from being switched out in the first display area 11 and interfering with the data line 15 and the driving circuit 21 of the first display area 11, and at the same time, the length of the data line 15 can be effectively reduced, thereby preventing the load from being too large due to too long data line 15, and improving the brightness uniformity of the display panel 10.

Referring to fig. 5 and fig. 6, in some embodiments, the first trace 151 and the adapting line 152 are formed on different layers, and the adapting line 152 is connected to the first trace 151 through a via. That is, the first traces 151 and the vias 152 are formed on different film layers, and it can be understood that the first traces 151 extend along a first direction, the vias 152 extend along a second direction, and the first direction is perpendicular to the second direction, and the vias 152 may have an overlapping region with the first traces 151 of the other data lines 15. Therefore, by disposing the patch cord 152 and the first trace 151 at different layers, the intersection of the patch cord 152 and the first trace 151 at the overlapping area can be avoided. The interference of the patch cord 152 to the first trace 151 of the other data line 15 is avoided.

In some embodiments, the patch cord 152 and the second trace 153 are formed on different layers, and the patch cord 152 is connected to the second trace 153 through a via. That is, the patch cord 152 and the second trace 153 are formed on different film layers, and it is understood that the second trace 153 extends along a first direction, the patch cord 152 extends along a second direction, and the first direction is perpendicular to the second direction, so that there may be an overlapping region between the patch cord 152 and the patch cord 152 in the other data lines 15. Therefore, by arranging the patch cord 152 and the second trace 153 at different layers, the intersection of the patch cord 152 and the second trace 153 at the overlapping region can be avoided. The second traces 153 of the other data lines 15 are prevented from being interfered by the patch cord 152.

In some embodiments, the first trace 151 and the second trace 153 are formed on the same layer.

The same layer may refer to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then patterning the film layer by using the same mask plate through a one-step patterning process. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or portions located at the "same layer" are made of the same material and are formed through the same patterning process. As can be seen, by disposing the film layers of the first wire 151 and the second wire 153 on the same layer, the manufacturing process can be simplified, the manufacturing cost can be saved, and the manufacturing efficiency can be improved.

Referring to fig. 6, in some embodiments, the display panel 10 includes a substrate 110, a driving layer 120, and a pixel layer 130 stacked in sequence, a data line 15 and a driving circuit 21 are formed on the driving layer 120, the driving layer 120 includes a first conductive layer 1205 and a second conductive layer 1207, a first trace 151 and a second trace 153 are formed on the second conductive layer 1207, and a patch cord 152 is formed on the first conductive layer 1205.

Specifically, the substrate 110 may be a flexible substrate. The driving layer 120 includes a buffer layer 1201, a gate dielectric layer 1202, a first insulating layer 1203, a second insulating layer 1204, a first flat layer 1205, and a second flat layer 1206.

The buffer layer 1201 is formed on the substrate 110, the gate dielectric layer 1202 is located on a side of the buffer layer 1201 away from the substrate 110, the first insulating layer 1203 is located on a side of the gate dielectric layer 1202 away from the substrate 110, the second insulating layer 1204 is located on a side of the first insulating layer 1203 away from the substrate 110, the first flat layer 1205 is located on a side of the second insulating layer 1204 away from the substrate 110, and the second flat layer 1206 is located on a side of the first flat layer 1205 away from the substrate 110.

The driving layer 120 further includes a first conductive layer 1207 and a second conductive layer 1208 forming the data line 15, wherein the first conductive layer 1207 is positioned between the second insulating layer 1204 and the first flat layer 1205, and the second conductive layer 1208 is positioned between the first flat layer 1205 and the second flat layer 1206. The first trace 151 and the second trace 153 of the data line 15 are formed on the second conductive layer 1208, and the patch cord 152 is formed on the first conductive layer 1207.

Further, the first trace 151 includes a first transition portion, and the second trace 153 includes a second transition portion, where an orthographic projection of the first transition portion on the substrate base 110 at least partially overlaps an orthographic projection of the transition line 152 on the substrate base 110, and an orthographic projection of the second transition portion on the substrate base 110 at least partially overlaps an orthographic projection of the transition line 152 on the substrate base 110.

The first planarization layer 1205 is provided with a first via 12051 and a second via 12052, where the first via 12051 is located at the overlapping position of the first transition portion 1521 and the first trace 151, and the second via 12052 is located at the overlapping position of the second transition portion 1252 and the second trace 153. The first transition portion at least partially passes through the first via 12051 to connect with the patch cord 152, and the second transition portion at least partially passes through the second via 12052 to connect with the patch cord 152.

In some embodiments, a plurality of driving circuits 21 are formed on the driving layer 120, and at least one of the driving circuits 21 includes a driving transistor T0 and a storage capacitor C1.

The driving transistor T0 includes a first active layer 1211 disposed on the substrate 11, a first gate 1212 disposed on a side of the first active layer 1211 remote from the substrate 11, and a source 1213 and a drain 1214 disposed on a side of the first gate 1212 remote from the substrate 11 and electrically connected to the first active layer 1211. The first active layer 1211 is disposed on the same layer as the gate dielectric layer, for example, the source electrode 1213 and the drain electrode 1214 are electrically connected to the first active layer 1211 through vias penetrating the second insulating layer 1215, the first insulating layer 1214 and the gate dielectric layer 1212, respectively.

The storage capacitor C1 includes a first electrode plate 1221 located at the same layer as the first gate electrode 1212, and a second electrode plate 1222 located between the first insulating layer 1214 and the second insulating layer 1215. It should be understood that the storage capacitor C1 further includes a first insulating layer 1214 between the first electrode plate 1221 and the second electrode plate 1222.

Referring to fig. 7 or fig. 8, the pixel unit 31 may be a light emitting diode, such as an OLED. The pixel unit 31 includes a first electrode 131 (e.g., an anode), a functional layer 132 on a side of the first electrode 131 away from the substrate 11, and a second electrode 133 (e.g., a cathode) on a side of the functional layer 132 away from the substrate 11. Here, the functional layer 132 includes at least a light emitting layer, for example, an organic light emitting layer. In certain embodiments, the functional layer 132 may further include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

Further, referring to fig. 7, when the pixel unit 31 is the first pixel unit 311, the first electrode 131 can be electrically connected to the drain 1214 of the corresponding driving transistor T0 through the second planarization layer 1206 and the first planarization layer 1205.

Referring to fig. 8, the display panel 10 further includes a transparent electrode ITO disposed on a side of the second planarization layer 1206 away from the substrate base plate 110, and when the pixel unit 31 is the second pixel unit 312, the first electrode 131 can be electrically connected to the transparent electrode ITO, and electrically connected to the source 1213 of the driving transistor through the second planarization layer 1206 and the first planarization layer 1205 through the transparent electrode ITO. It is understood that, since the driving circuit of the second pixel unit 312 is located in the transition region 111, the first electrode of the second pixel unit 312 is not directly electrically connected to the drain 1214 of the corresponding driving transistor T0 through the second planarization layer 1206 and the first planarization layer 1205, and therefore, the connection of the second pixel unit 312 to the driving circuit 21 can be realized through the arrangement of the transparent electrode ITO.

In some embodiments, referring to fig. 7 or 8, the pixel layer 130 further includes a pixel defining layer 134 for defining a plurality of pixel units 31, a support layer 127, and an encapsulation layer 136.

For example, the pixel defining layer 134 has a plurality of openings corresponding to the plurality of pixel units 31, and the plurality of pixel units 31 are located in the plurality of openings. For example, the encapsulation layer 136 may include a thin film encapsulation layer. In some embodiments, the encapsulation layer 136 may include a first inorganic layer 1361, a second inorganic layer 1362, and an organic layer 1363 located between the first inorganic layer 1361 and the second inorganic layer 1362.

As some implementations, one or more of the second insulating layer 1215, the first insulating layer 1214, the gate dielectric layer 1212, the buffer layer 124, the planarization layer 125, the pixel defining layer 134, and the support layer 127 may include an organic insulating material such as polyimide, a resin material, or the like, or an inorganic insulating material including silicon oxide, silicon nitride, silicon oxynitride, or the like.

In some embodiments, the patch cords 152 of each data line 15 are equal in length.

Therefore, the load difference of the patch cord 152 of each data line 15 can be ensured to be minimum, and the brightness uniformity of the second display area 12 is improved.

In some embodiments, the patch cords 152 of adjacent data lines 15 are equally spaced.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims (14)

1. A display panel is characterized by comprising a first display area and a second display area which are adjacent;

the second display area array is provided with a plurality of pixel units, each pixel unit corresponds to one driving circuit, each column of pixel units is connected with the same data line through the driving circuit, and the data line is used for providing data signals for the driving circuit;

the first display area comprises a transition area, the second display area comprises a hole digging area, the transition area is positioned on two sides of the hole digging area, the pixel unit comprises a second pixel unit positioned in the hole digging area, and the second pixel unit is connected with the driving circuit of the transition area;

the data line comprises a first wiring, a patch cord and a second wiring, the first wiring is located in the second display area and bypasses the digging hole area, the second wiring is located in the transition area, the patch cord is connected with the first wiring and the second wiring respectively, and the joint of the patch cord and the first wiring is located outside the digging hole area.

2. The display panel according to claim 1, wherein the first trace and the patch cord are formed on different layers, and the patch cord is connected to the first trace through a via.

3. The display panel according to claim 2, wherein the patch cord and the second trace are formed on different layers, and the patch cord is connected to the second trace through a via.

4. The display panel according to claim 3, wherein the first traces and the second traces are formed on a same layer.

5. The display panel according to claim 4, wherein the display panel comprises a base substrate, a driving layer, and a pixel layer, which are sequentially stacked, the pixel unit being formed in the pixel layer;

the driving layer comprises a first conducting layer and a second conducting layer, the first wiring and the second wiring are formed on the second conducting layer, and the patch cord is formed on the first conducting layer.

6. The display panel of claim 5, wherein the driving layer further comprises:

a buffer layer on the substrate base plate;

the gate dielectric layer is positioned on one side of the buffer layer, which is far away from the substrate base plate;

the first insulating layer is positioned on one side, far away from the substrate, of the gate dielectric layer;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the first flat layer is positioned on one side, far away from the substrate, of the second insulating layer;

the second flat layer is positioned on one side, away from the substrate base plate, of the first flat layer;

the first conductive layer is located between the second insulating layer and the first planar layer, and the second conductive layer is located between the first planar layer and the second planar layer.

7. The display panel according to claim 5, wherein the driving circuit is formed in the driving layer, and the driving circuit comprises:

a driving transistor and a storage capacitor, the driving transistor including:

a first active layer on the substrate base plate;

the first grid electrode is positioned on one side, far away from the substrate, of the first active layer;

the first insulating layer is positioned on one side, far away from the substrate, of the first grid electrode;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the source electrode and the drain electrode are positioned on one side, far away from the substrate, of the second insulating layer and are electrically connected to the first active layer;

a storage capacitor, comprising:

the first electrode plate is positioned on the same layer as the first grid electrode; and

a second electrode plate located between the first insulating layer and the second insulating layer.

8. The display panel according to claim 7, wherein the pixel unit comprises:

a first electrode electrically connected to the source electrode;

the functional layer is positioned on one side of the first electrode, which is far away from the substrate;

and the second electrode is positioned on one side of the functional layer away from the substrate.

9. The display panel of claim 5, wherein the pixel layer comprises a pixel definition layer defining the pixel unit, a support layer, and an encapsulation layer.

10. The display panel according to claim 1, wherein the pixel units further include first pixel units arranged in an array outside the excavated area of the second display area, the first wires are connected to the driving circuits of the first pixel units, and the second wires are connected to the driving circuits of the second pixel units.

11. The display panel of claim 1, wherein the patch cords of each of the data lines are equal in length.

12. The display panel according to claim 1, wherein the patch cord of the adjacent data lines are equally spaced.

13. The display panel of claim 1, wherein the hollowed area comprises one of a circle, a square, or a drop shape.

14. A display device comprising the display panel of any one of claims 1 to 13, and an optical element on a non-display side of the display panel, wherein an orthographic projection of the optical element on the display panel at least partially overlaps the cutout region.

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