CN115101010A - Display panel and display device - Google Patents

Abstract

The present application provides a display panel and a display device. The display panel includes a first display area and a second display area. The second display area array is provided with a plurality of pixel units, each pixel unit corresponds to a driving circuit, and each column of pixel units is connected to the driving circuit through the same data line. It includes a transition area, the second display area includes a digging area, the pixel unit includes a second pixel unit located in the digging area, and the second pixel unit is connected with the driving circuit of the transition area; Two wirings, the first wiring is located in the second display area and bypasses the hole digging area, the second wiring is located in the transition area, the patch cords are respectively connected to the first routing and the second routing, and the patching cable is connected to the first routing The connection of the lines is outside the cutout area. The present application can avoid mutual interference caused by the data lines being turned out in the normal pixel area, and at the same time, the brightness uniformity of the display panel can be improved.

Description

Display panels and display devices

technical field

The present application relates to the field of display, and in particular, to a display panel and a display device.

Background technique

In order to improve the screen-to-body ratio and aesthetics of display devices, more and more display devices use Full Display with Camera (FDC) technology. The front camera is built into the bottom of the screen. However, when the front camera is placed under the screen, in order to reduce the entry of light from the screen that affects the outside world into the under-screen camera, the pixel circuit corresponding to the pixel unit in the FDC hole is usually moved to the transition area on both sides. The data signal (data) is wound horizontally in the normal display area under the FDC hole to the transition area and connected to the pixel circuit corresponding to the pixel unit in the FDC hole. signal write to the circuit above the area. However, in this way, the data signal wiring is too long, resulting in an excessive load, which is likely to cause poor dark lines in the column where the FDC hole area is located, and the data signal wiring interferes with the pixel circuit in the normal display area.

SUMMARY OF THE INVENTION

In view of this, the present application provides a display panel and a display device.

The display panel of the embodiment of the present application includes an adjacent first display area and a second display area;

The second display area array is provided with a plurality of pixel units, each of the pixel units corresponds to a driving circuit, and the pixel units in each column are connected to the driving circuit through the same data line, and the data line is used to connect to the driving circuit. the drive circuit provides data signals;

The first display area includes a transition area, the second display area includes a punching area, the transition area is located on both sides of the punching area, and the pixel unit includes a second pixel unit located in the punching area , the second pixel unit is connected to the drive circuit of the transition region;

The data line includes a first line, an adapter line, and a second line, the first line is located in the second display area and bypasses the digging area, and the second line is located in the transition area, the patch cords are respectively connected to the first routing wires and the second routing wires, and the connection between the patch cords and the first routing wires is located outside the digging area.

In some embodiments, the first trace and the patch wire are formed on different layers, and the patch wire is connected to the first trace through a via hole.

In some embodiments, the patch wire and the second trace are formed on different layers, and the patch wire is connected to the second trace through a via hole.

In some embodiments, the first trace and the second trace are formed on the same layer.

In some embodiments, the display panel includes a base substrate, a driving layer and a pixel layer stacked in sequence, the data line and the driving circuit are formed on the driving layer, and the pixel unit is formed on the pixel Floor;

The driving layer includes a first conductive layer and a second conductive layer, the first wiring and the second wiring are formed on the second conductive layer, and the transition wire is formed on the first conductive layer.

In some embodiments, the driver layer further includes:

a buffer layer on the base substrate

a first insulating layer located on the buffer layer away from the base substrate;

a second insulating layer on the side of the first insulating layer away from the base substrate;

a first flat layer on the side of the second insulating layer away from the base substrate;

a second flat layer on the side of the first flat layer away from the base substrate;

The first conductive layer is located between the second insulating layer and the first planarization layer, and the second conductive layer is located between the first planarization layer and the second planarization layer.

In some embodiments, the driver circuit is formed on the driver layer, and the driver circuit includes:

A drive transistor and a storage capacitor, the drive transistor includes:

a first active layer on the base substrate;

a first gate on the side of the first active layer away from the base substrate;

a first insulating layer on the side of the first gate away from the base substrate;

a second insulating layer on the side of the first insulating layer away from the base substrate;

a source electrode and a drain electrode located on the side of the second insulating layer away from the base substrate and electrically connected to the first active layer;

Storage capacitors, including:

a first electrode plate on the same layer as the first grid; and

The second electrode plate is located between the first insulating layer and the second insulating layer.

The pixel unit includes:

In certain embodiments, a first electrode, the first electrode is electrically connected to the source;

a functional layer on the side of the first electrode away from the base substrate;

A second electrode located on the side of the functional layer away from the base substrate.

In certain embodiments, the pixel layer includes a pixel defining layer, a support layer, and an encapsulation layer that define the pixel unit.

In some embodiments, the patch cords of each of the data lines are of equal length.

In some embodiments, the spacing between the patch lines of the adjacent data lines is equal.

In some embodiments, the first direction is the same as the column arrangement direction of the second pixel unit, and the second direction is the same as the row arrangement direction of the second pixel unit.

In certain embodiments, the cutout area is circular.

The display device provided by the embodiment of the present application includes the display panel of the above-mentioned embodiment.

In the display panel and the display device in the present application, the first wiring of the data line corresponding to the second pixel unit is located in the second display area and bypasses the digging area, and the second wiring is arranged in the transition area, and then The first wiring is connected outside the digging area and the second wiring in the transition area is connected by the patch wire, which avoids the mutual interference caused by the data lines being transferred out in the normal pixel area, and at the same time improves the brightness uniformity of the display panel and avoids the This prevents the data lines from being rotated out of the first display area and causing mutual interference with the first display area. At the same time, the length of the data lines can be effectively reduced, so as to avoid excessive load caused by too long data lines, and improve the display panel’s performance. Brightness uniformity, in addition, does not need to occupy the space of the upper frame, which further improves the screen ratio of the display panel.

Additional aspects and advantages of the present application will be set forth, in part, from the following description, and in part will become apparent from the following description, or may be learned by practice of the present application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic plan view of a display panel according to an embodiment of the present application.

FIG. 2 is a partial enlarged schematic view of some embodiments at II in FIG. 1 .

FIG. 3 is a partial enlarged schematic view of some embodiments at II in FIG. 1 .

FIG. 4 is a partial enlarged schematic view of some embodiments at II in FIG. 1 .

FIG. 5 is a partial enlarged schematic view of some embodiments at V in FIG. 2 .

FIG. 6 is a schematic cross-sectional view of certain embodiments at VI in FIG. 5 .

FIG. 7 is a schematic cross-sectional view of some embodiments at VII in FIG. 1 .

FIG. 8 is a schematic cross-sectional view of certain embodiments at VIII in FIG. 4 .

Description of main component symbols:

The display device 100, the display panel 10, the first display area 11, the transition area 111, the second display area 12, the digging area 121, the first pixel unit 311, and the second pixel unit 312;

Data line 15, first line 151, transfer line 152, second line 153;

Base substrate 110, driving layer 120, active layer 1201, gate dielectric layer 1202, first insulating layer 1203, second insulating layer 1204, first planarization layer 1205, second planarization layer 1206, first conductive layer 1207, The second conductive layer 1208, the driving circuit 21, the driving transistor T0, the first active layer 1211, the first gate 1212, the source 1213, the drain 1214, the storage capacitor C1, the first electrode plate 1215, the second electrode plate 1216 ;

Pixel layer 130, pixel unit 31, first pixel unit 311, second pixel unit 312, first electrode 131, functional layer 132, second electrode 133, pixel defining layer 134, support layer 135, encapsulation layer 136, first organic layer 1361, second organic layer 1362;

Transparent wire ITO.

Detailed ways

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present application, and should not be construed as a limitation on the present application.

In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", " rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc., or The positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as a limitation on this application. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as "first", "second" may expressly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the application. Furthermore, this application may repeat reference numerals and/or reference letters in different instances for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, this application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

Referring to FIGS. 1-4 , an embodiment of the present application provides a display panel 10 . The display panel 10 includes a first display area 11 and a second display area 12 adjacent to the first display area 11 . The second display area 12 is provided with a plurality of pixel units 31 in an array, each pixel unit 31 corresponds to a driving circuit 21 , and each column of pixel units 31 is connected to the same data line 15 through the driving circuit 21 , and the data line 15 is used to connect to the driving circuit 21 provide data signals.

The first display area 11 includes a transition area 111, the second display area 12 includes a hole-digging area 121, the transition area 111 is located on both sides of the hole-digging area 121, the pixel unit 31 includes a second pixel unit 312 located in the hole-digging area 11, the second The pixel unit 312 is connected to the driving circuit 21 of the transition area 11;

The data line 15 includes a first line 151 , an adapter line 152 and a second line 153 . The first line 151 is located in the second display area 12 and bypasses the digging area 121 , and the second line 153 is located in the transition area 111 . The wiring 152 is respectively connected to the first wiring 151 and the second wiring 153 , and the connection between the transfer wiring 152 and the first wiring 151 is located outside the digging area 121 .

The present application further provides a display device 100, and the display panel 10 provided by the embodiment of the present application can be applied to the display device 100 of the embodiment of the present application, that is, the display device 100 of the embodiment of the present application can be implemented by the present application The display panel 10 of the mode performs image display.

In the display panel 10 and the display device 100 according to the embodiment of the present application, the first wiring 151 of the data line 15 corresponding to the second pixel unit 312 is located in the second display area 12 and bypasses the digging area 121 , and the second The traces 153 are arranged in the transition area 111, and are then connected to the first traces 151 and the second traces 153 located in the transition area 121 at the edge of the digging area 121 through the transition wires 152, so as to prevent the data traces 15 from being displayed normally. The switching out of the first display area 11 causes mutual interference, and at the same time, the brightness uniformity of the display panel 10 is improved, and the data line 15 is prevented from being rotated out of the first display area 11 and causing mutual interference with the first display area 11, and at the same time, the data can be effectively reduced. The length of the line 15 is reduced, so as to avoid excessive load caused by the long data line 15, and improve the brightness uniformity of the display panel 10. Since the refresh rate of the display panel 10 is improved, in addition, it does not need to occupy the space of the upper frame, which further improves the The screen ratio of the display panel 10 .

Please further refer to FIG. 1 to FIG. 8 , and the specific structures of the display panel 10 and the display device 100 will be described below.

In some embodiments, the display device 100 may be a smart phone, a tablet computer, a smart bracelet, a virtual reality device, a personal data terminal, a notebook computer, etc. that can display images, but is not limited thereto, for example, in In this embodiment, the display device 100 may be described by taking a mobile phone using an under-screen camera technology as an example.

The display device 100 also includes optical elements disposed in the display panel 10 , and the optical elements may include but are not limited to photosensitive elements such as cameras, infrared sensors, and fingerprint collectors.

The display panel 10 may be an OLED display panel 10 . The display panel 10 includes a display area in which a plurality of pixel units 31 , a plurality of driving circuits 21 and a plurality of data lines 15 are formed.

Please further refer to FIG. 1 , a plurality of pixel units 31 are arranged in an array to form multiple rows and multiple columns. Each of the pixel units 31 and the driving circuits 21 includes a plurality of pixel units 31 . Each pixel unit 31 is provided with a corresponding driving circuit 21 . The driving circuit 21 is used to drive the pixel units 31 to emit light. The number of data lines 15 is equal to the number of columns of pixel units 31 , that is, each column of pixel units 31 is connected to the same data line 15 through a corresponding driving circuit 21 . The data line 15 is used for transmitting a data signal to the driving circuit 21 so that the driving circuit 21 drives the corresponding pixel unit 31 to emit light.

Further, the display area can be divided into a first display area 11 and a second display area 12, wherein the first display area 11 is adjacent to the second display area 12, for example, the first display area 11 can be located in the second display area 12 and the first display area 11 includes a transition area 111, the second display area 12 includes a digging area 121, the transition area 111 is located on both sides of the digging area 121, and the digging area 121 can be an under-screen camera area, The optical element is arranged in the digging area 121 . The hole-digging area 121 may be in the shape of a circle, a square, a droplet, an ellipse, or other regular or irregular images, that is, the specific shape of the hole-digging area 121 is not limited. In this embodiment, the hole-digging area 121 may be A circle is used for illustration, and the diameter of the digging area 121 is smaller than the width of the second display area 12 .

The pixel unit 31 includes a first pixel unit 311 arranged in an array outside the hole area 121 in the second display area 12 and a second pixel unit 312 arranged in the hole area 121 in an array. The driving circuit 21 corresponding to the first pixel unit 31 is arranged in the second display area 12 outside the hole area 121 , and the driving circuit 21 corresponding to the second pixel unit 312 is arranged in the transition area 111 in the first display area 11 on both sides. , that is, the driving circuit 21 is not arranged in the digging area 121 . It can be understood that since the optical element is disposed in the hole-drilling region 121 , if the driving circuit 21 is arranged in the hole-drilling region 121 , it will block the transmission of external light to the optical element, resulting in the failure of the optical element to work normally. Therefore, the driving circuit 21 corresponding to the second pixel unit 312 is disposed in the transition region 111 on both sides of the hole-drilling region 121 .

Please further refer to FIG. 2 , the data line 15 includes a first wiring 151 , an adapter wiring 152 and a second wiring 153 .

The first traces 151 of the plurality of data lines 15 are sequentially arranged in the second display area 12 along the second direction, and are at least partially disposed around the transition area 111 , and the second traces 153 are located in the transition area 111 . The line 151 is at least partially parallel to the second wiring 153 and extends along the first direction, and the patch cord 152 extends along the second direction. The first direction and the second direction may be perpendicular, that is, the first wiring 151 is at least partially And the patch cord 152 is arranged vertically. It should be noted that the first direction may be the column direction (or vertical direction) of the pixel unit, and the second direction may be the row direction (or horizontal direction) of the pixel unit.

The first wiring 151 is used to connect the driving circuit 21 of the first pixel unit 311 , and the second wiring 153 is used to connect the driving circuit 21 corresponding to the second pixel unit 312 . The patch cord 152 is a patch cord connecting the first trace 151 and the second trace 153 , that is, the first trace 151 is connected to the second trace 153 located in the transition area 111 through the patch cord 152 .

Further, the first traces 151 and the transition wires 152 are switched in the second display area 12 outside the hole-drilling area 121 , so that the data lines 15 are prevented from being switched out of the first display area 11 and connected to the first display area 11 . The long data lines 15 and the driving circuit 21 interfere with each other, and at the same time, the length of the data lines 15 can be effectively reduced, thereby avoiding excessive load caused by the data lines 15 being too long, and improving the brightness uniformity of the display panel 10 .

Referring to FIG. 5 and FIG. 6 , in some embodiments, the first trace 151 and the patch wire 152 are formed on different layers, and the patch wire 152 is connected to the first trace 151 through a via hole. That is, the first trace 151 and the patch wire 152 are formed in different layers. It can be understood that the first trace 151 extends along the first direction, the patch wire 152 extends along the second direction, and the first direction is the same as the first direction. The second direction is vertical, and the transition line 152 and the first traces 151 of the other data lines 15 have an overlapping area. Therefore, by arranging the patch cords 152 and the first traces 151 on different layers, the intersection of the patch cords 152 and the first traces 151 can be avoided at the overlapping area. Interference with the first traces 151 of the other data lines 15 is avoided by the patch cords 152 .

In some embodiments, the patch wire 152 and the second trace 153 are formed on different layers, and the patch wire 152 is connected to the second trace 153 through a via hole. That is, the patch cords 152 and the second traces 153 are formed in different film layers. It can be understood that the second traces 153 extend along the first direction, the patch cords 152 extend along the second direction, and the first direction and the The second direction is vertical. Therefore, the patch cord 152 may have an overlapping area with the patch cord 152 in other data lines 15 . Therefore, by arranging the patch cords 152 and the second traces 153 on different layers, the intersection of the patch cords 152 and the second traces 153 can be avoided at the overlapping area. Interference with the second traces 153 of the other data lines 15 is avoided by the patch cords 152 .

In some embodiments, the first traces 151 and the second traces 153 are formed on the same layer.

It should be noted that the same layer may refer to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by one patterning process using the same mask. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or sections located on the "same layer" are composed of the same material and formed by the same patterning process. As can be seen from this, by arranging that the film layers included in the first wiring 151 and the second wiring 153 are located on the same layer, the manufacturing process can be simplified, the manufacturing cost can be saved, and the manufacturing efficiency can be accelerated.

Referring to FIG. 6 , in some embodiments, the display panel 10 includes a base substrate 110 , a driving layer 120 and a pixel layer 130 stacked in sequence, the data lines 15 and the driving circuit 21 are formed on the driving layer 120 , and the driving layer 120 includes a first A conductive layer 1205 and a second conductive layer 1207 , the first wiring 151 and the second wiring 153 are formed on the second conductive layer 1207 , and the patch wire 152 is formed on the first conductive layer 1205 .

Specifically, the base substrate 110 may be a flexible substrate. The driving layer 120 includes a buffer layer 1201 , a gate dielectric layer 1202 , a first insulating layer 1203 , a second insulating layer 1204 , a first planarizing layer 1205 and a second planarizing layer 1206 .

The buffer layer 1201 is formed on the base substrate 110 , the gate dielectric layer 1202 is located on the side of the buffer layer 1201 away from the base substrate 110 , and the first insulating layer 1203 is located on the side of the gate dielectric layer 1202 away from the base substrate 110 , the second insulating layer 1204 is located on the side of the first insulating layer 1203 away from the base substrate 110 , the first flat layer 1205 is located on the side of the second insulating layer 1204 away from the base substrate 110 , and the second planarization layer 1206 is located on the side of the first planar The layer 1205 is away from the side of the base substrate 110 .

The driving layer 120 further includes a first conductive layer 1207 and a second conductive layer 1208 for forming the data lines 15, wherein the first conductive layer 1207 is located between the second insulating layer 1204 and the first flat layer 1205, and the second conductive layer 1208 is located between the second insulating layer 1204 and the first flat layer 1205 between the first flat layer 1205 and the second flat layer 1206 . The first wiring 151 and the second wiring 153 of the data line 15 are formed on the second conductive layer 1208 , and the transition wire 152 is formed on the first conductive layer 1207 .

Further, the first wiring 151 includes a first transition portion, the second wiring 153 includes a second transition portion, and the orthographic projection of the first transition portion on the base substrate 110 and the transition line 152 on the base substrate 110 The orthographic projection on the base substrate 110 at least partially overlaps, and the orthographic projection of the second transition portion on the base substrate 110 at least partially overlaps the orthographic projection of the transition line 152 on the base substrate 110 .

The first flat layer 1205 is provided with a first via hole 12051 and a second via hole 12052, wherein the first via hole 12051 is located where the first transfer portion 1521 and the first trace 151 overlap, and the second via hole 12052 is located in the second via hole 12051. The connecting portion 1252 overlaps with the second wiring 153 . The first adapter portion is connected to the adapter line 152 through at least part of the first via hole 12051 , and the second adapter portion is connected to the adapter line 152 through at least part of the second through hole 12052 .

Referring to the drawings, in some embodiments, a plurality of driving circuits 21 are formed on the driving layer 120 , and at least one driving circuit 21 includes a driving transistor T0 and a storage capacitor C1 .

The driving transistor T0 includes a first active layer 1211 located on the base substrate 11 , a first gate 1212 located on the side of the first active layer 1211 away from the base substrate 11 , and a first gate 1212 located away from the base substrate 11 . one side and is electrically connected to the source electrode 1213 and the drain electrode 1214 of the first active layer 1211 . The first active layer 1211 and the gate dielectric layer are disposed in the same layer, for example, the source electrode 1213 and the drain electrode 1214 pass through the second insulating layer 1215 , the first insulating layer 1214 and the gate dielectric layer 1212 respectively. The hole is electrically connected to the first active layer 1211 .

The storage capacitor C1 includes a first electrode plate 1221 located on the same layer as the first gate electrode 1212 , and a second electrode plate 1222 located between the first insulating layer 1214 and the second insulating layer 1215 . It should be understood that the storage capacitor C1 further includes a first insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222 .

Please refer to FIG. 7 or FIG. 8 , the pixel unit 31 may be a light emitting diode, such as an OLED. The pixel unit 31 includes a first electrode 131 (eg, an anode), a functional layer 132 located on a side of the first electrode 131 away from the base substrate 11 , and a second electrode 133 (eg, a cathode) located on a side of the functional layer 132 away from the base substrate 11 . . Here, the functional layer 132 includes at least a light-emitting layer, such as an organic light-emitting layer. In certain embodiments, the functional layer 132 may also include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

Further, referring to FIG. 7 , when the pixel unit 31 is the first pixel unit 311 , the first electrode 131 can pass through the second flat layer 1206 and the first flat layer 1205 to be electrically connected to the drain 1214 of the corresponding driving transistor T0 .

Referring to FIG. 8 , the display panel 10 further includes a transparent electrode ITO. The transparent electrode ITO is located on the side of the second flat layer 1206 away from the substrate bottom plate 110 . When the pixel unit 31 is the second pixel unit 312 , the first electrode 131 may be It is electrically connected to the transparent electrode ITO, and is electrically connected to the source electrode 1213 of the driving transistor through the second flat layer 1206 and the first flat layer 1205 through the transparent electrode ITO. Understandably, since the driving circuit of the second pixel unit 312 is located in the transition region 111 , the first electrode of the second pixel unit 312 does not directly pass through the second flat layer 1206 and the first flat layer 1205 and the drain of the corresponding driving transistor T0 The electrode 1214 is electrically connected. Therefore, the connection between the second pixel unit 312 and the driving circuit 21 can be realized by the arrangement of the transparent electrode ITO.

In some embodiments, referring to FIG. 7 or FIG. 8 , the pixel layer 130 further includes a pixel defining layer 134 , a support layer 127 and an encapsulation layer 136 for defining the plurality of pixel units 31 .

For example, the pixel defining layer 134 has a plurality of openings corresponding to the plurality of pixel units 31, and the plurality of pixel units 31 are located in the plurality of openings. For example, the encapsulation layer 136 may comprise a thin film encapsulation layer. In some embodiments, the encapsulation layer 136 may include a first inorganic layer 1361 , a second inorganic layer 1362 , and an organic layer 1363 between the first inorganic layer 1361 and the second inorganic layer 1362 .

As some implementations, one or more of the second insulating layer 1215, the first insulating layer 1214, the gate dielectric layer 1212, the buffer layer 124, the planarization layer 125, the pixel defining layer 134, the support layer 127 may include, for example, Organic insulating materials such as polyimide and resin materials, or inorganic insulating materials including silicon oxides, silicon nitrides, silicon oxynitrides, and the like.

In some embodiments, the patch cords 152 of each data line 15 are of equal length.

In this way, the load difference of the patch cables 152 of each data line 15 can be minimized, and the brightness uniformity of the second display area 12 is improved.

In some embodiments, the spacing between the patch lines 152 of adjacent data lines 15 is equal.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples", etc. A particular feature, structure, material, or characteristic described in this embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present application have been shown and described, those of ordinary skill in the art will appreciate that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present application, The scope of the application is defined by the claims and their equivalents.

Claims (14)

1. A display panel is characterized by comprising a first display area and a second display area which are adjacent;

the second display area array is provided with a plurality of pixel units, each pixel unit corresponds to one driving circuit, each column of pixel units is connected with the same data line through the driving circuit, and the data line is used for providing data signals for the driving circuit;

the first display area comprises a transition area, the second display area comprises a hole digging area, the transition area is positioned on two sides of the hole digging area, the pixel unit comprises a second pixel unit positioned in the hole digging area, and the second pixel unit is connected with the driving circuit of the transition area;

the data line comprises a first wiring, a patch cord and a second wiring, the first wiring is located in the second display area and bypasses the digging hole area, the second wiring is located in the transition area, the patch cord is connected with the first wiring and the second wiring respectively, and the joint of the patch cord and the first wiring is located outside the digging hole area.

2. The display panel according to claim 1, wherein the first trace and the patch cord are formed on different layers, and the patch cord is connected to the first trace through a via.

3. The display panel according to claim 2, wherein the patch cord and the second trace are formed on different layers, and the patch cord is connected to the second trace through a via.

4. The display panel according to claim 3, wherein the first traces and the second traces are formed on a same layer.

5. The display panel according to claim 4, wherein the display panel comprises a base substrate, a driving layer, and a pixel layer, which are sequentially stacked, the pixel unit being formed in the pixel layer;

the driving layer comprises a first conducting layer and a second conducting layer, the first wiring and the second wiring are formed on the second conducting layer, and the patch cord is formed on the first conducting layer.

6. The display panel of claim 5, wherein the driving layer further comprises:

a buffer layer on the substrate base plate;

the gate dielectric layer is positioned on one side of the buffer layer, which is far away from the substrate base plate;

the first insulating layer is positioned on one side, far away from the substrate, of the gate dielectric layer;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the first flat layer is positioned on one side, far away from the substrate, of the second insulating layer;

the second flat layer is positioned on one side, away from the substrate base plate, of the first flat layer;

the first conductive layer is located between the second insulating layer and the first planar layer, and the second conductive layer is located between the first planar layer and the second planar layer.

7. The display panel according to claim 5, wherein the driving circuit is formed in the driving layer, and the driving circuit comprises:

a driving transistor and a storage capacitor, the driving transistor including:

a first active layer on the substrate base plate;

the first grid electrode is positioned on one side, far away from the substrate, of the first active layer;

the first insulating layer is positioned on one side, far away from the substrate, of the first grid electrode;

the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer;

the source electrode and the drain electrode are positioned on one side, far away from the substrate, of the second insulating layer and are electrically connected to the first active layer;

a storage capacitor, comprising:

the first electrode plate is positioned on the same layer as the first grid electrode; and

a second electrode plate located between the first insulating layer and the second insulating layer.

8. The display panel according to claim 7, wherein the pixel unit comprises:

a first electrode electrically connected to the source electrode;

the functional layer is positioned on one side of the first electrode, which is far away from the substrate;

and the second electrode is positioned on one side of the functional layer away from the substrate.

9. The display panel of claim 5, wherein the pixel layer comprises a pixel definition layer defining the pixel unit, a support layer, and an encapsulation layer.

10. The display panel according to claim 1, wherein the pixel units further include first pixel units arranged in an array outside the excavated area of the second display area, the first wires are connected to the driving circuits of the first pixel units, and the second wires are connected to the driving circuits of the second pixel units.

11. The display panel of claim 1, wherein the patch cords of each of the data lines are equal in length.

12. The display panel according to claim 1, wherein the patch cord of the adjacent data lines are equally spaced.

13. The display panel of claim 1, wherein the hollowed area comprises one of a circle, a square, or a drop shape.

14. A display device comprising the display panel of any one of claims 1 to 13, and an optical element on a non-display side of the display panel, wherein an orthographic projection of the optical element on the display panel at least partially overlaps the cutout region.

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