CN115099412A

CN115099412A - Feature extraction method and related equipment

Info

Publication number: CN115099412A
Application number: CN202210685142.0A
Authority: CN
Inventors: 窦猛汉; 王超; 袁野为; 郑永杰; 李叶
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2022-09-23

Abstract

The invention discloses a feature extraction method and related equipment, wherein the method comprises the following steps: acquiring a feature to be extracted and target class data; calculating a first correlation coefficient of the features to be extracted and the target class data, and calculating a second correlation coefficient between the features to be extracted; determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient; and determining an objective function value of the feature extraction function, which meets a preset condition, based on an objective quantum circuit, and taking the feature to be extracted corresponding to the objective function value as an extraction feature. By the technical scheme, the characteristics of high association degree with the target category data and low redundancy can be extracted.

Description

Feature extraction method and related equipment

Technical Field

The invention belongs to the technical field of quantum computing, and particularly relates to a feature extraction method and related equipment.

Background

The data volume of the financial field and other industries is rapidly increasing along with the development of science and technology, and not only the data volume but also a great number of data dimensions are provided. The dimension reduction is carried out on the data, namely a small amount of feature data containing key information is extracted from a large amount of feature data, so that the accuracy rate can be improved and the processing speed can be increased when other models process the extracted feature data.

In the related art, it is desirable to extract feature data having a high degree of association with a target class and a small degree of redundancy between them, and how to extract such data is important.

Disclosure of Invention

The invention aims to provide a feature extraction method and related equipment, aiming at extracting feature data which are highly associated with a target class and have low redundancy.

In order to achieve the above object, a first aspect of the embodiments of the present invention provides a feature extraction method, including:

acquiring a feature to be extracted and target category data;

calculating a first correlation coefficient of the features to be extracted and the target class data, and calculating a second correlation coefficient between the features to be extracted;

determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient;

and determining an objective function value of the feature extraction function, which meets a preset condition, based on an objective quantum circuit, and taking the feature to be extracted corresponding to the objective function value as an extraction feature.

Optionally, the determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient includes:

determining the association information of the features to be extracted and the target class data based on the first association coefficient;

determining redundant information among the features to be extracted based on the second correlation coefficient;

determining a feature extraction function based on the correlation information and the redundancy information.

Optionally, the function value of the feature extraction function is negatively correlated with the associated information, and the function value of the feature extraction function is positively correlated with the redundant information.

Optionally, the target quantum circuit includes a target quantum computation circuit and a target quantum search circuit, and the target quantum computation circuit is configured to compute a difference between the function value of the feature extraction function and a threshold;

the determining of the objective function value of the feature extraction function, which meets a preset condition, based on the objective quantum line includes:

inputting the initial state corresponding to the feature to be extracted into the target quantum computing circuit to obtain a final state used for expressing the difference between the function value and the threshold value;

inputting the final state into the target quantum search line to obtain an output state which represents that the function value is smaller than the threshold value;

determining the smallest of the function values as the objective function value based on the output state.

Optionally, the inputting the final state into a target quantum search line to obtain an output state indicating that the function value is smaller than the threshold includes:

and inputting the final state into a target quantum search circuit to obtain an output state containing a target state with amplified amplitude, wherein the target state is a quantum state representing that the function value is smaller than the threshold value.

Optionally, the target quantum search circuit includes a search unit, and the search unit includes a first phase flipping unit and a second phase flipping unit, which are sequentially cascaded, where the first phase flipping unit is configured to flip an input first quantum state along a non-good state, the second phase flipping unit is configured to flip an input second quantum state along the first quantum state, and the non-good state is a superposition state of the last state, which is used to represent a sub-state of the function value smaller than the threshold.

Optionally, the first correlation coefficient is any one of Kullback-Leibler divergence, mutual information, and a correlation coefficient, and the second correlation information is any one of Kullback-Leibler divergence, mutual information, and a correlation coefficient.

In a second aspect of the embodiments of the present invention, there is provided a feature extraction apparatus, including:

the acquisition module is used for acquiring the features to be extracted and the target category data;

the calculation module is used for calculating a first correlation coefficient between the features to be extracted and the target category data and calculating a second correlation coefficient between the features to be extracted;

a determination module for determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient;

and the extraction module is used for determining an objective function value of the feature extraction function, which meets a preset condition, based on the target quantum circuit, and taking the feature to be extracted corresponding to the objective function value as an extraction feature.

Optionally, the determining module is further configured to:

the extraction module is further configured to:

inputting the initial state corresponding to the feature to be extracted into the target quantum computing circuit to obtain a final state used for representing the difference between the function value and the threshold value;

Optionally, the extracting module is further configured to:

Optionally, the target quantum search circuit includes a search unit, and the search unit includes a first phase inversion rotor unit and a second phase inversion rotor unit which are sequentially cascaded, where the first phase inversion rotor unit is configured to invert an input first quantum state along a non-good state, the second phase inversion rotor unit is configured to invert an input second quantum state along the first quantum state, and the non-good state is a superposed state of the last state, where the superposed state is used to represent a sub-state where the function value is smaller than the threshold.

In a third aspect of embodiments of the present invention, a storage medium is provided, in which a computer program is stored, where the computer program is configured to perform the steps of the method according to any one of the above first aspects when the computer program runs.

In a fourth aspect of the embodiments of the present invention, there is provided an electronic apparatus, including a memory and a processor, where the memory stores therein a computer program, and the processor is configured to execute the computer program to perform the steps of the method in any one of the above first aspects.

Based on the technical scheme, after the features to be extracted and the target class data are obtained, a first correlation coefficient of the features to be extracted and the target class data is calculated, and a second correlation coefficient between the features to be extracted is calculated; the first correlation coefficient may reflect the degree of correlation between the features to be extracted and the target category data, the second correlation coefficient may reflect the degree of correlation between the respective features to be extracted, further reflecting the redundancy among the features to be extracted, determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient, wherein the feature extraction function can represent the correlation degree between the features to be extracted and the target class data and the redundancy among the features to be extracted, and then the objective function value which accords with the preset condition of the feature extraction function is determined to represent the greater association degree between the feature to be extracted and the objective category data based on the objective quantum circuit, and the redundancy among the small features to be extracted is used, and the features to be extracted corresponding to the objective function values are used as extraction features, so that feature data which are high in association with the target class and small in redundancy among the features can be obtained.

Drawings

Fig. 1 is a block diagram illustrating a hardware configuration of a computer terminal of a feature extraction method according to an exemplary embodiment.

FIG. 2 is a flow diagram illustrating a method of feature extraction according to an example embodiment.

Fig. 3 is a flowchart illustrating a feature extraction method including step S23 according to an exemplary embodiment.

Fig. 4 is a schematic diagram illustrating a target quantum computing circuit, according to an example embodiment.

Fig. 5 is a schematic diagram illustrating a controlled quantum logic gate, according to an example embodiment.

Fig. 6 is a block diagram illustrating a feature extraction apparatus according to an exemplary embodiment.

Detailed Description

The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

The embodiment of the invention firstly provides a feature extraction method, which can be applied to electronic equipment, such as a computer terminal, in particular to a common computer, a quantum computer and the like.

This will be described in detail below by way of example as it would run on a computer terminal. Fig. 1 is a block diagram illustrating a hardware configuration of a computer terminal of a feature extraction method according to an exemplary embodiment. As shown in fig. 1, the computer terminal may include one or more processors 102 (only one is shown in fig. 1) (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing a quantum wire-based feature extraction method, and optionally, may further include a transmission device 106 for a communication function and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the feature extraction method in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by quantum languages such as Qrun languages, so that the support on the operation of a quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a series of instruction sequences that operate quantum logic gates in a time sequence.

In practical applications, due to the limited development of quantum device hardware, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program in the embodiment of the invention is a program for representing quantum bits and evolution thereof written in a classical language, wherein the quantum bits, quantum logic gates and the like related to quantum computation are represented by corresponding classical codes.

A quantum circuit, which is an embodiment of a quantum program and also a weighing sub-logic circuit, is the most common general quantum computation model, and represents a circuit that operates on a quantum bit under an abstract concept, and the circuit includes the quantum bit, a circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation.

Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.

The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds, or even thousands, of quantum gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.

It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved by using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H gates, adama gates), pauli-X gates (X gates, pauli X gates), pauli-Y gates (Y gates, pauli Y gates), pauli-Z gates (Z gates, pauli Z gates), RX gates (RX swing gates), RY gates (RY swing gates), RZ gates (RZ swing gates), and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, isswap gates, Toffoli gates, etc. Quantum logic gates are typically represented using unitary matrices, which are not only matrix-form but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a vector corresponding to a quantum state right vector by a unitary matrix left. For example, a quantum state right vector |0>The corresponding vector may be

Quantum state right vector |1>The corresponding vector may be

From 3/4/2014, "11-day extra-daily bond" becomes the first default public bond in our country, and the bond default appears successively. The establishment of the bond default early warning model plays an important role in stabilizing the healthy development of economy. And the selection of effective detection indexes plays a vital role on the model, and the good index selection can improve the learning efficiency and accuracy of the model, accelerate the detection speed, reduce redundant information and reduce the risk of overfitting. The above process of selecting the detection index, that is, the process of feature extraction, can realize data dimension reduction through feature extraction. Data dimensionality reduction is important in financial data analysis, and when the data dimensionality is too high, strong correlation is easy to exist among all dimensionalities of high-dimensional data, so that a large amount of useless extra information exists in the data. These dimensions of high correlation are colloquially the dimensions with higher similarity correlation. The redundant information not only makes the data not be understood intuitively, but also brings difficulty to subsequent data mining and model analysis, and the redundant information not only makes the model difficult to converge and has large memory consumption, but also may generate an overfitting phenomenon, and directly interferes the conclusion of the subsequent analysis. Therefore, it is important to extract feature data having a high degree of association with a target class and a small degree of redundancy between them, and based on this, a feature extraction method is proposed as follows.

Fig. 2 is a flow diagram illustrating a method of feature extraction, as shown in fig. 2, according to an example embodiment, the method comprising:

and S21, acquiring the feature to be extracted and the target class data.

S22, calculating a first correlation coefficient between the features to be extracted and the target class data, and calculating a second correlation coefficient between the features to be extracted.

S23, determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient.

And S24, determining an objective function value of the feature extraction function, which meets a preset condition, based on the target quantum circuit, and taking the feature to be extracted corresponding to the objective function value as an extraction feature.

In step S21, the features to be extracted may be all features related to the target object, and are the operation objects for performing the feature extraction, that is, all feature data before performing the feature extraction. For example, the feature to be extracted may be feature information in a financial statement, such as income, net profit, depreciation cost, income tax, and the like. The target category data is used to indicate category information to which the features to be extracted from the features to be extracted conform, and for example, the increase or decrease of the stock price can be used as the target category data. The acquired feature to be extracted and the target category data may be input into a computer to be acquired through one or more of voice, text, entity key and entity key, or may be acquired through wired communication or wireless communication, which is not limited in this application.

In step S22, a first correlation coefficient is used to indicate a degree of correlation between the feature to be extracted and the target category data, where the greater the first correlation coefficient is, the higher the degree of correlation between the feature to be extracted and the target category data is, and the feature to be extracted with the higher degree of correlation is the feature that is desired to be extracted. The second correlation coefficient is used for representing the correlation degree between the features to be extracted, and similarly, the higher the correlation degree between the features to be extracted is, the more similar the effective information contained between the features to be extracted is, and further, the higher the redundancy between the features to be extracted is.

In a possible implementation manner, the first correlation coefficient is any one of Kullback-Leibler divergence, mutual information, and a correlation coefficient, and the second correlation information is any one of Kullback-Leibler divergence, mutual information, and a correlation coefficient. Further, the first correlation coefficient and the second correlation coefficient may be calculated by using a formula of Kullback-Leibler Divergence (KL Divergence), Mutual Information (Mutual Information), or a correlation coefficient (correlation coefficient), respectively.

Taking mutual information as an example, the calculation formula is as follows:

wherein x and y are variables, p (x) is the probability density of x, p (y) is the probability density of y, p (x, y) is the joint probability density of x and y, and I (x; y) represents mutual information of x and y, where x and y represent first correlation coefficients when the features to be extracted and the target class data, and represent second correlation coefficients when x and y represent different features to be extracted.

Optionally, referring to fig. 3, in step S23, determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient includes:

s231, determining the association information of the features to be extracted and the target class data based on the first association coefficient.

S232, determining redundant information among the features to be extracted based on the second correlation coefficient.

S233, determining a feature extraction function based on the correlation information and the redundant information.

In step S231, the first correlation coefficient may be multiplied by the feature to be extracted to obtain correlation information between the feature to be extracted and the target category data. For example, the first correlation coefficient is calculated by using the mutual information, and then multiplied by the feature to be extracted to obtain the correlation information a ^T z, wherein a is a vector formed by the first association coefficient, the ith element is a first association coefficient I (fi; c) which represents the association degree of the ith feature fi to be extracted and the target category data c, z is a vector formed by the feature zi to be extracted, the ith element is zi, and z belongs to {0,1} ⁿ And n represents the number of elements in z, in one possible embodiment, I (fi; c) can be replaced by the absolute value of the correlation coefficient between fi and c, of course, in other embodiments, when the feature to be extracted is a continuous variable, the above formula can be directly used for calculation, in the case of a large data volume, the probability density function can be obtained by using a non-parametric density estimation method, and in the case of processing classified variables, the information entropy can be used for calculation. The present application is not particularly limited thereto.

In step S232, the method may be based on the formula qz ^T And calculating redundant information by using the sigma-z, wherein the sigma is a matrix formed by I (fi; fj), the I (fi; fj) represents a second correlation coefficient of the feature fi to be extracted and the feature fj to be extracted, and q is an adjusting coefficient which can be a real number. In one possible embodiment, I (fi; fj) may be replaced by the absolute value of the correlation coefficient between fi and fj, although in other embodiments, when the feature to be extracted is a continuous variable, the above formula may be used directly to calculateThe probability density function can be obtained by using a nonparametric density estimation method under the condition of large data volume, and the information entropy can be used for calculation under the condition of processing classified variables, so that the application is not particularly limited.

Step S231 and step S232 may be executed simultaneously, or may be executed sequentially according to a certain order, and after obtaining the associated information and the redundant information, step S233 is executed. In step S233, the feature extraction function may be determined as f (z) -a by the aforementioned associated information and redundant information ^T z+qz ^T Σ z, wherein f (z) a feature extraction function whose function value is negatively correlated with the correlation information, whose function value is positively correlated with the redundant information. And the smaller the function value of f (z), the higher the degree of association between the extracted features and the target classification data, and the less redundant information between the features. In other embodiments, of course, the whole of f (z) is multiplied by-1, so that the function value is positively correlated with the associated information and negatively correlated with the redundant information, and the larger the function value is, the higher the association degree between the extracted features and the target classification data is, and the less redundant information is among the features. In this regard, the present application is not particularly limited. Furthermore, different feature extraction functions may also be determined based on the first correlation coefficient and the second correlation coefficient in other ways.

In step S24, the feature extraction function is optimized and solved by the target quantum circuit to find a target function value meeting a preset condition, for example, the feature extraction function is f (z) -a ^T z+qz ^T In Σ z, the objective function value meeting the preset condition may be the smallest function value or a function value smaller than a specific threshold. When the function value is small enough, the correlation degree between the corresponding to-be-extracted features and the target classification data is high, the redundancy between the corresponding to-be-extracted features is small, the corresponding to-be-extracted features are the features to be extracted, and the to-be-extracted features corresponding to the objective function value, namely the features to be extracted for calculating the objective function value, are used as the extraction features. For example, z is composed of z1, z2 and z3, the values of the independent variable z corresponding to the objective function value are respectively z 1-0, z 2-z 3-1, and 0 represents that the special to be extracted is selectedAnd the features are used as extracted features, if 1 indicates that the features are not selected, the features z1 are discarded, and the features z2 and z3 are output as extracted features, so that the feature extraction process is completed.

In one possible implementation, a Max-minimum Redundancy (mRMR) algorithm is also used to perform feature extraction, which is calculated as follows:

the more the value of S is, the higher the degree of association between the corresponding feature to be extracted and the target class data c is, and the smaller the redundancy between the features to be extracted. If the global optimal solution is optimally solved by using an exhaustive algorithm of the global optimal solution, the complexity is exponential, and if the incremental search algorithm is adopted for solving, although the complexity is low, the global optimal solution is a non-global optimal solution algorithm and can possibly fall into a local optimal solution. Based on this, the problem can be considered to be converted into a Quadratic Unconstrained Binary Optimization (QUBO) for solving, and then the mRMR problem can be converted into:

minf(z)＝-a ^T z+qz ^T Σz，

and then the optimized solution is carried out by using a quantum computing mode.

For optimization goal f (z) ═ a ^T z+qz ^T Σ z, where the elements of a and Σ are both positive numbers, has a unique maximum value by calculation, considering that the variables are continuous,

taking the maximum value in time, corresponding to

And z can be controlled to be a small positive number when the adjustment coefficient q is small ^T The larger the value of (a), whereas the larger the positive value of q, the larger the value of z ^T The more value ofSmall, z ∈ {0,1} ⁿ That is, when z is binarized, the smaller q is, and z is ^T The more 1 in the element(s), the larger q, z ^T The fewer 1's in the elements (a), the number of features to be finally extracted can be further controlled by controlling the value of q.

Based on the technical scheme, after the features to be extracted and the target class data are obtained, a first correlation coefficient of the features to be extracted and the target class data is calculated, and a second correlation coefficient between the features to be extracted is calculated; the first correlation coefficient may reflect the degree of correlation between the features to be extracted and the target category data, the second correlation coefficient may reflect the degree of correlation between the respective features to be extracted, further reflecting the redundancy among the features to be extracted, determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient, wherein the feature extraction function can represent the correlation degree between the features to be extracted and the target class data and the redundancy among the features to be extracted, and then determining that the objective function value of the feature extraction function which meets the preset condition represents a larger association degree between the feature to be extracted and the objective category data based on the objective quantum circuit, and the redundancy among all the small features to be extracted is smaller, and the features to be extracted corresponding to the objective function value are taken as extraction features, so that feature data which are high in association with the objective class and small in redundancy among the features can be obtained.

Optionally, the target quantum circuit includes a target quantum computation circuit for computing a difference between the function value of the feature extraction function and a threshold value, and a target quantum search circuit.

Alternatively, in step S24, determining the objective function value of the feature extraction function that meets the preset condition based on the objective quantum wire may include:

and S241, inputting the initial state corresponding to the feature to be extracted into the target quantum computing circuit to obtain a final state used for representing the difference between the function value and the threshold value.

And S242, inputting the final state into the target quantum search line to obtain an output state which shows that the function value is smaller than the threshold value.

S243, determining the smallest function value as the objective function value based on the output state.

In step S241, the target quantum computing circuit may be a quantum circuit for computing a difference between the function value and a threshold value, the function value may be a function value of the above-mentioned feature extraction function f (z), and an initial value of the threshold value may be determined according to actual circumstances. And preparing the features to be extracted to an initial state, such as an equal-amplitude superposition state, and inputting a target quantum calculation circuit to obtain the difference of the final state expression function value minus the threshold value. For example, the initial state is

Sub-state |00 thereof>、|01>、|10>、|11>Representing a combination of 2 features to be extracted, 0 representing no selection of the corresponding feature to be extracted, 1 representing a selection, e.g. |00>And indicating that the first feature to be extracted and the second feature to be extracted are not selected. Calculating line operation through target quantum to obtain final state

Sub-state | a thereof>、|b>、|c>、|d>Can respectively represent the correspondence |00>、|01>、|10>、|11>The calculation result of (2).

In step S242, the last state is input into the target quantum search circuit, where the last state is composed of a plurality of sub-states, and different sub-states correspond to differences between function values of different features to be extracted and thresholds, and then the target quantum search circuit searches to find sub-states representing that the function values are smaller than the thresholds and mark the sub-states as output states, for example, amplitudes of the sub-states in the output states may be amplified. The function value is smaller than the threshold value, which shows that the correlation degree between the corresponding to-be-extracted features and the target category data is higher, the redundancy between the to-be-extracted features is smaller, and the corresponding to-be-extracted features meet the requirements better.

In step S243, the qubits representing the output state and the qubits representing the features to be extracted may be measured simultaneously, and when the two types of qubits are entangled by the quantum logic gate and the measurement result corresponding to the output state represents that the function value is smaller than the threshold, the measurement result of the qubits representing the features to be extracted, which is obtained by simultaneous measurement, is taken as the extracted features. The smaller function value obtained in step S242 may be used as a new threshold value, and the process returns to step S242, and further smaller function value is found, and the process is repeated a plurality of times until the smallest function value is found as the objective function value.

Optionally, in step S242, inputting the final state into a target quantum search line, and obtaining an output state indicating that the function value is smaller than the threshold value, includes:

Specifically, the target state is a sub-state of the final state, and after the final state is input into a target quantum search line, the amplitude of the target state is amplified, so that the measured probability of the target state becomes larger and even approaches to 1, thus measuring the quantum bit representing the output state, and obtaining the measurement result corresponding to the target state at a high probability to complete the search of the target state.

Specifically, the target quantum search circuit may include a plurality of cascaded search units, where the last state is input to a first search unit, the quantum state output by the first search unit is input to a second search unit, and so on until the last search unit outputs the output state. The first quantum state input by the first search unit may be a last state, and the first quantum states input by the remaining search units are quantum states output by the previous search unit.

Each searching unit marks the target state, amplifies the amplitude of the marked target state, and inputs the final state into the searching unit in sequence, wherein the amplitude of the target state can be amplified one or more times.

The first phase flipping unit marks a target state, sets the target function to be represented by subtracting a threshold value from the feature extraction function f (z), and when the target function value is a negative number, it means that the function value of f (z) is smaller than the threshold value, and further the target state is a quantum state representing that the target function value is a negative number, for example, in one possible embodiment, the initial state is represented by a complementary code, and the obtained final state is also a complementary code, and when the most significant bit thereof is a sign bit, and the sign bit thereof is |1>, it means that the target function value corresponding to the last state is a negative number, and when the sign bit thereof is |0>, it means that the target function value corresponding to the last state is a non-negative number. The first phase inversion unit may further comprise a Z gate which is applied to the qubit representing the sign bit to cause a phase inversion thereof to mark the target state in the last state to be distinguished from other quantum states in other last states. Of course, in other possible embodiments, the target state in the final state may be phase-flipped in other manners, and the present invention is not limited thereto.

After the first phase inversion rotor unit marks the target state, the output quantum state is input into the second phase inversion rotor unit so as to amplify the amplitude of the marked target state. Of course, when the quantum search line includes a plurality of search cells, the amplitude of the target state in the last state may be amplified a plurality of times.

For the final state, when the initial state is used to represent a selection combination of multiple features to be extracted, for example, when the initial state is an equal-amplitude superposition state, the obtained final state is also a superposition state, each sub-state of the superposition state represents a calculation result of a selection combination corresponding to an objective function, wherein a sub-state representing that a function value is greater than a threshold value constitutes a superposition state | g >, and a sub-state representing that the function value is less than or equal to the threshold value constitutes a superposition state | b >, and | g > may be called a good state, | b > may be called a non-good state, | g > and | b > are orthogonal, and the final state may be represented by | g > and | b >. Furthermore, in the same search unit, the first phase inversion unit can invert the input first quantum state | a > along the non-good state | b > to obtain | c >, and the inverted quantum state | c > is input into the second phase inversion unit as the second quantum state, so that | c > is inverted along the first quantum state | a >, and further amplification of the first quantum state | a > is realized, and the action processes of other search units are the same. By setting the number of search cells, the amplitude of the target state can be amplified to a desired degree, for example, the measurement probability corresponding to the amplitude thereof is made to approach 1. By adopting the search line, approximate quadratic acceleration can be realized compared with a classical traversal method.

Alternatively, the target quantum computation wires may be constructed based on phase estimation quantum wires.

The target function, that is, the feature extraction function minus the threshold value, which is generally a polynomial, constructs a target quantum computation circuit for computing the target function, including:

and S211, constructing a controlled quantum logic gate for calculating each item in the polynomial based on the target quantum logic gate in the phase estimation quantum circuit.

And S212, acting the controlled quantum logic gate on the quantum bit which is not the phase estimation quantum line to obtain a target quantum calculation line for calculating the polynomial.

Phase estimation quantum wires are used to solve a unitary matrix acting on the quantum wire and the eigenvalues of its eigenvectors, which can then be expressed as unimodules since the eigenvalues of the unitary matrix must be unimodules

Solving for eigenvalues is therefore equivalent to solving for phase

Specifically, the phase estimation quantum wire may be used to represent coefficients in a polynomial, and a target quantum computation wire for computing the polynomial may be constructed by modifying the phase estimation quantum wire. A qubit other than the phase estimation quantum wire may be called a first qubit.

In step S211, a controlled quantum logic gate may be constructed for each term monomial in the computational polynomial using the target quantum logic gate in the phase estimation quantum wire. The target quantum logic gate in the phase estimation quantum circuit may be a quantum logic gate for representing coefficients of the polynomial in the phase estimation quantum circuit, and may itself be a quantum logic gate controlled by a single or multiple qubits, such as a controlled RY gate or a controlled RX gate, and a control bit, such as the aforementioned first qubit, may be additionally added on the basis of the target quantum logic gate, so that the target quantum logic gate becomes a controlled quantum logic gate controlled by a larger number of qubits, and of course, the target quantum computation circuit may also be a single quantum logic gate, such as a U1 gate or an RZ gate, and then a controlled quantum logic gate controlled by a single or multiple qubits is constructed on the basis of the target quantum computation circuit. Of course, in other possible embodiments, other quantum wires or other quantum logic gates may also be used to construct the aforementioned controlled quantum logic gate or construct the target quantum computing wire, and the present application is not limited in this respect.

After the controlled quantum logic gate is constructed, the process proceeds to step S212, and in step S212, a first qubit may be additionally obtained for inputting the argument of the polynomial into the target quantum computation circuit. And applying the controlled quantum logic gate to the first quantum bit, and combining the first quantum bit with the phase estimation quantum line to obtain a target quantum calculation line for calculating the polynomial. It should be noted that the controlled qubit logic gate acting on the first qubit may indicate that the controlled qubit logic gate is associated with the first qubit in the target quantum computing circuit, the quantum state of the first qubit may be input into the controlled qubit logic gate, which may be a control bit of the controlled qubit logic gate, and the controlled qubit logic gate does not necessarily change the quantum state of the first qubit after acting on the first qubit, for example, when the controlled qubit logic gate acts on the first qubit for the controlled U1 gate, the first qubit may be a control bit of the controlled U1 gate, and the quantum state of the controlled qubit is not changed after being input into the controlled U1 gate.

Optionally, in step S211, constructing a controlled quantum logic gate for calculating each term in the polynomial based on the target quantum logic gate in the phase estimation quantum line, including:

and S2111, determining a target quantum logic gate in the phase estimator sub-line, wherein the target quantum logic gate is used for calculating the coefficient corresponding to each term in the polynomial.

And S2112, taking the first qubit as a control bit of the target quantum logic gate to obtain a controlled quantum logic gate for calculating each item in the polynomial.

In step S2111, a target quantum logic gate for calculating the coefficient of each polynomial in the polynomial is first found in the phase estimation quantum circuit, for convenience of description, taking the case where the polynomial only includes one polynomial as an example, see the phase estimation quantum circuit in the target quantum calculation circuit shown in fig. 4, where the phase estimation quantum circuit includes a qubit 513, a qubit 514, a qubit 515, a qubit 516 and quantum logic gates on the qubits. The phase estimation quantum line is used for calculating coefficient 2 of the monomial 2x1x2, wherein a target quantum logic gate for calculating coefficient 2 comprises a controlled RY gate 501, a controlled RY gate 502 and a controlled RY gate 503, wherein the controlled RY gate 501 acts on a qubit 513 and a qubit 516, the qubit 513 is a control bit, and the qubit 516 is a target bit; controlled RY gate 502 acts on qubit 514 and qubit 516, qubit 514 being the control bit and qubit 516 being the target bit; controlled RY gate 503 acts on qubit 515 and qubit 516, qubit 515 being the control bit and qubit 516 being the target bit.

In step S2112, the first qubit is a qubit that is not a qubit of the phase estimation quantum line, and for the first qubit in the target quantum computation line, the first qubit is added as a control bit of the target quantum logic gate, resulting in a controlled quantum logic gate for each polynomial in the computation polynomial. It should be noted that the target qubit may also be a controlled qubit, and after the first qubit is added as the control bit thereof, the number of control bits of the target qubit is increased, for example, the target qubit is a controlled RY gate controlled by a single qubit, and after one first qubit is added as the control bit thereof, the target qubit is controlled by two qubits. Following the foregoing example, referring to fig. 4, the first qubits are qubits 511 and qubits 512, which are used to represent the inputs of x1 and x2 in the polynomial 2x1x2, respectively, and the input data thereof may be binarized, that is, the inputs of x1 and x2 are 0 or 1, for the determined controlled RY gate 501 corresponding to the polynomial 2x1x2, the controlled RY gate 502 and the controlled RY gate 503, for each of which the qubits 511 and the qubits 512 are added as control bits, thereby obtaining a controlled quantum logic gate 521 corresponding to the controlled RY gate 501, a controlled quantum logic gate 522 corresponding to the controlled RY gate 502, and a controlled quantum logic gate 523 corresponding to the controlled RY gate 503. Wherein, the parameters of the controlled RY gate 501, the controlled RY gate 502 and the controlled RY gate 503 are respectively-pi, -2 pi, -4 pi. It should be noted that the parameter-pi, -2 pi, -4 pi corresponds to a specific characteristic value of the controlled RY gate, and for other characteristic values, the parameter values may be different, and when the number of control bits of the controlled RY gate is different, the parameter values may also be different.

Similarly, for a polynomial comprising a plurality of monomials, for example for 2x1x2+3(x1) ² For 3(x1) ² The corresponding target quantum logic gate executes the foregoing steps to construct a corresponding target quantum computing circuit, which is not described in detail herein. In addition, for decimal input data, it may be converted into binary data, and then assigned to an argument of each term in the corresponding polynomial, for example, when calculating 4x, x is 3, then 3 may be converted into binary data 011, and expressed by three arguments x1, x2, and x3, where x1 is 0, and x2 is x3 is 1, then 4x may be converted into calculation formula 4 (4x1+2x2+ x 3). The calculation of other decimal data may be performed in this manner, to which the present application is not particularly limited.

Optionally, the phase estimation quantum line further includes an inverse fourier transform unit, and the inputting an initial state corresponding to the feature to be extracted into the target quantum calculation line to obtain a final state representing a difference between the function value and the threshold may include:

inputting the initial state of at least the first qubit into the controlled quantum logic gate of the target quantum computing circuit to obtain an intermediate state;

and inputting the intermediate state into the inverse Fourier transform unit to obtain a final state.

Specifically, the controlled quantum logic gate operates on the initial state, the operation result is still in the phase of the quantum state, and further operates on the initial state by using the inverse fourier transform unit, so that the calculation result is in the quantum state of the final state, for example, when the polynomial calculation result is 0, the corresponding final state may be |0 >.

Optionally, the target quantum computing circuit further includes a second qubit and a third qubit, and before the initial state corresponding to the feature to be extracted is input into the target quantum computing circuit and a final state representing a difference between the function value and the threshold is obtained, the method may further include:

and preparing the second quantum ratio to an equal-amplitude superposition state, and preparing the third quantum ratio to an eigenstate of the target quantum logic gate.

Specifically, in order to meet the operation requirement of the phase estimation quantum circuit, the second quantum ratio is specially prepared to be in an equal-amplitude superposition state, and the third quantum ratio is specially prepared to be in an eigenstate of the target quantum logic gate. Continuing with the previous example, reference is made to fig. 4 where qubit 513, qubit 514, and qubit 515 are second qubits for use as control bits for the target quantum logic gate, and qubit 516 is a third qubit for use as a target bit for the target quantum logic gate. And then qubit 513, qubit 514 and qubit 515 are prepared to |0> states respectively, and then an H-gate is applied to each qubit to obtain an equal-amplitude superposition state. For qubit 516, since the target qubit gate is a controlled RY gate, it is first prepared to the |0> state, and then applied to the qubit 516 by using an H gate 541 and an S gate 542, respectively, to obtain the eigen state of the controlled RY gate.

Optionally, the target quantum logic gate is a controlled RY gate or a controlled RX gate. For a controlled RX gate, to prepare its eigenstates, only the H-gate needs to be applied to |0>The third qubit of the state. For convenient calculation, when the target quantum logic gate is a controlled RY gate or a controlled RX gate, the corresponding characteristic value is

i is an imaginary number sign, theta is an input parameter of the target quantum logic gate, and the bottom angle of the controlled RY gate or the controlled RX gate can be selected to be

I.e. the parameters of the controlled RY gate and the controlled RX gate are constructed on the basis of this base angle, where m is the number of second qubits. In the phase estimation quantum circuit, to represent a real number, for example, c, a target quantum logic gate may be constructed using a product of c and a base angle as a parameter, the number of target quantum logic gates representing the real number c is equal to the number of second qubits, and is also m, and the parameter value of the parameter of each target quantum logic gate is 2 ^m-1 θ，2 ^m-2 Theta … … 2 theta, theta being the product of the expressed coefficient c and the base angle,

for example, when the second qubit number is 3, 3 controlled RY gates are required, with parameters 4 θ, 2 θ, θ, respectively, and since c is 2 and m is 3, this results in a higher probability of being used for the subsequent qubits

The parameters of these 3 controlled RY gates are-4 π, -2 π, - π, respectively.

In summary, the first qubit, the second qubit, and the third qubit may be obtained through the first quantum register, the second quantum register, and the third quantum register, respectively, in the target quantum computing circuit, the first qubit is used to input the value of the argument into the target quantum computing circuit in an initial state, the second qubit is used to output a final state representing the computing result of the polynomial, and the third qubit plays an auxiliary role, and accordingly, the first qubit, the second qubit, and the third qubit are the key register, the value register, and the auxiliary register, respectively, where operations in the value register and the auxiliary register are phase estimation.

Correspondingly, for the target quantum computation circuit shown in fig. 4, the inverse fourier transform unit includes an isswap gate 531, an H gate 532, an inverse CR gate 533, an H gate 534, an inverse CR gate 535, an inverse CR gate 536, and an H gate 537, where the isswap gate 531 acts on the qubit 513 and the qubit 515, respectively; h-gate 532 acts on qubit 513; an inverse CR gate 533 acts on qubit 513 and qubit 514, with qubit 513 being the control bit and qubit 514 being the target bit; h gate 534 acts on qubit 514 and inverse CR gate 535 acts on qubit 513 and qubit 515, with qubit 513 being the control bit and qubit 515 being the target bit; inverse CR gate 536 acts on qubit 514 and qubit 515, with qubit 514 being the control bit and qubit 515 being the target bit; h-gate 537 operates on qubit 515. Of course, for target quantum computation circuits with other structures, for example, when the polynomial expressed by the target quantum computation circuit has a plurality of monomials, the specific structure of the corresponding inverse fourier transform unit is different, and the target quantum computation circuit can be designed according to specific situations as long as the target quantum computation circuit can realize inverse quantum fourier transform. The inverse CR gate is a conjugate transpose of the CR gate.

Optionally, the target quantum computing circuit further includes a fourth qubit, and before an initial state corresponding to the feature to be extracted is input into the target quantum computing circuit and a final state representing a difference between the function value and the threshold is obtained, the method may further include:

and preparing the fourth quantum ratio to an equal-amplitude superposition state.

Specifically, for part of target quantum logic gates, no operation is performed when the target quantum logic gates act on the |0> state, at this time, the original second qubit and the original third qubit can be merged, corresponding operation is performed only by using one group of qubits, namely the fourth qubit, so as to meet the operation requirement of the phase estimation quantum circuit, and the fourth qubit is directly prepared to the equal-amplitude superposition state, so that the requirement of the qubits can be reduced. Then, while the initial state is input to the target quantum computing circuit, the equal-amplitude superposition state of the fourth qubit may be input to the target quantum computing circuit.

In one possible implementation, the target quantum logic gate is an RZ gate or a U1 gate. The single quantum logic gates are all single quantum logic gates, wherein the unitary matrix corresponding to the U1 gate is as follows:

wherein,

for the parameter, i is an imaginary symbol. For RZ and U1 gates, the corresponding bottom angles are different from those of the controlled RY or RX gates described above, and the bottom angles of the RZ and U1 gates are

Where m is the number of fourth qubits. Similarly, for RZ gate and U1 gate, in the phase estimation quantum circuit, to represent a real number, for example, c, a target quantum logic gate can be constructed by taking the product of c and the base angle as a parameter, the number of target quantum logic gates representing the real number c is the same as the number of fourth qubits, also m, and the parameter value of the parameter of each target quantum logic gate is 2 ^m-1 θ，2 ^m-2 Theta … … 2 theta, theta being the product of the expressed coefficient c and the base angle,

for example, referring to fig. 5, to compute 2x1x3, in the first qubit 901, the first qubit 902, the first qubit 903, and the first qubit 904, the first qubit 902 and the first qubit 904 may be added as control bits to a U1 gate 911 to obtain a controlled quantum logic gate 921 for constructing a 2x1x3A target quantum computation circuit is created that computes 2x1x3, where the fourth qubit 905 is the target bit of the controlled quantum logic gate 921. Similarly, for a polynomial including a plurality of monomials, for example, for 2x1x3+3x1x2, the foregoing steps may be performed on the target quantum logic gate corresponding to 3x1x2, and details thereof are not repeated.

The optimization problem of feature extraction can be converted into a quadratic unconstrained binary optimization problem, namely, a QUBO problem, and the core is to find the minimum value of a binary polynomial, for example, find the minimum value of y ═ 2x1x3+4x2x3+ x2, where the input of each argument is a binary value, i.e., the input is 0 or 1. One possible algorithm for finding the minimum value is to find the minimum value among all the calculation results, so that a large number of calculations are required, and the above-mentioned polynomial calculation method can be utilized. Referring to the foregoing method, for each polynomial, all the first qubits corresponding to the argument of the polynomial may be added as control bits of the target quantum logic gate, for example, for the first polynomial 2x1x3, the first qubits corresponding to x1 and x3 are added as control bits of the target quantum logic gate, and for x2, only the first qubit corresponding to x2 is added as control bits of the target quantum logic gate. In some cases, the degree of the argument in the polynomial may be 2 or more, for example, may comprise (x1) ⁿ On the other hand, since the input is 0 or 1 for the binarized polynomial (x1) ⁿ Since n is an integer of 2 or more, x1, the higher-order argument of the binarized polynomial may be converted to 1-order. Of course, in other embodiments, other target Quantum wires, such as Quantum wires implemented based on the Quantum Approximation Optimization Algorithm (QAOA), may be used to determine the target function value.

Fig. 6 illustrates a feature extraction apparatus according to an exemplary embodiment, and as shown in fig. 6, the apparatus 600 includes:

an obtaining module 610, configured to obtain a feature to be extracted and target category data;

a calculating module 620, configured to calculate a first correlation coefficient between the features to be extracted and the target category data, and calculate a second correlation coefficient between the features to be extracted;

a determining module 630, configured to determine a feature extraction function based on the first correlation coefficient and the second correlation coefficient;

an extracting module 640, configured to determine, based on a target quantum line, an objective function value of the feature extraction function that meets a preset condition, and use the feature to be extracted corresponding to the objective function value as an extraction feature.

Optionally, the determining module 630 is further configured to:

the extraction module 640 is further configured to:

determining the smallest of the function values to be the objective function value based on the output state.

Optionally, the extracting module 640 is further configured to:

and inputting the final state into a target quantum search line to obtain an output state containing a target state with amplified amplitude, wherein the target state is a quantum state representing that the function value is smaller than the threshold value.

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

Yet another embodiment of the present invention further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in the above-mentioned feature extraction method embodiment when running.

Specifically, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, which can store computer programs.

Yet another embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores therein a computer program, and the processor is configured to execute the computer program to perform the steps in the above-mentioned embodiment of the feature extraction method.

Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:

acquiring a feature to be extracted and target category data;

The construction, features and effects of the invention have been described in detail in the embodiments illustrated in the drawings, which are intended as illustrative of the preferred embodiments of the invention, but the invention is not limited thereto, and it is intended that all equivalent embodiments modified or modified based on the idea of the invention are within the scope of the invention without departing from the spirit of the invention covered by the description and the drawings.

Claims

1. A method of feature extraction, the method comprising:

acquiring a feature to be extracted and target category data;

2. The method of claim 1, wherein determining a feature extraction function based on the first correlation coefficient and the second correlation coefficient comprises:

3. The method of claim 2, wherein the function value of the feature extraction function is inversely related to the correlation information and the function value of the feature extraction function is positively related to the redundant information.

4. The method of claim 3, wherein the target quantum wires include a target quantum computation wire for computing a difference between the function value of the feature extraction function and a threshold value, and a target quantum search wire;

the determining, based on the target quantum wire, an objective function value of the feature extraction function that meets a preset condition includes:

5. The method of claim 4, wherein said inputting the last state into a target quantum search line resulting in an output state representing the function value being less than the threshold comprises:

6. The method as claimed in claim 5, wherein the target quantum search circuit comprises a search unit, the search unit comprises a first phase inversion unit and a second phase inversion unit which are cascaded in sequence, the first phase inversion unit is used for inverting a first quantum state of an input along a non-good state, the second phase inversion unit is used for inverting a second quantum state of the input along the first quantum state, and the non-good state is a superposition state of sub-states of the last state which represent that the function value is smaller than the threshold value.

7. The method of claim 1, wherein the first correlation coefficient is any one of Kullback-Leibler divergence, mutual information, and correlation coefficient, and the second correlation information is any one of Kullback-Leibler divergence, mutual information, and correlation coefficient.

8. A feature extraction apparatus, characterized in that the apparatus comprises:

and the extraction module is used for determining an objective function value which meets a preset condition of the feature extraction function based on the objective quantum circuit, and taking the feature to be extracted corresponding to the objective function value as an extraction feature.

9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 7.