CN115098173A - Dual-core AMP framework-based method for identifying friend or foe identification signals at high speed - Google Patents
Dual-core AMP framework-based method for identifying friend or foe identification signals at high speed Download PDFInfo
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Abstract
The invention discloses a method for identifying friend or foe identification signals at a high speed based on a dual-core AMP framework, which relates to the technical field of receiver communication, improves mass data in the field of digital signal processing, particularly friend or foe identification, and is favorable for improving the real-time performance of a receiver, and comprises the following steps of 1: selecting a chip of zynq7000 series, dividing two CPU functions into a CPU0 and a CPU1, and dividing the CPU0 and the CPU1 into a driving layer, a data processing layer and a network layer; step 2: the configuration hardware circuit is used for generating signals, acquiring device descriptors and configuring a system clock and interrupt signal generating circuit; and 3, step 3: the CPU0 is configured to serve as a main core of the dual-core communication system, the linux system is operated and the CPU1 is started after the dual-core communication system is started, an interface in a driving layer is called to establish communication, and when data are uploaded to hardware, the data are packaged through an interface function and written into a shared memory, so that high-speed transmission of the data is achieved.
Description
Technical Field
The invention relates to the technical field of receiver communication, in particular to a method for identifying friend or foe identification signals at a high speed based on a dual-core AMP framework.
Background
At present, the current development situation of the integrated circuit industry in China is as follows: large market demand and unbalanced supply and demand. The industrial structure development is unbalanced, the industrial technical level is not enough, the industrial infrastructure is not enough, the talents are rare, and the like, and the domestic chip industry is everywhere restricted by people, so the performance improvement of the chip is not slow.
In recent years, the rapidly advancing semiconductor technology has made the number of CPU cores on one chip to be hundreds or even thousands. The embedded Multi-core system can be divided into a Symmetric Multi-Processing (SMP) and an asymmetric Processing (AMP) according to the architecture division. The two architectures are different in code, resource and structure, and the most direct difference is that the processors in the SMP system have the same authority, and can independently access shared resources, such as DDR, I/O, interrupt and external equipment. The processor runs the same instruction set, and the operating system performs task allocation and memory management in a unified manner. The asymmetric processor means that the authorities of the processors in the system are different, and the processors need to execute their respective tasks and cannot acquire information of other processors. The asymmetric embedded system can meet the performance requirement of a specific application program and simultaneously reduce development cost and resource consumption.
The operating system is an important component of the embedded system, connects the software and the hardware of the embedded system, and is an important basis for realizing the functions of the embedded system. The Linux operating system is widely applied to an embedded multi-core system, is an open-source UNIX operating system based on POSIX standard, can provide a good development environment for the embedded multi-core system through multithreading and multi-process, driver and file system management, and can adapt to different working environment requirements, including functions of human-computer interaction, equipment management, various communication modes and the like. However, under the condition that the source code of the Linux operating system is not changed, the kernel still has numerous non-preemptive areas, which causes higher-delay response of the system, and cannot meet the high-speed forwarding requirement of the receiver project of the friend-foe identification technology of the project group where the author is located, so as to solve the problems, the simplest way is to improve the performance of the single-core processor. Unfortunately, increasing the main frequency and parallelism of the instruction level of the processor causes limitations in increasing the power consumption and execution efficiency of the chip, and the performance of the processor is limited.
Disclosure of Invention
The invention aims to: in order to solve the technical problems, the invention provides a method for identifying the friend or foe identification signal at a high speed based on a dual-core AMP architecture, which improves mass data in the field of digital signal processing, particularly friend or foe identification, and is beneficial to improving the real-time performance of a receiver.
The invention specifically adopts the following technical scheme for realizing the purpose:
a method for identifying friend or foe identification signals at high speed based on a dual-core AMP architecture comprises the following steps:
step 1: selecting a chip of zynq7000 series, dividing two CPU functions into a CPU0 and a CPU1, and dividing the CPU0 and the CPU1 into a driving layer, a data processing layer and a network layer;
step 2: the configuration hardware circuit is used for generating signals, acquiring device descriptors and configuring a system clock and interrupt signal generating circuit;
and step 3: configuring a CPU0 to serve as a main core of a dual-core communication system, running a linux system and starting the CPU1 after starting, calling an interface in a driving layer to establish communication, and when data are uploaded on hardware, packaging the data through an interface function and writing the data into a shared memory to realize high-speed transmission of the data;
and 4, step 4: the CPU1 starts and reads the address to jump after receiving the request of the CPU0, monitors the data of the shared memory area, receives the data when the data is uploaded, analyzes the data through an friend or foe identification algorithm formulated by the North convention, starts to process the data and forwards the data to the computer for result display.
As an optional technical solution, the driving layer in step 1 specifically includes the following steps:
step 1.1: the CPU0 driving layer mainly comprises a xillybus DMA drive provided by the xillybus official, a data interface with a specific register or address is provided according to a communication protocol, description characters of each device are obtained, inter-core data interaction and hardware data uploading are carried out by using the packaged driving interface, and an interrupt signal is sent by using interrupt equipment; the CPU1 driver layer primarily performs the acquisition of shared memory data.
As an optional technical solution, the data processing layer in step 1 specifically includes the following steps:
step 1.2: the CPU1 data processing layer processing logic is as follows:
step 1.2.1: setting an initial signal amplitude Threshold, and if the amplitude of the signal to be detected is continuously higher than the Threshold by 1us, storing the pulse signal parameters; if the identification signal does not exist, judging the identification signal as a non-friend identification signal, and terminating identification;
step 1.2.2: randomly searching four adjacent pulses P1, P2, P3 and P4 in the signal pulse TOA, judging the four pulses as interrogation signal leading pulses if the intervals of P1, P2, P3 and P4 are subjected to micro-jump on the basis of 17.375us, 10us and 13us according to the characteristics of the interrogation signals, and sending the four pulses to the next step of judging sidelobe suppression pulses; otherwise, judging the signal as a non-inquiry signal and sending the signal to the next stage of identification process;
step 1.2.3: judging whether the pulse exists in 10.5us and 16.25us immediately after the pulse, if so, positioning the signal to be in accordance with the inquiry signal of the mode, otherwise, judging the signal to be a friend or foe identification signal;
step 1.3: the CPU0 data processing layer mainly repackages the hardware data to make it adapt to the CPU1 data processing layer structure, and the purpose is to reduce the modification of hardware and save resources.
As an optional technical solution, the network layer in step 1 specifically includes the following steps:
step 1.4: the CPU0 network layer provides an access interface to the shared memory, writes the packaged data into the shared memory and prompts the driver layer to send out an interrupt; the CPU1 network layer provides tcp network communication interface, which interacts with computer upper computer software reliably, and displays the efficiency of system and signal identification result in real time.
As an optional technical solution, the configuring the hardware circuit in step 2 specifically includes the following steps:
step 2.1: and a hardware circuit is configured, a register is initialized, a BOOT.bin file is read and transmitted to a DDR memory, and then a bit file in the DDR is loaded to an FPGA to generate a North York friend or friend identification signal.
As an optional technical solution, the communication flow between the CPU0 and the CPU1 is as follows:
step 3.1: if the access flag of the CPU0 is true, an interrupt signal is sent to the CPU1 to prompt the CPU1 to analyze the data information transmitted by the CPU0 and upload the data information to the upper computer software through a network interface, and after the data information is analyzed, an interrupt is sent to the CUP0 and the access flag value is false
Step 3.2: if the access flag of the CPU1 is true, an interrupt signal is sent to the CPU0 to prompt the CPU0 to pack the signal transmitted by the FPGA and write the signal into the shared memory, and after the signal is finished, an interrupt signal is sent to the CPU1 to prompt the CPU to acquire information from the shared memory and to enable the access flag value to be false
Step 3.3: the access marks of the two CPUs have mutual exclusion relation, namely, the access marks only have the condition of one true and one false
The invention has the following beneficial effects:
1. the two CPUs can mutually independently execute own functions, run under different operating systems, and simultaneously ensure the running independence of each operating system by utilizing an interrupt mechanism.
2. The shared memory is used for inter-core communication, and the problem of data loss caused by insufficient register space in the traditional SMP mode is solved.
3. The friend or foe identification algorithm is built in, so that the special signals can be accurately identified and uploaded to a computer at a high speed for real-time display.
4. Only the data processing layer function of the CPU0 needs to be modified simply, and hardware does not need to be modified, so that the resource consumption is reduced.
5. The inter-core communication mode based on the AMP architecture is provided, delay and resource consumption caused by the fact that an operating system manages a CPU in an original default SMP architecture are reduced, response time is short, and the problems of data loss and slow transmission caused by frequent interruption when the data volume is large and a plurality of data packets are provided are solved.
Drawings
Fig. 1 illustrates the friend or foe identification signal decision logic of the CPU1 data processing layer of the present invention.
Fig. 2 is a general communication flow diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1 to 2, the present embodiment provides a method for identifying friend or foe identification signals at high speed based on a dual-core AMP architecture, comprising the following steps:
step 1: selecting a chip of zynq7000 series, dividing two CPU functions into a CPU0 and a CPU1, and dividing the CPU0 and the CPU1 into a driving layer, a data processing layer and a network layer;
step 2: the configuration hardware circuit is used for generating signals, acquiring device descriptors and configuring a system clock and interrupt signal generating circuit;
and step 3: configuring a CPU0 to serve as a main core of a dual-core communication system, running a linux system and starting the CPU1 after starting, calling an interface in a driving layer to establish communication, and when data are uploaded on hardware, packaging the data through an interface function and writing the data into a shared memory to realize high-speed transmission of the data;
and 4, step 4: the CPU1 starts and reads the address to jump after receiving the request of the CPU0, monitors the data of the shared memory area, receives the data when the data is uploaded, analyzes the data through an friend or foe identification algorithm formulated by the North convention, starts to process the data and forwards the data to the computer for result display.
The concrete during operation: the method comprises the steps of configuring a hardware layer circuit, initializing a register, reading a BOOT.bin file, transmitting the BOOT.bin file to a DDR memory, then loading a bit file in the DDR to an FPGA to generate a North York friend or friend identification signal, acquiring an equipment descriptor, and configuring a system clock and an interrupt signal generation circuit. As used herein, a signal is 1024 x 4 data generated by a signal source in accordance with the format of a friend or foe identification signal.
And configuring a DMA channel in the xillinx official network to enable the theoretical speed of the DMA channel to reach 400 MB/s. After being started, the CPU0 wakes up linux, and when a generated signal is uploaded to the CPU0 through DMA, the generated signal is repacked by the CPU0 and then uploaded to a designated shared memory, and an interrupt signal is sent to the CPU 1. The CPU1 obtains the information in the shared memory after receiving the interrupt signal, packages the information, and uploads the packaged information to the upper computer software through the TCP interface to display the analysis result.
In this embodiment, when the theoretical rate of DMA is 400MB/s, and when data with packet length of 1024 is sent out, the AMP generates less interrupts, and the rate is increased from 110MB/s to 280MB/s of SMP, which is closer to the theoretical value, because the delay caused by the upper and lower part mechanism of linux system interrupt in SMP mode, and obviously, the AMP mode eliminates this part of delay, so when the number of packets is large, the rate of AMP mode is significantly increased.
Example 2
Preferably, in this embodiment, a hardware layer circuit is configured, a register is initialized, a boot.bin file is read and transmitted to a DDR memory, then a bit file in the DDR is loaded into an FPGA to generate a north-bound friend-foe identification signal, a device descriptor is acquired, and a system clock and interrupt signal generation circuit are configured. As used herein, a signal is 8192 x 4 data generated by a signal source in accordance with the format of a friend or foe identification signal.
And configuring a DMA channel in the xillinx official network to enable the theoretical speed of the DMA channel to reach 400 MB/s. After being started, the CPU0 wakes up linux, and after a generated signal is uploaded to the CPU0 through DMA, the generated signal is repackaged by the CPU0 and then uploaded to a designated shared memory, and an interrupt signal is sent to the CPU 1. The CPU1 obtains the information in the shared memory after receiving the interrupt signal, packages the information, and uploads the packaged information to the upper computer software through the TCP interface to display the analysis result.
In this embodiment, when the theoretical rate of DMA is 400MB/s, and when data with a packet length of 8192 is sent out, the AMP generates less interrupts, and the rate is increased from 270MB/s to 360MB/s of SMP, which is closer to the theoretical value, because of the delay caused by the upper and lower mechanisms of linux system interrupt in SMP mode, while it is obvious that the AMP mode eliminates this delay, when the data packet is large, although the rate is increased by not as much as the rate is increased when the data packet is small, it is obvious that the transmission rate can also be increased.
Example 3
Preferably, in this embodiment, in a previous experiment, the response time of the SMP is generally 100us, and the use of the AMP mode can increase the interrupt response time thereof to 10us, thereby significantly increasing the interrupt speed and increasing the transmission rate.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents and improvements made by those skilled in the art within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A method for identifying friend or foe identification signals at high speed based on a dual-core AMP architecture is characterized by comprising the following steps:
step 1: selecting a chip of zynq7000 series, dividing two CPU functions into a CPU0 and a CPU1, and dividing the CPU0 and the CPU1 into a driving layer, a data processing layer and a network layer;
step 2: the configuration hardware circuit is used for generating signals, acquiring device descriptors and configuring a system clock and interrupt signal generating circuit;
and step 3: configuring a CPU0 to serve as a main core of a dual-core communication system, running a linux system and starting the CPU1 after starting, calling an interface in a driving layer to establish communication, and when data are uploaded on hardware, packaging the data through an interface function and writing the data into a shared memory to realize high-speed transmission of the data;
and 4, step 4: the CPU1 starts and reads the address to jump after receiving the request of the CPU0, monitors the data of the shared memory area, receives the data when the data is uploaded, analyzes the data through an friend or foe identification algorithm formulated by the North convention, starts to process the data and forwards the data to the computer for result display.
2. The method for identifying the friend or foe identification signal at a high speed based on the dual-core AMP architecture according to claim 1, wherein the driving layer in step 1 specifically includes the following steps:
step 1.1: the CPU0 driving layer mainly comprises a xillybus DMA drive provided by the xillybus official, a data interface with a specific register or address is provided according to a communication protocol, description characters of each device are obtained, inter-core data interaction and hardware data uploading are carried out by using the packaged driving interface, and an interrupt signal is sent by using interrupt equipment; the CPU1 driver layer primarily performs the acquisition of shared memory data.
3. The method according to claim 1, wherein the data processing layer in step 1 specifically includes the following steps:
step 1.2: the CPU1 data processing layer processing logic is as follows:
step 1.2.1: setting an initial signal amplitude Threshold, and if the amplitude of the signal to be detected is continuously higher than the Threshold by 1us, storing the pulse signal parameters; if the identification signal does not exist, judging the identification signal as a non-friend identification signal, and terminating identification;
step 1.2.2: randomly searching four adjacent pulses P1, P2, P3 and P4 in the signal pulse TOA, judging the four pulses as interrogation signal leading pulses if the intervals of P1, P2, P3 and P4 are subjected to micro-jump on the basis of 17.375us, 10us and 13us according to the characteristics of the interrogation signals, and sending the four pulses to the next step of judging sidelobe suppression pulses; otherwise, judging the signal as a non-inquiry signal and sending the signal to the next stage of identification process;
step 1.2.3: judging whether the pulse immediately follows the 10.5us or 16.25us, if so, positioning the signal to be in accordance with the inquiry signal of the mode, otherwise, judging the signal to be a friend or foe identification signal;
step 1.3: the CPU0 data processing layer mainly repackages the hardware data to make it adapt to the CPU1 data processing layer structure, and the purpose is to reduce the modification of hardware and save resources.
4. The method for identifying the friend or foe identification signal at a high speed based on the dual-core AMP architecture according to claim 1, wherein the network layer in step 1 specifically includes the following steps:
step 1.4: the CPU0 network layer provides an access interface to the shared memory, writes the packaged data into the shared memory and prompts the driver layer to send out an interrupt; the CPU1 network layer provides tcp network communication interface, which interacts with computer upper computer software reliably, and displays the efficiency of system and signal identification result in real time.
5. The method for identifying the friend or foe identification signal at a high speed based on the dual-core AMP architecture as recited in claim 1, wherein the step 2 of configuring the hardware circuit specifically comprises the following steps:
step 2.1: and a hardware circuit is configured, a register is initialized, a BOOT.bin file is read and transmitted to a DDR memory, and then a bit file in the DDR is loaded to an FPGA to generate a North York friend or friend identification signal.
6. The method for fast identification of friend or foe identification signal based on dual-core AMP architecture as claimed in claim 1, wherein the communication flow between CPU0 and CPU1 is as follows:
step 3.1: if the access flag of the CPU0 is true, an interrupt signal is sent to the CPU1 to prompt the CPU1 to analyze the data information transmitted by the CPU0 and upload the data information to the upper computer software through a network interface, and after the data information is analyzed, an interrupt is sent to the CUP0 and the access flag value is false
Step 3.2: if the access flag of the CPU1 is true, an interrupt signal is sent to the CPU0 to prompt the CPU0 to pack the signal transmitted by the FPGA and write the signal into the shared memory, and after the signal is finished, an interrupt signal is sent to the CPU1 to prompt the CPU to acquire information from the shared memory and to enable the access flag value to be false
Step 3.3: the access marks of the two CPUs have mutual exclusion relation, namely, the condition of true and false exists only.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09330135A (en) * | 1996-06-07 | 1997-12-22 | Denso Corp | Operation characteristic correction device for electronic circuit |
| US20050204080A1 (en) * | 2004-03-11 | 2005-09-15 | International Business Machines Corporation | Method, system, and computer program product for dynamically selecting software buffers for aggregation according to current system characteristics |
| CN101673332A (en) * | 2009-10-12 | 2010-03-17 | 湖南大学 | Kernel code protection method based on Harvard architecture |
| CN101738610A (en) * | 2009-10-16 | 2010-06-16 | 西安电子科技大学 | Parallel collecting and processing device of high-speed multichannel laser echo |
| CN104335546A (en) * | 2012-05-22 | 2015-02-04 | 思科技术公司 | Using neighbor discovery to create trust information for other applications |
| CN105652269A (en) * | 2016-01-05 | 2016-06-08 | 四川九洲电器集团有限责任公司 | Radar system integrated with friend/foe attribute identification device |
| CN106772486A (en) * | 2017-02-17 | 2017-05-31 | 上海华测导航技术股份有限公司 | A kind of GNSS receiver board based on ZYNQ frameworks |
| CN110166975A (en) * | 2019-06-20 | 2019-08-23 | 内蒙古大学 | Agriculture internet of things sensors communication means based on wireless network and raspberry pie node |
| JP2020177544A (en) * | 2019-04-19 | 2020-10-29 | 株式会社ローラン | Linux installation support program |
| CN111913822A (en) * | 2020-08-28 | 2020-11-10 | 电子科技大学 | Inter-core communication mode based on AMP architecture |
| CN113127807A (en) * | 2021-04-19 | 2021-07-16 | 深圳华创电科技术有限公司 | Mode5 leading pulse jitter value calculation method and system based on constrained least square algorithm |
| CN113541823A (en) * | 2020-03-30 | 2021-10-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | General hardware processing platform of CNI comprehensive detector |
| CN114218154A (en) * | 2021-12-09 | 2022-03-22 | 中科航宇(广州)科技有限公司 | On-orbit reconstruction method and device of satellite-borne equipment, electronic equipment and medium |
-
2022
- 2022-06-17 CN CN202210694325.9A patent/CN115098173B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09330135A (en) * | 1996-06-07 | 1997-12-22 | Denso Corp | Operation characteristic correction device for electronic circuit |
| US20050204080A1 (en) * | 2004-03-11 | 2005-09-15 | International Business Machines Corporation | Method, system, and computer program product for dynamically selecting software buffers for aggregation according to current system characteristics |
| CN101673332A (en) * | 2009-10-12 | 2010-03-17 | 湖南大学 | Kernel code protection method based on Harvard architecture |
| CN101738610A (en) * | 2009-10-16 | 2010-06-16 | 西安电子科技大学 | Parallel collecting and processing device of high-speed multichannel laser echo |
| CN104335546A (en) * | 2012-05-22 | 2015-02-04 | 思科技术公司 | Using neighbor discovery to create trust information for other applications |
| CN105652269A (en) * | 2016-01-05 | 2016-06-08 | 四川九洲电器集团有限责任公司 | Radar system integrated with friend/foe attribute identification device |
| CN106772486A (en) * | 2017-02-17 | 2017-05-31 | 上海华测导航技术股份有限公司 | A kind of GNSS receiver board based on ZYNQ frameworks |
| JP2020177544A (en) * | 2019-04-19 | 2020-10-29 | 株式会社ローラン | Linux installation support program |
| CN110166975A (en) * | 2019-06-20 | 2019-08-23 | 内蒙古大学 | Agriculture internet of things sensors communication means based on wireless network and raspberry pie node |
| CN113541823A (en) * | 2020-03-30 | 2021-10-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | General hardware processing platform of CNI comprehensive detector |
| CN111913822A (en) * | 2020-08-28 | 2020-11-10 | 电子科技大学 | Inter-core communication mode based on AMP architecture |
| CN113127807A (en) * | 2021-04-19 | 2021-07-16 | 深圳华创电科技术有限公司 | Mode5 leading pulse jitter value calculation method and system based on constrained least square algorithm |
| CN114218154A (en) * | 2021-12-09 | 2022-03-22 | 中科航宇(广州)科技有限公司 | On-orbit reconstruction method and device of satellite-borne equipment, electronic equipment and medium |
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