CN115085875B - Device and method for realizing safe backup of double encoders - Google Patents

Device and method for realizing safe backup of double encoders Download PDF

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Publication number
CN115085875B
CN115085875B CN202210578386.9A CN202210578386A CN115085875B CN 115085875 B CN115085875 B CN 115085875B CN 202210578386 A CN202210578386 A CN 202210578386A CN 115085875 B CN115085875 B CN 115085875B
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encoder
module
data
control module
logic processing
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CN115085875A (en
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吕文尔
朱常春
王少白
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Shanghai Zhuoxin Medical Technology Co ltd
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Shanghai Zhuoxin Medical Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0014—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the source coding

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

The invention relates to a device and a method for realizing safe backup of double encoders, comprising the following steps: the device comprises a first encoder, a second encoder, a first encoder data acquisition module, a second encoder data acquisition module, a first encoder judgment module, a second encoder judgment module, a selection module, a conversion module and a communication processing module; the first encoder data acquisition module and the second encoder data acquisition module acquire first encoder data and second encoder data respectively, and the first encoder judgment module and the second encoder judgment module judge whether the time sequence of the first encoder and the second encoder acquired by the first encoder data acquisition module and the second encoder data acquisition module is correct or not; the conversion module converts the first and/or second encoder data; the control module transmits corresponding data to the upper computer and sends an instruction to the logic processing module; the upper computer comprises a counting module and a judging module, wherein the counting module is used for counting the times when the first encoder and the second encoder are both in error, and the judging module judges whether the times of the first encoder and the second encoder are both greater than or equal to a threshold value.

Description

Device and method for realizing safe backup of double encoders
Technical Field
The invention relates to the technical field of encoders, in particular to a device and a method for realizing safe backup of double encoders.
Background
Along with the rapid development of the current technology, the application of the encoder is more and more, and the double encoder can be used in the application scenes with high accuracy requirements and low operability requirements, such as the robot field, the big data information screening field, the sensor verification field and the like. Many universal motor drives can be connected with double encoders, but the double encoders of the universal motor drives have two application modes: 1. both encoders are used to control, for example, one for speed control and one for position control; 2. the motor driver is controlled by only one encoder, and the other encoder is read by the upper computer and is controlled by corresponding logic. However, since the technical fields of high precision requirements and low error rate requirements are similar to those of surgical robots, industrial robots and the like, the execution efficiency is also important, and the machine cannot be stopped due to the error of one encoder. Therefore, the safe backup of the data is very important, and the two modes can not realize the function of realizing the safe backup of the two encoders before the access to the driver, namely, when the data of one encoder fails due to errors, the encoder can be timely switched to the other encoder which collects the data to transmit the data instruction, the safety of stable data transmission is enhanced, and the errors are reduced.
Disclosure of Invention
The invention aims at providing a device and a method for realizing safe backup of double encoders aiming at the prior art.
Specifically, a device for realizing safe backup of double encoders includes: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
The signal conversion communication module comprises a first encoder and a second encoder;
The logic processing module comprises a first encoder data acquisition module, a second encoder data acquisition module, a first encoder judgment module, a second encoder judgment module, a selection module, a conversion module and a communication processing module;
The first encoder data acquisition module acquires first encoder data, the second encoder data acquisition module acquires second encoder data, the first encoder judgment module judges whether the first encoder time sequence acquired by the first encoder data acquisition module is correct, and the second encoder judgment module judges whether the second encoder time sequence acquired by the second encoder data acquisition module is correct; the selection module selects correct encoder data to transmit to the control module; the conversion module converts the first encoder and/or the second encoder data; the communication processing module realizes data communication;
the control module transmits corresponding data to the upper computer and sends an instruction to the logic processing module;
The upper computer comprises a counting module and a judging module, wherein the counting module is used for counting the times when the first encoder and the second encoder are in error, and the judging module judges whether the times of the first encoder and the second encoder are in error are larger than or equal to a threshold value.
Further, the first encoder and the second encoder comprise an incremental encoder and an absolute value encoder, or two absolute value encoders with the same function; the delta encoder comprises an ABZ delta encoder or a rotary delta encoder, and the absolute value encoder comprises a single-turn absolute value encoder or a multi-turn absolute value encoder of the SSI/BISS-C bus.
Further, when the first encoder and the second encoder include an incremental encoder and an absolute value encoder, the conversion module converts the data, including converting the incremental encoder data into data that is identical or similar to the absolute value encoder data.
Further, the logic processing module comprises a hardware chip set-up or a programmable logic device software programming, and the programmable logic device comprises a CPLD or an FPGA.
Further, the control module includes a motor driver; the upper computer comprises an operation robot executing end and an industrial robot executing end; the logic processing module judges whether a data transmission stopping instruction is received.
Specifically, a method for realizing safe backup by using double encoders includes:
The method for realizing the safe backup of the double encoder relates to a device for realizing the safe backup of the double encoder, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
step three: the control module transmits corresponding data to the upper computer;
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Further, after the step two is executed, the method further comprises a conversion module, wherein the conversion module converts the encoder data, and the conversion module converts the incremental encoder data into data consistent with or similar to the absolute value encoder data; before executing the step two, the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Further, the method comprises the steps of: in the second step, a corresponding judgment result is input to the control module, which comprises: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
Further, the third step includes: when the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Further, in the fourth step, the method further includes: the counting module and the judging module are used for sending an error clearing instruction to the logic processing module through the control module when the control module transmits the data comprising the second encoder and the first encoder to the upper computer and the upper computer is in an error state; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops operation, and the subsequent data transmission to the upper computer is stopped, so that the upper computer is prevented from being in error and loss caused by executing the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
The invention has the advantages that:
when the data of one encoder fails due to errors, the encoder can be switched to the other encoder which collects the data in time to transmit the data instruction, so that the safety of stable data transmission is enhanced, and the error rate is reduced; the invention judges before data is transmitted to a control module of a motor driver, so that the invention is safe, prepositive, faster and higher in efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a dual encoder implementation security backup device.
Fig. 2 is a flow chart of a method for implementing a secure backup by using a dual encoder.
Fig. 3 is a schematic flow chart of a method for implementing safe backup by using a dual encoder according to an embodiment of the present invention.
Detailed Description
The technical scheme of the present invention will be described in more detail with reference to the accompanying drawings, and the present invention includes, but is not limited to, the following examples.
As shown in fig. 1, a dual encoder implementing a safe backup device according to the present invention includes: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer. The signal conversion communication module comprises a first encoder and a second encoder; the logic processing module comprises a first encoder data acquisition module, a second encoder data acquisition module, a first encoder judgment module, a second encoder judgment module, a selection module, a conversion module and a communication processing module. The logic processing module comprises a hardware chip construction and a programmable logic device software programming, and the programmable logic device comprises a CPLD or an FPGA. The selection module selects correct encoder data to transmit to the control module; the conversion module converts the first encoder and/or the second encoder data; the communication processing module realizes data communication. The first encoder data acquisition module acquires first encoder data, and the second encoder data acquisition module acquires second encoder data, wherein the first encoder and the second encoder comprise at least one absolute value encoder, and concretely comprise an incremental encoder and an absolute value encoder or two absolute value encoders with the same function. The method for implementing backup by two encoders with different functions is that the logic processing module processes encoder data, processes one encoder data to be consistent with or similar to the other encoder data, for example, converts incremental encoder data to be consistent with or similar to absolute value encoder data, for example: the initial value of the absolute value encoder is read, the initial value of the absolute value encoder is added with the value of the incremental encoder to approximate the value of the absolute value encoder, and the resolution of the absolute value encoder and the incremental encoder possibly differ, so that the absolute value encoder is approximate, and the backup function is realized. The encoder comprises an ABZ incremental encoder, a single-turn absolute value encoder or a multi-turn absolute value encoder of the SSI/BISS-C bus, and the incremental encoder comprises an ABZ incremental encoder or a rotary incremental encoder, and the absolute value encoder comprises a single-turn absolute value encoder or a multi-turn absolute value encoder of the SSI/BISS-C bus. The first encoder judging module judges whether the first encoder time sequence acquired by the first encoder data acquisition module is correct or not, the second encoder judging module judges whether the second encoder time sequence acquired by the second encoder data acquisition module is correct or not, and the control module transmits corresponding data to the upper computer and sends an instruction to the logic processing module; the control module includes a motor driver. The host computer still includes: the counting module is used for counting the number of errors of the first encoder and the second encoder, and the judging module judges whether the number of errors of the first encoder and the second encoder is larger than or equal to a threshold value, namely, the threshold value is a whole number which is larger than or equal to 5 and smaller than or equal to 10, such as 5,6,8 and 10, so that errors caused by jitter are prevented, and losses caused by an execution end executing an error instruction are prevented because of too many judging times and too long judging time.
The error prevention caused by jitter means that, since the error of data transmission in each unit time is negligible, when the number of errors of two encoders is not equal to or greater than a threshold, the error caused by jitter is possible, in this case, the first encoder may be correct when the data is converted for the second time, so that whether the timing sequence of the first encoder is correct is judged again at this time, and the data transmission is stopped only because the error caused by jitter is misjudged to be that all the two encoders are wrong, thereby stopping the operation of the upper computer.
Wherein, the upper computer is an operation robot executing end and an industrial robot executing end.
As shown in fig. 2 and fig. 3, a flow chart of a dual-encoder implementing a safe backup method of the present invention includes:
The method for realizing the safe backup of the double encoder relates to a device for realizing the safe backup of the double encoder, which comprises the following steps: the device comprises a signal conversion communication module, a logic processing module, a control module and an upper computer, but is not limited to the device.
Step one: the first encoder data acquisition module in the logic processing module acquires the first encoder data, and the second encoder data acquisition module in the logic processing module acquires the second encoder data.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging result data to the control module.
Wherein, step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the time sequence of the second encoder are correct. The logic processing module firstly judges whether a data transmission stopping instruction is received or not before inputting a corresponding judging result to the control module; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step. Step two, the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder judging module judges that the first encoder time sequence is correct, the logic processing module inputs first encoder data to the control module; if the first encoder judging module judges that the first encoder time sequence is incorrect, the second encoder judging module judges whether the second encoder time sequence is correct or not; if the second encoder judging module judges that the second encoder time sequence is correct, the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state; if the second encoder judging module judges that the second encoder time sequence is incorrect, the logic processing module inputs the first encoder in an error state and the second encoder in an error state to the control module, and the first encoder judging module judges whether the first encoder time sequence is correct again.
The method comprises the steps of judging whether the time sequence is correct or not, converting the encoder data by a conversion module, namely converting the incremental encoder data into data consistent with or similar to the absolute value encoder data, and transmitting the encoder data with the correct time sequence.
Step three: the control module such as a motor driver, a PLC and other main control systems transmit corresponding data to an upper computer such as an operation robot executing end.
When the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state. The data to be transmitted is the data output to the logic processing module by the absolute value encoder, the data output to the control module by the logic processing module or the increment encoder which is consistent with or similar to the absolute value encoder data and is converted by the conversion module is output to the logic processing module, the data output to the control module by the logic processing module is transmitted by the data of the encoder with correct time sequence.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the upper computer, the control module transmits the command for stopping data transmission to the logic processing module, the logic processing module executes the command for stopping data transmission, so that the signal conversion communication module stops working and stops the subsequent data transmission to the upper computer, and the upper computer is prevented from error and loss caused by executing the error command; if the judgment module judges that the count value of the counting module is smaller than the threshold value, the upper computer sends an error clearing instruction to the control module, the control module sends the error clearing instruction to the logic processing module, and the logic processing module executes the error clearing instruction.
One embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
step three: the control module transmits corresponding data to the upper computer;
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module; the conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a selection module and a data communication module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module, a selection module and a data communication module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module. The conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
Step three: the control module transmits corresponding data to the upper computer, and when the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends instructions to the logic processing module through the control module
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module; the conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer, and when the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a selection module and a data communication module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
Step three: the control module transmits corresponding data to the upper computer. When the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module, a selection module and a data communication module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module. The conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer. When the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module.
One embodiment of the present invention for implementing a dual encoder secure backup method includes:
the method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; wherein the host computer includes: the counting module and the judging module are used for judging the number of the electronic devices,
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
step three: the control module transmits corresponding data to the upper computer;
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module; the host computer includes: the counting module and the judging module are used for judging the number of the electronic devices,
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module; the conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a selection module and a data communication module; wherein the host computer includes: a counting module and a judging module;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
the method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module, a selection module and a data communication module, and the upper computer comprises: and the counting module and the judging module.
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module. The conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; wherein, the host computer includes: and the counting module and the judging module.
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
Step three: the control module transmits corresponding data to the upper computer, and when the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module; wherein, the host computer includes: and the counting module and the judging module.
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module; the conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer, and when the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a selection module and a data communication module; wherein, the host computer includes: and the counting module and the judging module.
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
Step three: the control module transmits corresponding data to the upper computer. When the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
Another embodiment of the present invention for implementing a dual encoder secure backup method includes:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer; the logic processing module comprises a conversion module, a selection module and a data communication module; wherein, the host computer includes: and the counting module and the judging module.
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module; the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
Step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequence of the first encoder and the second encoder is correct, and input corresponding judging results to the control module, for example: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module. The conversion module converts the encoder data, including converting the incremental encoder data to data that is consistent with or similar to the absolute value encoder data.
Step three: the control module transmits corresponding data to the upper computer. When the logic processing module inputs the first encoder data to the control module, the control module transmits the first encoder data to the upper computer; when the logic processing module inputs the second encoder data to the control module and inputs that the first encoder is in an error state, the control module transmits the data comprising the second encoder and that the first encoder is in an error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the host computer that the first encoder is in an error state and the second encoder is in an error state.
Step four: the upper computer sends an instruction to the logic processing module through the control module. When the control module transmits the data comprising the second encoder and the first encoder to the upper computer and is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
The present invention is not limited to the above embodiments, and those skilled in the art can implement the present invention in various other embodiments according to the examples and the contents of the drawings, so that the design of the present invention is simply changed or modified while adopting the design structure and concept of the present invention, and the present invention falls within the scope of protection.

Claims (11)

1. An apparatus for implementing a secure backup with a dual encoder, comprising: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
The signal conversion communication module comprises a first encoder and a second encoder;
The logic processing module comprises a first encoder data acquisition module, a second encoder data acquisition module, a first encoder judgment module, a second encoder judgment module, a selection module, a conversion module and a communication processing module;
The first encoder data acquisition module acquires first encoder data, the second encoder data acquisition module acquires second encoder data, the first encoder judgment module judges whether the first encoder time sequence acquired by the first encoder data acquisition module is correct, and the second encoder judgment module judges whether the second encoder time sequence acquired by the second encoder data acquisition module is correct; the selection module selects correct encoder data to transmit to the control module; the conversion module converts the first encoder and/or the second encoder data; the communication processing module realizes data communication;
the control module transmits corresponding data to the upper computer and sends an instruction to the logic processing module;
The upper computer comprises a counting module and a judging module, wherein the counting module is used for counting the times when the first encoder and the second encoder are both in error, and the judging module judges whether the times of the first encoder and the second encoder are both greater than or equal to a threshold value; the first encoder and the second encoder comprise an incremental encoder and an absolute value encoder, or two absolute value encoders with the same function; the incremental encoder comprises an ABZ incremental encoder or a rotary incremental encoder, and the absolute value encoder comprises a single-turn absolute value encoder or a multi-turn absolute value encoder of an SSI/BISS-C bus; when the first encoder and the second encoder comprise an incremental encoder and an absolute value encoder, the conversion module converts the data, including converting the incremental encoder data into data consistent with or similar to the absolute value encoder data.
2. The device for implementing the safe backup of the double encoder according to claim 1, wherein the logic processing module comprises a hardware chip building or a programmable logic device software programming, and the programmable logic device comprises a CPLD or an FPGA.
3. The apparatus for implementing a dual encoder for a safe backup of claim 1, wherein the control module comprises a motor driver; the upper computer comprises an operation robot executing end and an industrial robot executing end; the logic processing module judges whether a data transmission stopping instruction is received.
4. A method for implementing a secure backup for a dual encoder, comprising:
The method for realizing the safe backup of the double encoders relates to a device for realizing the safe backup of the double encoders, which comprises the following steps: the system comprises a signal conversion communication module, a logic processing module, a control module and an upper computer;
Step one: a first encoder data acquisition module in the logic processing module acquires first encoder data in the signal conversion communication module, and a second encoder data acquisition module in the logic processing module acquires second encoder data in the signal conversion communication module;
step two: the first encoder judging module and the second encoder judging module in the logic processing module respectively judge whether the time sequences of the first encoder and the second encoder are correct or not, and input corresponding judging results to the control module;
step three: the control module transmits corresponding data to the upper computer;
Step four: the upper computer sends an instruction to the logic processing module through the control module; after the second step is executed, the method further comprises a conversion module, wherein the conversion module converts the encoder data, and the conversion module converts the incremental encoder data into data consistent with or similar to the absolute value encoder data; before executing the step two, the logic processing module firstly judges whether a data transmission stopping instruction is received or not; if the instruction is received, the logic processing module executes the instruction for stopping data transmission to stop data transmission; if the instruction is not received, executing the second step.
5. The method for implementing a safe backup of a dual encoder as claimed in claim 4, wherein the apparatus includes a selection module and a data communication module, and the step two of inputting the corresponding determination result to the control module includes: the first encoder judging module judges whether the first encoder time sequence is correct or not; if the first encoder data is correct, the selection module selects the first encoder data, and the first encoder data is input to the control module through the data communication module; if not, the second encoder judging module judges whether the second encoder time sequence is correct; if the first encoder data is correct, the selection module selects the first encoder data, inputs the second encoder data to the control module through the data communication module, and inputs that the first encoder is in an error state; if the first encoder data is incorrect, the selection module selects the first encoder data, and the first encoder is in an error state and the second encoder is in an error state are input to the control module through the data communication module.
6. The method for implementing a secure backup of a dual encoder as claimed in claim 4, wherein in said step three, comprising: when the logic processing module inputs first encoder data to the control module, the control module transmits the first encoder data to an upper computer; when the logic processing module inputs the second encoder data to the control module and inputs the first encoder in an error state, the control module transmits the data comprising the second encoder and the first encoder in the error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the upper computer that the first encoder is in an error state and the second encoder is in an error state.
7. The method for implementing a secure backup of a dual encoder as claimed in claim 5, wherein in said step three, comprising: when the logic processing module inputs first encoder data to the control module, the control module transmits the first encoder data to an upper computer; when the logic processing module inputs the second encoder data to the control module and inputs the first encoder in an error state, the control module transmits the data comprising the second encoder and the first encoder in the error state to the upper computer; when the logic processing module inputs to the control module that the first encoder is in an error state and the second encoder is in an error state, the control module transmits to the upper computer that the first encoder is in an error state and the second encoder is in an error state.
8. The method for implementing safe backup of double encoders according to claim 4, wherein in the fourth step, the apparatus further comprises a counting module and a judging module, and when the control module transmits the data including the second encoder to the upper computer and the first encoder is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
9. The method for implementing safe backup of double encoders according to claim 5, wherein in the fourth step, the apparatus further comprises a counting module and a judging module, and when the control module transmits the data including the second encoder to the upper computer and the first encoder is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
10. The method for implementing safe backup of double encoders according to claim 6, wherein in the fourth step, the apparatus further comprises a counting module and a judging module, and when the control module transmits the data including the second encoder to the upper computer and the first encoder is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
11. The method for implementing safe backup of double encoders according to claim 7, wherein in the fourth step, the apparatus further comprises a counting module and a judging module, and when the control module transmits the data including the second encoder to the upper computer and the first encoder is in an error state, the upper computer sends an error clearing instruction to the logic processing module through the control module; when the control module transmits a command for stopping data transmission to the logic processing module through the control module, the signal conversion communication module stops working, the subsequent data transmission to the upper computer is stopped, and the loss caused by the error of the upper computer and the execution of the error command is prevented; if the error is smaller than the threshold value, the upper computer sends an error clearing instruction to the logic processing module through the control module.
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