CN115085679A - Signal predistortion circuit architecture - Google Patents

Signal predistortion circuit architecture Download PDF

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Publication number
CN115085679A
CN115085679A CN202110265285.1A CN202110265285A CN115085679A CN 115085679 A CN115085679 A CN 115085679A CN 202110265285 A CN202110265285 A CN 202110265285A CN 115085679 A CN115085679 A CN 115085679A
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circuit
receiving
signal
analog
digital
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王文山
徐铭均
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

A signal predistortion circuit architecture comprises a digital predistortion circuit, a first transceiver circuit, a first analog front end circuit, a second transceiver circuit and a second analog front end circuit, and has better signal path isolation. The digital predistortion circuit outputs a first digital transmission signal according to at least one first predistortion parameter and a second digital transmission signal according to at least one second predistortion parameter, and determines whether to adjust the at least one first predistortion parameter according to a first digital receiving signal and determines whether to adjust the at least one second predistortion parameter according to a second digital receiving signal. The transmission circuit of the first transceiver circuit, the first analog front-end circuit and the receiving circuit of the second transceiver circuit generate the first digital receiving signal according to the first digital transmission signal. The transmission circuit of the second transceiver circuit, the second analog front-end circuit and the receiving circuit of the first transceiver circuit generate the second digital receiving signal according to the second digital transmission signal.

Description

Signal predistortion circuit architecture
Technical Field
The present invention relates to a circuit architecture, and more particularly, to a signal predistortion circuit architecture.
Background
Generally, a Digital Predistortion (DPD) circuit is used to remove non-linearity of an analog circuit, such as a power amplifier. For example, fig. 1 shows a conventional wireless circuit architecture 100 including a Digital Signal Processor (DSP) 110, a DPD circuit 120, a transmit path 130, a front-end modulator (FEM) 140, and a receive path 150, wherein the transmit path 130 includes a digital-to-analog converter (DAC) 132, an up-converter 134, and a Power Amplifier (PA) 136, the receive path 150 includes a Low Noise Amplifier (LNA) 152, a down-converter 154, and an analog-to-digital converter (ADC) 156, and the FEM 140 transmits/receives signals via an antenna in a communication mode. When determining the digital predistortion parameters, the DPD circuit 120 outputs a predistortion signal according to a default signal and the digital predistortion parameters, and the predistortion signal returns to the DPD circuit 120 through the transmission path 130, the transmission end (Tx) and the reception end (Rx) of the FEM 140, and the reception path 150, so that the DPD circuit 120 adjusts the digital predistortion parameters according to the difference between the received signal and the default signal, wherein the default signal may be generated by the DPD circuit 120 itself or from the DSP 110. However, in order to save circuit area, the layout distance between the transmission path 130 and the reception path 150 is usually small, which results in poor isolation between the transmission path 130 and the reception path 150, and significant signal coupling between the paths, which prevents the DPD circuit 120 from correctly determining the digital predistortion parameters.
To solve the above problem, a common way is to provide an additional receiving path as shown in fig. 2. Compared to fig. 1, the wireless circuit architecture 200 of fig. 2 further includes a coupler (coupler)210, a feedback circuit 220 and a switch 230, the feedback circuit 220 being, for example, a circuit similar/equal to the LNA 152 and the downconverter 154. When determining the digital predistortion parameters, the DPD circuit 120 outputs a predistortion signal according to a default signal and the digital predistortion parameters, and the predistortion signal returns to the DPD circuit 120 through the transmission path 130, the transmission end (Tx) of the FEM 140, the coupler 210, the feedback circuit 220, the switch 230 and the ADC 156, so that the DPD circuit 120 adjusts the digital predistortion parameters according to the difference between the received signal and the default signal. Since the distance between the feedback path 220 and the transmission path 130 is longer than the distance between the receiving path 150 and the transmission path 130, this approach has better isolation effect, but requires additional pin (pin) and circuit area, which results in increased cost.
Yet another solution is: under the architecture of fig. 1, the requirement of signal to interference ratio (SIR) is reduced, and thus the requirement of isolation between the tx path 130 and the rx path 150 is reduced. However, the above method requires better performance of the noise suppression algorithm and circuit design capability, which greatly increases the cost and design difficulty.
Disclosure of Invention
It is therefore an objective of the claimed invention to provide a signal predistortion circuit architecture to avoid the problems of the prior art.
The invention provides a signal predistortion circuit architecture, which comprises a digital predistortion circuit, a first transmission circuit, a first receiving circuit, a second transmission circuit, a second receiving circuit, a first analog front end circuit and a second analog front end circuit. The digital predistortion circuit is used for outputting a first digital transmission signal according to at least one first predistortion parameter and outputting a second digital transmission signal according to at least one second predistortion parameter, and determining whether to adjust the at least one first predistortion parameter according to a first digital receiving signal and determining whether to adjust the at least one second predistortion parameter according to a second digital receiving signal. The first transmission circuit is used for transmitting a first analog transmission signal according to the first digital transmission signal. The first receiving circuit is used for transmitting the second digital receiving signal to the digital predistortion circuit according to a second analog receiving signal. The second transmission circuit is used for transmitting a second analog transmission signal according to the second digital transmission signal. The second receiving circuit is used for transmitting the first digital receiving signal to the digital pre-distortion circuit according to a first analog receiving signal, wherein a minimum layout distance between the first transmitting circuit and the first receiving circuit is smaller than a minimum layout distance between the first transmitting circuit and the second receiving circuit, and a minimum layout distance between the second transmitting circuit and the second receiving circuit is smaller than a minimum layout distance between the second transmitting circuit and the first receiving circuit. The first analog front-end circuit is coupled between the first transmission circuit and the second receiving circuit and used for generating the first analog receiving signal according to the first analog transmission signal. The second analog front-end circuit is coupled between the second transmission circuit and the first receiving circuit and used for generating a second analog receiving signal according to the second analog transmission signal.
The features, operation and efficacy of the present invention will be described in detail in the following description of the preferred embodiments with reference to the accompanying drawings.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present application will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 illustrates a conventional wireless circuit architecture;
FIG. 2 illustrates another conventional wireless circuit architecture;
FIG. 3 shows an embodiment of a signal predistortion circuit architecture of the present invention;
FIG. 4 shows an embodiment of the first transmitting circuit, the first receiving circuit, the second transmitting circuit and the second receiving circuit of FIG. 3; and
fig. 5 shows another embodiment of the first transmitting circuit, the first receiving circuit, the second transmitting circuit and the second receiving circuit of fig. 3.
Detailed Description
The invention discloses a signal predistortion circuit architecture which can improve the isolation effect between a transmission path and a receiving path when Digital Predistortion (DPD) training is executed in a very low cost mode so as to improve the efficacy of the DPD.
Fig. 3 shows an embodiment of the signal predistortion circuit architecture of the present invention. The signal predistortion circuit architecture 300 of fig. 3 includes a Digital Signal Processor (DSP) 310, a DPD circuit 320, a first transmission circuit 330, a first receiving circuit 340, a second transmission circuit 350, a second receiving circuit 360, a first analog front end circuit 370 and a second analog front end circuit 380, wherein the first transmission circuit 330, the first receiving circuit 340 and the first analog front end circuit 370 as a whole have functions similar to/equal to the functions of the second transmission circuit 350, the second receiving circuit 360 and the second analog front end circuit 380 as a whole.
As mentioned above, for example, the signal predistortion circuit architecture 300 is applied to a multiple-input multiple-output (MIMO) wireless communication device (not shown); the first transmission circuit 330 includes a first rf transmission circuit (not shown); the first analog front-end circuit 370 includes a first front-end modulator (FEM) (not shown) for transmitting signals from the transmitting end (Tx1) to the receiving end (Rx1) in a training mode and transmitting/receiving signals via an antenna in a communication mode; the first receiving circuit 340 includes a first rf receiving circuit (not shown); the second transmission circuit 350 includes a second rf transmission circuit (not shown); the second analog front-end circuit 380 includes a second front-end modulator (not shown) for transmitting signals from the transmitting end (Tx2) to the receiving end (Rx2) in a training mode, and transmitting/receiving signals via an antenna in a communication mode; the second receiving circuit 360 includes a second rf receiving circuit (not shown); and the DSP circuit 310 and the DPD circuit 320 are included in a digital baseband circuit (not shown). For another example, the signal predistortion circuit architecture 300 is applied to an audio device (not shown); the first transmission circuit 330 includes a first digital-to-analog converter (DAC) (not shown); the first analog front-end circuit 370 includes a first amplifier (not shown) for transmitting signals from the transmitting end (Tx1) to the receiving end (Rx1) in a training mode, and for transmitting signals to or receiving signals from an external device (e.g., speaker/earphone) in a play mode; the first receiving circuit 340 includes a first analog-to-digital converter (ADC) (not shown); the second transmission circuit 350 includes a second DAC (not shown); the second analog front-end circuit 380 includes a second amplifier (not shown) for transmitting signals from the transmitting end (Tx2) to the receiving end (Rx2) in a training mode, and transmitting signals to or receiving signals from an external device (e.g., speaker/earphone) in a play mode; the second receiving circuit 360 includes a second ADC (not shown); and the DSP circuit 310 and the DPD circuit 320 are included in a digital audio circuit. The circuits not shown are all well known in the art, and details thereof are omitted herein.
Please refer to fig. 3. The first transmission circuit 330 is disposed beside the first receiving circuit 340, and the isolation between the two circuits may be insufficient; the second transmitting circuit 350 is disposed beside the second receiving circuit 360, and the isolation between the two circuits may be insufficient. To avoid the effect of DPD from being affected by insufficient isolation, the signal predistortion circuit architecture 300 uses the first transmission circuit 330, the first analog front end circuit 370 and the second reception circuit 360 as a signal loop for a first DPD training, and uses the second transmission circuit 350, the second analog front end circuit 380 and the first reception circuit 340 as a signal loop for a second DPD training. Since the minimum layout distance between the first transmitting circuit 330 and the second receiving circuit 360 is much larger than the minimum layout distance between the first transmitting circuit 330 and the first receiving circuit 340, the isolation between the first transmitting circuit 330 and the second receiving circuit 360 is relatively better, and the influence on the efficiency of the DPD can be reduced. Similarly, since the minimum layout distance between the second transmission circuit 350 and the first reception circuit 340 is much larger than the minimum layout distance between the second transmission circuit 350 and the first reception circuit 360, the isolation between the second transmission circuit 350 and the first reception circuit 340 is relatively better, and the influence on the efficiency of DPD can be reduced.
Please refer to fig. 3. When performing the first DPD training, the DPD circuit 320 processes a first original signal according to at least one first predistortion parameter to output a first digital transmission signal, which is returned to the DPD circuit 320 via the first transmission circuit 330, the transmitting end (Tx1) of the first analog front-end circuit 370, the receiving end (Rx1) of the first analog front-end circuit 370, and the second receiving circuit 360, so that the DPD circuit 320 determines whether to adjust the at least one first predistortion parameter according to a difference between a signal received by the DPD circuit (i.e., the first digital received signal) and the first original signal, which may be self-generated by the DPD circuit 320 (where the DSP 310 is not necessary) or from the DSP 310, thereby reducing the difference or ensuring that the difference is small enough to achieve the effect of DPD. When performing a second DPD training, the DPD circuit 320 processes a second original signal according to at least one second predistortion parameter to output a second digital transmission signal, which is returned to the DPD circuit 320 via the second transmission circuit 350, the transmitting end (Tx2) and the receiving end (Rx2) of the second analog front-end circuit 380, and the first receiving circuit 340, so that the DPD circuit 320 determines whether to adjust at least one second predistortion parameter according to a difference between a signal received by the DPD circuit (i.e., the second digital reception signal) and the second original signal, which may be generated by the DPD circuit 320 itself (at this time, the DSP 310 is not necessary), or from the DSP 310, to reduce the difference or ensure that the difference is small enough to achieve the effect of DPD. The first digital receiving signal reflects a first nonlinear effect caused by the first transmitting circuit 330, the first analog front-end circuit 370 and the second receiving circuit 360; the second digital receiving signal reflects a second nonlinear effect caused by the second transmitting circuit 350, the second analog front-end circuit 380 and the first receiving circuit 340. The digital predistortion circuit 320 reduces/eliminates the first nonlinear effect by adjusting the at least one first predistortion parameter, and reduces/eliminates the second nonlinear effect by adjusting the at least one second predistortion parameter.
The above description is provided. The first transmission circuit 330 is used for transmitting a first analog transmission signal according to the first digital transmission signal. The first receiving circuit 340 is used for transmitting the second digital receiving signal to the DPD circuit 320 according to a second analog receiving signal. The second transmission circuit 350 is used for transmitting a second analog transmission signal according to the second digital transmission signal. The second receiving circuit 360 is used for transmitting the first digital receiving signal to the DPD circuit 320 according to a first analog receiving signal. The first analog front-end circuit 370 is coupled between the first transmitting circuit 330 and the second receiving circuit 360 for generating the first analog receiving signal according to the first analog transmitting signal. The second analog front-end circuit 380 is coupled between the second transmission circuit 350 and the first receiving circuit 340, and is configured to generate the second analog receiving signal according to the second analog transmission signal.
In one exemplary implementation, the first transmitting circuit 330, the first receiving circuit 340, the second transmitting circuit 350 and the second receiving circuit 360 are included in an integrated circuit (labeled "IC" in fig. 3), and the DPD circuit 320 may be included in the integrated circuit or in another integrated circuit. The first analog front-end circuit 370 and the second analog front-end circuit 380 are disposed on a circuit board (e.g., a printed circuit board) (such as the "PCB" shown in fig. 3) and are located outside the integrated circuit. The first analog front-end circuit 370 is coupled to the second receiving circuit 360 via a first trace of the circuit board and a first connection interface (e.g., pins or solder balls) (not shown). The second analog front-end circuit 380 is coupled to the first receiving circuit 340 via a second trace of the circuit board and a second connection interface (e.g., pins or solder balls) (not shown).
Fig. 4 shows an embodiment of the first transmitting circuit 330, the first receiving circuit 340, the second transmitting circuit 350 and the second receiving circuit 360 of fig. 3. The first transfer circuit 330 includes a first DAC 332 and a first transfer circuit 334 (e.g., a circuit including an upconverter and a power amplifier, wherein the power amplifier generally has a non-linear characteristic). The first DAC 332 is used for generating a first conversion signal according to the first digital transmission signal; the first transmission circuit 334 is used for generating the first analog transmission signal according to the first conversion signal. The first receiving circuit 340 includes a first receiving circuit 342 (e.g., a circuit including a low noise amplifier and a down converter) and a first ADC 344. The first receiving circuit 342 is used for generating a second signal to be converted according to the second analog receiving signal; the first ADC 344 is used for generating the second digital receiving signal according to the second signal to be converted. Similarly, the second transmission circuit 350 includes a second DAC 352 and a second transmission circuit 354 (e.g., a circuit including an upconverter and a power amplifier, wherein the power amplifier generally has a non-linear characteristic). The second DAC 352 is used for generating a second conversion signal according to the second digital transmission signal; the second transmitting circuit 354 is used for generating the second analog transmitting signal according to the second converting signal. The second receiving circuit 360 includes a second receiving circuit 362 (e.g., a circuit including a low noise amplifier and a down converter) and a second ADC 364. The second receiving circuit 362 is used for generating a first signal to be converted according to the first analog receiving signal; the second ADC 364 is used for generating the first digital receiving signal according to the first signal to be converted.
Please refer to fig. 4. In an exemplary embodiment, the signal predistortion circuit architecture 300 is applied to a wireless communication device, and further comprises a first switching circuit 410 and a second switching circuit 420. The first switching circuit 410 is used for coupling the first analog front-end circuit 370 and the second receiving circuit 360 in a training mode, and for coupling the first analog front-end circuit 370 and the first receiving circuit 340 in a communication mode. The second switching circuit 420 is used for coupling the second analog front-end circuit 380 and the first receiving circuit 340 in the training mode, and for coupling the second analog front-end circuit 380 and the second receiving circuit 360 in the communication mode. The DSP 310 is used for receiving and processing a first communication signal via the first analog front-end circuit 370, the first switch circuit 410 and the first receiving circuit 340 in the communication mode, and receiving and processing a second communication signal via the second analog front-end circuit 380, the second switch circuit 420 and the second receiving circuit 360 in the communication mode, wherein the first communication signal originates from a first wireless communication object (not shown), the second communication signal originates from the first wireless communication object or a second wireless communication object (not shown), and the first wireless communication object/the second wireless communication object performs wireless communication with the wireless communication device. In short, the signal receiving path in the training mode is different from the signal receiving path in the communication mode.
Please refer to fig. 4. The first digital receiving signal reflects a first nonlinear effect caused by the first transmitting circuit 330, the first analog front-end circuit 370 and the second receiving circuit 360; the second digital receiving signal reflects a second non-linear effect caused by the second transmitting circuit 350, the second analog front-end circuit 380 and the first receiving circuit 340. The contribution of the second receiving circuit 360 to the first nonlinear effect is similar to the contribution of the first receiving circuit 340 to the second nonlinear effect (e.g., the difference between the two contributions is at least less than-10 dB), so as to ensure that the parameters obtained in the training mode can be applied in the communication mode; or the second receiving circuit 360 contributes much less to the first nonlinear effect than the first transmitting circuit 330 and the first analog front-end circuit 370 (e.g., the difference between the two contributions is at least greater than 10dB), and the first receiving circuit 340 contributes much less to the second nonlinear effect than the second transmitting circuit 350 and the second analog front-end circuit 380 contribute to the second nonlinear effect (e.g., the difference between the two contributions is at least greater than 10 dB).
Please refer to fig. 3 and the description of fig. 3-4. In an implementation example, the signal receiving path in the training mode is the same as the signal receiving path in the communication mode; in this case, the first switch circuit 410 and a second switch circuit 420 of fig. 4 are not necessary, and the DSP 310 is configured to receive and process the first communication signal via the first analog front-end circuit 370 and the second receiving circuit 360 in the communication mode, and receive and process the second communication signal via the second analog front-end circuit 380 and the first receiving circuit 340 in the communication mode. Since the details of the foregoing embodiments and examples can be understood by those skilled in the art, the repetitive and redundant descriptions are omitted here.
It is noted that, in the communication mode, the DPD circuit 320 may not adjust the at least one first predistortion parameter, and may not adjust the at least one second predistortion parameter; alternatively, in the communication mode, the DPD circuit 320 determines whether to adjust the at least one first predistortion parameter according to the first wireless communication signal, and determines whether to adjust the at least one second predistortion parameter according to the second wireless communication signal.
Fig. 5 shows another embodiment of the first transmitting circuit 330, the first receiving circuit 340, the second transmitting circuit 350 and the second receiving circuit 360. The first transmission circuit 330 includes a first DAC 502 for generating the first analog transmission signal according to the first digital transmission signal. The first receiving circuit 340 includes a first ADC 504 for generating the second digital receiving signal according to the second analog receiving signal. The second transmission circuit 350 includes a second DAC506 for generating the second analog transmission signal according to the second digital transmission signal. The second receiving circuit 360 includes a second ADC 508 for generating the first digital receiving signal according to the first analog receiving signal.
Please refer to fig. 5. In an exemplary embodiment, the signal predistortion circuit architecture 300 is applied to an audio device, and further includes a first switch circuit 510 and a second switch circuit 520. The first switching circuit 510 is used for coupling the first analog front-end circuit 370 and the second receiving circuit 360 in a training mode, and for coupling the first analog front-end circuit 370 and the first receiving circuit 340 in a play mode. The second switch circuit 520 is used for coupling the second analog front-end circuit 380 and the first receiving circuit 340 in the training mode, and for coupling the second analog front-end circuit 380 and the second receiving circuit 360 in the play mode. The DSP 310 is used for receiving and processing a first audio signal (e.g., a first audio control signal from a speaker/earphone) via the first analog front-end circuit 370, the first switch circuit 510 and the first receiving circuit 340 in the playback mode, and receiving and processing a second audio signal (e.g., a second audio control signal from the speaker/earphone) via the second analog front-end circuit 380, the second switch circuit 520 and the second receiving circuit 360 in the playback mode. In short, the signal receiving path in the training mode is different from the signal receiving path in the play mode. It is noted that the above descriptions of the contributions of the first nonlinear effect and the second nonlinear effect also apply to the present embodiment. It is noted that, in the playback mode, the DPD circuit 320 may not adjust the at least one first predistortion parameter, and may not adjust the at least one second predistortion parameter; alternatively, in the playback mode, the DPD circuit 320 determines whether to adjust the at least one first predistortion parameter according to the first audio signal, and determines whether to adjust the at least one second predistortion parameter according to the second audio signal.
Please refer to fig. 3 and the descriptions of fig. 3 and fig. 5. In one implementation, the training mode signal reception path is the same as the communication mode signal reception path; in this case, the first switch circuit 510 and the second switch circuit 520 of fig. 5 are not necessary, and the DSP 310 is used for receiving and processing the first audio signal via the first analog front-end circuit 370 and the second receiving circuit 360 in the play mode, and receiving and processing the second audio signal via the second analog front-end circuit 380 and the first receiving circuit 340 in the play mode. Since the details of the foregoing embodiments and examples can be understood by those skilled in the art, the repetitive and redundant descriptions are omitted here.
It should be noted that, when the implementation is possible, a person having ordinary skill in the art can selectively implement some or all of the features in any of the above embodiments, or selectively implement a combination of some or all of the features in the above embodiments, so as to increase the flexibility of implementing the invention.
In summary, the present invention can improve the isolation between the transmission path and the reception path when performing DPD training with little cost, so as to improve the efficiency of DPD.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations are within the scope of the patent protection sought by the present invention.
Description of reference numerals:
100: wireless circuit architecture
110: DSP (digital signal processor)
120: DPD circuit (digital predistortion circuit)
130: conveying path
132: DAC (digital-to-analog converter)
134: frequency booster
136: PA (Power amplifier)
140: FEM (front modulator)
Tx: transmitting terminal
Rx: receiving end
150: receiving path
152: LNA (Low noise amplifier)
154: frequency demultiplier
156: ADC (analog-to-digital converter)
200: wireless circuit architecture
210: coupler
220: feedback circuit
230: switching device
300: signal predistortion circuit architecture
310: DSP (digital signal processor)
320: DPD circuit (digital predistortion circuit)
330: first transmission circuit
340: first receiving circuit
350: second transmission circuit
360: second receiving circuit
370: first analog front-end circuit
380: second analog front-end circuit
Tx 1: transmitting terminal of first analog front end circuit
Rx 1: receiving end of first analog front-end circuit
Tx 2: transmitting end of second analog front end circuit
Rx 2: receiving end of second analog front-end circuit
IC: integrated circuit with a plurality of integrated circuits
PCB: printed circuit board
332: first DAC (first digital-to-analog converter)
334: first transmission circuit
342: first receiving circuit
344: first ADC (first analog-to-digital converter)
352: second DAC
354: second transmission circuit
362: second receiving circuit
364: second ADC
410: first switching circuit
420: second switching circuit
502: first DAC
504: first ADC
506: second DAC
508: second ADC
510: first switching circuit
520: a second switching circuit.

Claims (10)

1. A signal predistortion circuit architecture comprising:
a digital predistortion circuit, for outputting a first digital transmission signal according to at least one first predistortion parameter and outputting a second digital transmission signal according to at least one second predistortion parameter, and determining whether to adjust the at least one first predistortion parameter according to a first digital receiving signal and determining whether to adjust the at least one second predistortion parameter according to a second digital receiving signal;
a first transmission circuit for transmitting a first analog transmission signal according to the first digital transmission signal;
a first receiving circuit for transmitting the second digital receiving signal to the digital pre-distortion circuit according to a second analog receiving signal;
a second transmission circuit for transmitting a second analog transmission signal according to the second digital transmission signal;
a second receiving circuit for transmitting the first digital receiving signal to the digital pre-distortion circuit according to a first analog receiving signal, wherein a minimum layout distance between the first transmitting circuit and the first receiving circuit is smaller than a minimum layout distance between the first transmitting circuit and the second receiving circuit, and a minimum layout distance between the second transmitting circuit and the second receiving circuit is smaller than a minimum layout distance between the second transmitting circuit and the first receiving circuit;
a first analog front-end circuit coupled between the first transmission circuit and the second reception circuit for generating the first analog reception signal according to the first analog transmission signal; and
a second analog front-end circuit, coupled between the second transmission circuit and the first receiving circuit, for generating the second analog receiving signal according to the second analog transmission signal.
2. The signal predistortion circuit architecture of claim 1, wherein the first transmit circuit, the first receive circuit, the second transmit circuit and the second receive circuit are included in an integrated circuit; the first analog front-end circuit and the second analog front-end circuit are arranged on a circuit board and are positioned outside the integrated circuit; and the first analog front-end circuit is coupled with the second receiving circuit through a first wire of the circuit board, and the second analog front-end circuit is coupled with the first receiving circuit through a second wire of the circuit board.
3. The signal predistortion circuit architecture of claim 1, wherein:
the first transmission circuit includes:
a first digital-to-analog converter for generating a first converted signal according to the first digital transmission signal; and
a first transmission circuit for generating the first analog transmission signal according to the first conversion signal;
the first receiving circuit includes:
a first receiving circuit for generating a second signal to be converted according to the second analog receiving signal; and
a first analog-to-digital converter for generating the second digital receiving signal according to the second signal to be converted;
the second transmission circuit includes:
a second DAC for generating a second converted signal according to the second digital transmission signal; and
a second transmission circuit for generating the second analog transmission signal according to the second conversion signal;
the second receiving circuit includes:
a second receiving circuit for generating a first signal to be converted according to the first analog receiving signal; and
the second analog-to-digital converter is used for generating the first digital receiving signal according to the first signal to be converted.
4. The signal predistortion circuit architecture as claimed in claim 3, wherein said signal predistortion circuit architecture is comprised in a wireless communication device; the first transmission circuit comprises a first radio frequency transmission circuit, the first analog front-end circuit comprises a first front-end modulator, and the first receiving circuit comprises a first radio frequency receiving circuit; the second transmission circuit comprises a second radio frequency transmission circuit, the second analog front-end circuit comprises a second front-end modulator, and the second receiving circuit comprises a second radio frequency receiving circuit; and the digital predistortion circuit is included in a baseband circuit.
5. The signal predistortion circuit architecture of claim 4, further comprising:
a first switching circuit for coupling the first analog front-end circuit and the second receiving circuit in a training mode and coupling the first analog front-end circuit and the first receiving circuit in a communication mode;
a second switching circuit, for coupling the second analog front-end circuit and the first receiving circuit in the training mode, and for coupling the second analog front-end circuit and the second receiving circuit in the communication mode; and
a digital signal processor, coupled to the first receiving circuit and the second receiving circuit, for receiving and processing a first communication signal via the first analog front end circuit, the first switching circuit and the first receiving circuit in the communication mode, and receiving and processing a second communication signal via the second analog front end circuit, the second switching circuit and the second receiving circuit in the communication mode, wherein the first communication signal originates from a first wireless communication object, and the second communication signal originates from the first wireless communication object or a second wireless communication object.
6. The signal predistortion circuit architecture of claim 4, further comprising:
a first circuit for coupling the first analog front-end circuit and the second receiving circuit in a training mode and for coupling the first analog front-end circuit and the second receiving circuit in a communication mode;
a second circuit for coupling the second analog front-end circuit and the first receiving circuit in the training mode and for coupling the second analog front-end circuit and the first receiving circuit in the communication mode; and
a digital signal processor, coupled to the first receiving circuit and the second receiving circuit, for receiving and processing a first communication signal via the first analog front-end circuit and the second receiving circuit in the communication mode, and receiving and processing a second communication signal via the second analog front-end circuit and the first receiving circuit in the communication mode, wherein the first communication signal originates from a first wireless communication object, and the second communication signal originates from the first wireless communication object or a second wireless communication object.
7. The signal predistortion circuit architecture of claim 1, wherein:
the first transmission circuit includes:
a first digital-to-analog converter for generating the first analog transmission signal according to the first digital transmission signal;
the first receiving circuit includes:
a first analog-to-digital converter for generating the second digital receiving signal according to the second analog receiving signal;
the second transmission circuit includes:
a second DAC for generating the second analog transmission signal according to the second digital transmission signal; and
the second receiving circuit includes:
a second analog-to-digital converter for generating the first digital receiving signal according to the first analog receiving signal.
8. The signal predistortion circuit architecture as claimed in claim 7, wherein the signal predistortion circuit architecture is included in an audio device; the first analog front-end circuit comprises a first amplifier; the second analog front-end circuit includes a second amplifier.
9. The signal predistortion circuit architecture of claim 8, further comprising:
a first switching circuit for coupling the first analog front-end circuit and the second receiving circuit in a training mode and coupling the first analog front-end circuit and the first receiving circuit in a play mode;
a second switching circuit for coupling the second analog front-end circuit and the first receiving circuit in the training mode and coupling the second analog front-end circuit and the second receiving circuit in the play mode; and
a digital signal processor, coupled to the first receiving circuit and the second receiving circuit, for receiving and processing a first audio signal via the first analog front-end circuit, the first switching circuit and the first receiving circuit in the playback mode, and receiving and processing a second audio signal via the second analog front-end circuit, the second switching circuit and the second receiving circuit in the playback mode.
10. The signal predistortion circuit architecture of claim 8, further comprising:
a first circuit for coupling the first analog front-end circuit and the second receiving circuit in a training mode and for coupling the first analog front-end circuit and the second receiving circuit in a play mode;
a second circuit for coupling the second analog front-end circuit and the first receiving circuit in the training mode and for coupling the second analog front-end circuit and the first receiving circuit in the play mode; and
a digital signal processor, coupled to the first receiving circuit and the second receiving circuit, for receiving and processing a first communication signal via the first analog front-end circuit and the second receiving circuit in the playback mode, and receiving and processing a second communication signal via the second analog front-end circuit and the first receiving circuit in the playback mode, wherein the first communication signal originates from a first wireless communication object, and the second communication signal originates from the first wireless communication object or a second wireless communication object.
CN202110265285.1A 2021-03-11 2021-03-11 Signal predistortion circuit architecture Pending CN115085679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110265285.1A CN115085679A (en) 2021-03-11 2021-03-11 Signal predistortion circuit architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110265285.1A CN115085679A (en) 2021-03-11 2021-03-11 Signal predistortion circuit architecture

Publications (1)

Publication Number Publication Date
CN115085679A true CN115085679A (en) 2022-09-20

Family

ID=83241148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110265285.1A Pending CN115085679A (en) 2021-03-11 2021-03-11 Signal predistortion circuit architecture

Country Status (1)

Country Link
CN (1) CN115085679A (en)

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