CN115084163A - TFT array substrate, display screen and manufacturing method of TFT array substrate - Google Patents

Abstract

The application discloses TFT array substrate is applied to the display screen. The TFT array substrate comprises a substrate and a plurality of transistors arranged at intervals, the transistors comprise a grid electrode, an active layer, a source electrode, a drain electrode and a grid electrode insulating layer arranged between the grid electrode and the active layer, the transistors comprise a first transistor and a second transistor, and the thickness of the grid electrode insulating layer of the first transistor is smaller than that of the grid electrode insulating layer of the second transistor. In the present application, the display panel includes a light-emitting region, and the plurality of transistors are covered with the light-emitting region. The brightness of the light emitting area corresponding to the transistor is adjusted by changing the thickness of the gate insulating layer of the transistor, and the brightness uniformity of the light emitting area of the display screen is guaranteed.

Description

TFT array substrate, display screen and manufacturing method of TFT array substrate

Technical Field

The application relates to the technical field of display, in particular to a TFT array substrate, a display screen and a manufacturing method of the TFT array substrate.

Background

Due to the limitation of equipment and process, the performance of devices at different positions of the TFT array substrate is different, so that the brightness of a light emitting area of the display screen is uneven, optical Mura is generated, marks such as spots and the like are generated, the display performance of the display screen is influenced, and the use experience of a user is poor.

Disclosure of Invention

The application provides a TFT array substrate, a display screen and a manufacturing method of the TFT array substrate. The brightness of the light emitting area corresponding to the transistor is adjusted by changing the thickness of the gate insulating layer of the transistor, and the brightness uniformity of the light emitting area of the display screen is guaranteed.

The application provides a TFT array substrate, is applied to the display screen, its characterized in that, TFT array substrate includes the transistor that substrate and a plurality of interval set up, and the transistor includes grid, active layer, source electrode, drain electrode and sets up the gate insulation layer between grid and active layer, and a plurality of transistors include first transistor and second transistor, and the thickness of the gate insulation layer of first transistor is less than the thickness of the gate insulation layer of second transistor.

According to the display screen, the thickness of the first grid electrode insulating layer is reduced, the on-state current of the first transistor is compensated, and the brightness of the first light emitting area is increased, so that the brightness of the display screen is uniform, and the use experience of a user is improved.

In one possible implementation manner, the display screen includes a light emitting region, the plurality of transistors are covered by the light emitting region, and under the condition that the thicknesses of the gate insulating layer of the first transistor and the gate insulating layer of the second transistor are equal, the luminance of the first light emitting region corresponding to the first transistor is smaller than the luminance of the second light emitting region corresponding to the second transistor.

In the related art, due to limitations of equipment and processes, luminance of a light emitting region of a display screen is not uniform, for example, luminance of a first light emitting region is smaller than luminance of a second light emitting region. In this implementation, can guarantee the homogeneity of luminance through the luminance that increases first luminescence area, promote the display effect of display screen. In other embodiments, the brightness of the second light-emitting region may also be reduced to ensure brightness uniformity.

In one possible implementation, the active layer is located on one side of the gate insulating layer, the active layer includes a source contact region, a drain contact region, and a channel region, and the channel region is located between the source contact region and the drain contact region; the gate insulating layer corresponds to the channel region; the grid is positioned on one side of the grid insulating layer, which is back to the channel region; and the source electrode and the drain electrode are respectively connected with two ends of the source layer, the source electrode is electrically connected with the source electrode contact region, and the drain electrode is electrically connected with the drain electrode contact region.

In a possible implementation manner, the TFT array substrate further includes a dielectric layer, the dielectric layer covers the plurality of transistors, and the dielectric layer is provided with a first through hole and a second through hole corresponding to each active layer; the source electrode is electrically connected with the source electrode contact region through the first through hole, and the drain electrode is electrically connected with the drain electrode contact region through the second through hole.

In a possible implementation manner, the TFT array substrate further includes a blocking layer, a buffer layer, and a substrate disposed on a side of the active layer opposite to the gate insulating layer, and the active layer, the blocking layer, the buffer layer, and the substrate are sequentially stacked.

In a possible implementation manner, the TFT array substrate further includes a passivation layer, and the passivation layer covers the plurality of transistors.

The application also provides a display screen which comprises the TFT array substrate in the implementation mode. In the application, the brightness of the light emitting area of the display screen is uniform, and the user experience is good.

The application also provides a manufacturing method of the TFT array substrate. In this implementation, the TFT array substrate includes a substrate and a plurality of transistors arranged at intervals, each transistor includes a gate electrode, an active layer, a source electrode, a drain electrode, and a gate insulating layer arranged between the gate electrode and the active layer, and each transistor includes a first transistor and a second transistor;

the display screen comprises a light-emitting area, the plurality of transistors are covered by the light-emitting area, and the light-emitting area comprises a first light-emitting area and a second light-emitting area;

in this implementation, the manufacturing method includes:

forming a first active layer corresponding to the first transistor and a second active layer corresponding to the second transistor on the substrate;

and forming a first gate insulating layer corresponding to the first active layer and a second gate insulating layer corresponding to the second active layer on one side of the active layers, which faces away from the substrate, wherein the thickness of the first gate insulating layer is smaller than that of the second gate insulating layer.

The manufacturing method of the TFT array substrate provided by the application has no new film layer and new manufacturing process, cannot influence and damage manufacturing equipment of the TFT array substrate, cannot reduce a manufacturing process limit (Margin), and keeps the feasibility of the manufacturing process.

In one possible implementation, the light emitting region includes a first light emitting region and a second light emitting region; the manufacturing method further comprises the following steps:

under the condition that the thickness of the first gate insulating layer is equal to that of the second gate insulating layer, judging the magnitude relation between the brightness of the first light-emitting area and the brightness of the second light-emitting area, and setting the thickness of the gate insulating layer corresponding to the light-emitting area according to the judgment result;

if the brightness of the first light-emitting area is smaller than that of the second light-emitting area, reducing the thickness of the gate insulating layer corresponding to the first light-emitting area; and if the brightness of the first light-emitting area is greater than that of the second light-emitting area, reducing the thickness of the gate insulating layer corresponding to the second light-emitting area.

In the application, the thickness of the first gate insulating layer of the first transistor is smaller than that of the second gate insulating layer of the second transistor, and the first transistor corresponds to the light emitting region with lower brightness, so that the brightness of the light emitting region with lower brightness can be increased, and the brightness uniformity is ensured.

In one possible implementation, forming a first gate insulating layer corresponding to the first active layer and a second gate insulating layer corresponding to the second active layer on a side of the plurality of active layers opposite to the substrate includes:

forming a first insulating layer on the substrate, the first insulating layer covering the plurality of active layers;

forming a photoresist layer on one side of the first insulating layer, which is opposite to the substrate;

exposing the photoresist layer by first exposure light, wherein the first exposure light is emitted by an ultraviolet light source and irradiates the photoresist layer through a halftone mask;

developing the exposed photoresist layer to form a photoresist pattern consisting of a plurality of photoresist blocks; the photoresist pattern comprises a first photoresist block corresponding to the first active layer and a second photoresist block corresponding to the second active layer, and the thickness of the first photoresist block is smaller than that of the second photoresist block;

transferring the photoresist pattern onto the first insulating layer, specifically, etching the first insulating layer, removing the first insulating layer which is not covered by the photoresist pattern, and forming a first insulating block corresponding to the first active layer and a second insulating block corresponding to the second active layer;

ashing the light resistance pattern, removing the first photoresist block in the light resistance pattern, and enabling the second photoresist block to form a third photoresist block;

etching the plurality of insulating blocks, and thinning the first insulating block to form a first grid insulating layer, wherein the thickness of the first grid insulating layer is smaller than that of the second insulating block;

and removing the third photoresist block to expose the second insulating block to form a second gate insulating layer.

In one possible implementation, a patterning process for a photoresist layer includes:

the plurality of photoresist blocks comprise a first photoresist block and a second photoresist block; the half-tone mask comprises a first light-transmitting area, a second light-transmitting area and a third light-transmitting area, wherein the light transmittance of the first light-transmitting area is greater than that of the second light-transmitting area, and the light transmittance of the third light-transmitting area is greater than that of the first light-transmitting area; the first light-transmitting area corresponds to the area where the first photoresist block is located, the second light-transmitting area corresponds to the area where the second photoresist block is located, and a part of the photoresist layer corresponding to the third light-transmitting area is removed.

It is understood that the difference in light transmittance can affect the thickness of the resist block after exposure and development. In this implementation, the smaller the light transmittance, the greater the thickness of the resist block after exposure and development. The half tone mask adopted by the application has different light transmittance areas, and can form photoresist blocks with different thicknesses, so that gate insulating layers with different thicknesses can be formed. Therefore, the thickness of the gate insulating layer can be adjusted as required, so that the on-state current of the transistor can be adjusted, and the brightness of the light-emitting region can be changed to ensure the brightness uniformity of the light-emitting region.

In one possible implementation, the process of making the substrate includes:

forming a buffer layer on a substrate;

and forming a barrier layer on the side of the buffer layer opposite to the substrate.

In a possible implementation manner, the method for manufacturing the TFT array substrate further includes:

forming a first grid electrode corresponding to the first grid electrode insulating layer and a second grid electrode corresponding to the second grid electrode insulating layer on one side, back to the substrate, of the grid electrode insulating layers, wherein the distance between the first grid electrode and the first active layer is smaller than that between the second grid electrode and the second active layer;

forming a dielectric layer on the substrate, wherein the dielectric layer covers the plurality of active layers, the plurality of gate insulation layers and the plurality of gates, and the dielectric layer is provided with a first through hole and a second through hole corresponding to each active layer;

and forming a source electrode and a drain electrode on one side of the dielectric layer, which faces away from the substrate, wherein the source electrode is electrically connected with the active layer through the first through hole, and the drain electrode is electrically connected with the active layer through the second through hole.

In a possible implementation manner, the method for manufacturing the TFT array substrate further includes:

and forming a passivation film on the side of the dielectric layer opposite to the substrate, wherein the passivation film covers the source electrode, the drain electrode and the dielectric layer.

Drawings

FIG. 1A is a schematic diagram of a prior art display panel and a TFT array substrate;

fig. 1B is a schematic view of a display panel and a TFT array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic view of the internal structure of the TFT array substrate shown in fig. 1B;

FIG. 3 is a schematic flow chart of a method for fabricating the TFT array substrate shown in FIG. 2;

FIG. 4 is a schematic view of step S1 of the flowchart of FIG. 3;

FIG. 5 is a schematic view of step S2 of the flowchart of FIG. 3;

fig. 6 is a schematic diagram of forming a gate on a substrate in step S3 in the flow shown in fig. 3;

fig. 7 is a schematic diagram of forming a source and a drain on a substrate in step S3 in the flow chart shown in fig. 3;

fig. 8 is a flowchart illustrating a specific method for fabricating the first gate insulating layer and the second gate insulating layer in step S2 shown in fig. 3;

FIG. 9 is a diagram illustrating step S21 of the flowchart of FIG. 8;

FIG. 10 is a diagram illustrating step S22 of the flowchart of FIG. 8;

FIG. 11 is a diagram illustrating step S23 of the flowchart of FIG. 8;

fig. 12 is a schematic view of step S24 in the flowchart shown in fig. 8;

FIG. 13 is a diagram illustrating step S25 of the flowchart of FIG. 8;

fig. 14 is a schematic view of step S26 in the flowchart shown in fig. 8;

fig. 15 is a schematic diagram of step S27 in the flowchart shown in fig. 8.

Detailed Description

The embodiments of the present application will be described below with reference to the drawings. In the description of the embodiments of the present application, the "plurality" means two or more than two unless otherwise specified. "above" includes the present numbers, for example, two or more include two.

The embodiment of the application provides a display screen. The display screen can be applied to an electronic device with a display function, such as any electronic product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, and the like.

For example, the display screen may adopt a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED) display screen, an active-matrix organic light-emitting diode (AMOLED) display screen, a flexible light-emitting diode (FLED) display screen, a MiniLED display screen, a Micro led display screen, a Micro-OLED display screen, a quantum dot light-emitting diode (QLED) display screen, and the like. The embodiment of the application takes the display screen as an OLED display screen as an example for explanation.

Referring to fig. 1A, fig. 1A is a schematic diagram of a display screen 1000 and a TFT array substrate 100 in the prior art, and fig. 1B is a schematic diagram of the display screen 1000 and the TFT array substrate 100 according to an embodiment of the present disclosure. In the embodiment of the present application, the display screen 1000 may include an OLED device (not shown) and the TFT array substrate 100. The TFT array substrate 100 may include a plurality of transistors (not shown). A transistor may be connected in series with the OLED device for providing an on-state current to cause the OLED device to emit light.

For example, the display screen 1000 may include a light emitting region, and the plurality of transistors of the TFT array substrate 100 are covered by the light emitting region. The light emitting region may include a first light emitting region 1001 and a second light emitting region 1002, the first light emitting region 1001 may be located at a central region, and the second light emitting region 1002 may be disposed around the first light emitting region 1001.

In the related art, due to limitations of equipment and processes, luminance of a light emitting region of the display screen 1000 is not uniform, for example, luminance of the first light emitting region 1001 is smaller than luminance of the second light emitting region 1002. In this embodiment, the brightness of the first light-emitting area 1001 can be increased to ensure the uniformity of the brightness, thereby improving the display effect of the display screen 1000. In other embodiments, the brightness of the second light emitting region 1002 may also be reduced to ensure brightness uniformity.

Specifically, referring to fig. 2, fig. 2 is a schematic diagram of an internal structure of the TFT array substrate 100 shown in fig. 1B. Illustratively, the TFT array substrate 100 may include a plurality of transistors (10,20) arranged at intervals and a substrate 1. The substrate 1 may include a barrier layer 13, a buffer layer 12, and a base 11. The barrier layer 13, the buffer layer 12, and the substrate 11 are stacked in this order, and the transistors (10,20) are fixed to the barrier layer 13 on the side opposite to the buffer layer 12.

Illustratively, each transistor (10,20) includes a gate electrode (61,62), an active layer (31,32), a gate insulating layer (411,421), a source electrode 71, and a drain electrode 72. Wherein the active layers (31,32) are fixed on the side of the barrier layer 13 facing away from the buffer layer 12. A gate insulating layer (411,421) is disposed between the gate electrode (61,62) and the active layer (31, 32). Illustratively, the active layer (31,32) may include a source contact region, a drain contact region, and a channel region. The channel region may be located between the source contact region and the drain contact region. The gate insulating layer (411,421) may correspond to the channel region. The gate electrode (61,62) may be located on a side of the gate insulation layer (411,421) facing away from the channel region. The source electrode 71 and the drain electrode 72 are connected to both ends of the active layers (31,32), respectively, and the source electrode 71 is electrically connected to the source contact region and the drain electrode 72 is electrically connected to the drain contact region.

Illustratively, the plurality of transistors (10,20) may include a plurality of first transistors 10 and a plurality of second transistors 20. The plurality of first transistors 10 correspond to the first light emitting region 1001, and the plurality of second transistors 20 correspond to the second light emitting region 1002. The first transistor 10 includes a first gate insulating layer 411, the second transistor 20 includes a second gate insulating layer 421, and the thickness of the first gate insulating layer 411 is smaller than that of the second gate insulating layer 421.

Referring to fig. 1A, 1B and 2 together, in the prior art, due to the limitations of the equipment and the process, the brightness of the light-emitting region of the display screen 1000 is not uniform. That is, when the thickness of the first gate insulating layer 411 is equal to that of the second gate insulating layer 421, the luminance of the first light emitting region 1001 corresponding to the first transistor 10 is lower than the luminance of the first light emitting region 1002 corresponding to the second transistor 20. By reducing the thickness of the first gate insulating layer 411, the on-state current of the first transistor 10 is compensated, and the brightness of the first light emitting region 1001 is increased, so that the brightness of the display screen 1000 is uniform.

Specifically, the gate electrode (61,62), the active layer (31,32), and the gate insulating layer (411,421) form a parallel plate capacitor having a gate insulating layer capacitance C _0X . Understandably, C _0X Is inversely proportional to the thickness of the gate insulating layer (411,421), i.e. C can be varied by varying the thickness of the gate insulating layer (411,421) _0X . Furthermore, C _0X Is proportional to the on-current of the transistor (10,20) and determines the luminance of the OLED device.

The present application enables the gate insulation layer capacitance C of the first transistor 10 by reducing the thickness of the first gate insulation layer 411 _0X The on-state current of the first transistor 10 is increased to increase the brightness of the first light emitting region 1001, thereby ensuring the brightness of the display screen 1000Uniformity, the problem of luminous zone luminance inhomogeneous that causes because the restriction of panel preparation equipment and technology etc. is solved, promote user's use experience.

For example, the substrate 11 may be made of glass, or may be made of flexible PI (polyimide resin) for carrying other structures of the TFT array substrate 100.

Referring to fig. 3, fig. 3 is a flow chart illustrating a method for manufacturing the TFT array substrate 100 shown in fig. 2.

The specific flow of the manufacturing method of the TFT array substrate is as follows:

s1: referring to fig. 4, fig. 4 is a schematic diagram of step S1 in the flowchart of fig. 3. Manufacturing a substrate 1, specifically, forming a buffer layer 12 on a base 11; a barrier layer 13 is formed on the buffer layer 12 on the side facing away from the substrate 11. A first active layer 31 corresponding to the first transistor 10 and a second active layer 32 corresponding to the second transistor 20 are formed on the substrate 1.

S2: referring to fig. 5, fig. 5 is a schematic diagram of step S2 in the flowchart of fig. 3. A first gate insulating layer 411 is formed on the side of the first active layer 31 facing away from the substrate 1, and a second gate insulating layer 421 is formed on the side of the second active layer 32 facing away from the substrate 1, wherein the thickness of the first gate insulating layer 411 is smaller than that of the second gate insulating layer 421. In the embodiment, the gate 6 insulating layer is formed on the side of the active layer (31,32) opposite to the substrate 1, so that the interface state between the gate insulating layer (411,421) and the active layer (31,32) can be effectively reduced, and the device characteristics of the transistor can be improved.

S3: referring to fig. 6 and 7 together, fig. 6 is a schematic diagram of forming gates (61,62) on the substrate 1 in step S3 in the flowchart shown in fig. 3, and fig. 7 is a schematic diagram of forming a source 71 and a drain 72 on the substrate 1 in step S3 in the flowchart shown in fig. 3.

A gate electrode (61,62), a source electrode 71 and a drain electrode 72 are formed on the substrate 1.

Specifically, a first gate electrode 61 is formed on a side of the first gate insulating layer 411 facing away from the substrate 1, a second gate electrode 62 is formed on a side of the second gate insulating layer 421 facing away from the substrate 1, and a distance between the first gate electrode 61 and the first active layer 31 is smaller than a distance between the second gate electrode 62 and the second active layer 32;

forming a dielectric layer 8 on the substrate 1, the dielectric layer 8 covering the plurality of active layers (31,32), the plurality of gate insulating layers (411,421) and the plurality of gate electrodes (61,62), the dielectric layer 8 being provided with a first via hole and a second via hole corresponding to each active layer (31, 32);

a source electrode 71 and a drain electrode 72 are formed on the side of the dielectric layer 8 facing away from the substrate 1, the source electrode 71 being electrically connected to the active layers (31,32) via a first via, and the drain electrode 72 being electrically connected to the active layers (31,32) via a second via.

S4: referring to fig. 2, a passivation film 9 is formed on a side of dielectric layer 8 opposite to substrate 1, and passivation film 9 covers source electrode 71, drain electrode 72 and dielectric layer 8.

The manufacturing method of the TFT array substrate 100 provided by the application has no new film layer and new manufacturing process, cannot influence and damage manufacturing equipment of the TFT array substrate 100, cannot reduce a manufacturing process limit (Margin), and keeps the feasibility of the manufacturing process.

For example, referring to fig. 1A, fig. 1B and fig. 2 together, the method for manufacturing the TFT array substrate 100 may further include determining a magnitude relationship between the luminance of the first light emitting region 1001 and the luminance of the second light emitting region 1002 when the thicknesses of the first gate insulating layer 411 and the second gate insulating layer 421 are equal; and the thickness of the gate insulating layer (411,421) corresponding to the light emitting region (1001, 1002) is set according to the determination result. Specifically, if the luminance of the first light emitting region 1001 is smaller than the luminance of the second light emitting region 1002, the thickness of the gate insulating layer corresponding to the first light emitting region 1001 is reduced. If the luminance of the first light emitting region 1001 is higher than the luminance of the second light emitting region 1002, the thickness of the gate insulating layer 421 corresponding to the second light emitting region 1002 can be reduced.

In the embodiment of the present application, the case where the luminance of the first light-emitting region 1001 is smaller than the luminance of the second light-emitting region 1002 will be described. That is, the first light emitting region 1001 corresponds to the first gate insulating layer 411, and the second light emitting region 1002 corresponds to the second gate insulating layer 421. In the present application, the thickness of the first gate insulating layer 411 is smaller than the thickness of the second gate insulating layer 421, and thus the luminance of the first light-emitting region 1001 with low luminance can be increased, and the luminance uniformity can be ensured.

Referring to fig. 8, fig. 8 is a flowchart illustrating a specific method for fabricating the first gate insulating layer 411 and the second gate insulating layer 421 in step S2 shown in fig. 3. Specifically, the manufacturing process of the first gate insulating layer 411 and the second gate insulating layer 421 is as follows:

s21: referring to fig. 9, fig. 9 is a schematic diagram of step S21 in the flowchart shown in fig. 8. A first insulating layer 4 is formed on the substrate 1, and the first insulating layer 4 covers the first active layer 31 and the second active layer 32.

S22: referring to fig. 10, fig. 10 is a schematic diagram of step S22 in the flowchart shown in fig. 8. A photoresist layer 5 is formed on the side of the first insulating layer 4 facing away from the substrate 1.

S23: referring to fig. 11, fig. 11 is a schematic diagram of step S23 in the flowchart shown in fig. 8. The photoresist layer 5 is exposed by first exposure light, the first exposure light is emitted by an ultraviolet light source and irradiates the photoresist layer 5 through a halftone mask 50, so that the photoresist layer 5 forms a first photoresist region 51, a second photoresist region 52 and a third photoresist region 53, the first photoresist region 51 corresponds to a region where a pattern of the first gate insulating layer 411 is located, the second photoresist region 52 corresponds to a region where a pattern of the second gate insulating layer 421 is located, and the third photoresist region 53 corresponds to other regions of the photoresist layer 5 except the first photoresist region 51 and the second photoresist region 52.

S24: referring to fig. 11 and 12 together, fig. 12 is a schematic diagram of step S24 in the flowchart shown in fig. 8. The exposed photoresist layer 5 is developed to form a photoresist pattern composed of the first photoresist block 511 and the second photoresist block 521. Specifically, the photoresist layer 5 of the third photoresist region 53 is removed, the photoresist layer 5 of the first photoresist region 51 forms the first photoresist block 511, and the photoresist layer 5 of the second photoresist region 52 forms the first photoresist block 511; the thickness of the first photoresist block 511 is less than the thickness of the second photoresist block 521.

S25: referring to fig. 13, fig. 13 is a schematic diagram of step S25 in the flowchart of fig. 8. The photoresist pattern is transferred onto the first insulating layer 4. Specifically, the first insulating layer 4 is etched, and the first insulating layer 4 not covered by the photoresist pattern is removed, thereby forming a first insulating block 41 corresponding to the first active layer 31 and a second insulating block 42 corresponding to the second active layer 32.

S26: referring to fig. 13 and 14 together, fig. 14 is a schematic diagram of step S26 in the flow chart shown in fig. 8. The photoresist pattern is ashed to remove the first photoresist block 511 in the photoresist pattern, and the second photoresist block 521 is formed into a third photoresist block 5211.

S27: referring to fig. 14 and 15 together, fig. 15 is a schematic diagram of step S27 in the flowchart of fig. 8. And etching the plurality of insulating blocks (41, 42), and thinning the first insulating block 41 to form a first gate insulating layer 411, wherein the thickness of the first gate 6 insulating layer 411 is smaller than that of the second insulating block 42.

S28: please refer to fig. 5. The third photoresist block 5211 is removed to expose the second insulating block 42 to form the second gate 6 insulating layer 421.

Illustratively, the specific manufacturing method of the halftone mask 50 in step S23 is as follows:

s231: on-state currents of different areas are calculated according to the brightness distribution of the light-emitting area of the display screen 1000, and the thickness of the gate insulating layer of the TFT array substrate 100 corresponding to the different areas is calculated through the on-state currents. Illustratively, the thickness of the first gate insulating layer 411 is obtained according to the luminance of the first light emitting region 1001, and the thickness of the second gate insulating layer 421 is obtained according to the luminance of the second light emitting region 1002.

Referring to fig. 1A and 1B together, for example, the display panel 1000 may include a first light emitting region 1001 and a second light emitting region 1002, and the luminance of the first light emitting region 1001 is lower than that of the second light emitting region 1002, so that the thickness of the first gate insulating layer 411 corresponding to the first light emitting region 1001 should be reduced.

S232: the halftone mask 50 is designed and obtained based on the thickness of the gate insulating layer (411,412) calculated in S231.

Specifically, referring to fig. 5, 11 and 12, the halftone mask 50 includes a first transparent region 51a, a second transparent region 52a and a third transparent region 53a, wherein the light transmittance of the first transparent region 51a is greater than the light transmittance of the second transparent region 52a and less than the light transmittance of the third transparent region 53a, that is, the light transmittance of the third transparent region 53a is the largest, and the light transmittance of the second transparent region 52a is the smallest. The first light-transmitting region 51 corresponds to the first photoresist region 51, and the first photoresist region 51 corresponds to the first gate insulating layer 411. The second light-transmitting region 52 corresponds to the second photoresist region 52, and the second photoresist region 52 corresponds to the second gate insulating layer 421. The third light transmission region 53 corresponds to the third photoresist region 53 and is removed in step S24.

It is understood that the difference in light transmittance can affect the thickness of the resist block after exposure and development. In this embodiment, the smaller the light transmittance, the larger the thickness of the resist block after exposure and development. The halftone mask 50 adopted by the application has different light transmittance regions, and can form photoresist blocks with different thicknesses, so that gate insulating layers with different thicknesses can be formed. Therefore, the thickness of the gate insulating layer can be adjusted as required, so that the on-state current of the transistor can be adjusted, and the brightness of the light-emitting region can be changed to ensure the brightness uniformity of the light-emitting region.

Illustratively, the halftone mask 50 may be obtained by processing a mask that is originally present in a manufacturing apparatus of the TFT array substrate 100. The treatment method can be to apply the shading paint on the specific position of the original mask. Specifically, the original mask may include a fourth light-transmission region and a fifth light-transmission region. The light transmittance of the fourth light transmission area is smaller than that of the fifth light transmission area. The fourth light-transmitting region may be used as the second light-transmitting region 52a of the halftone mask 50. Further, a light-shielding paint may be applied to a partial region of the fifth light-transmitting region as the first light-transmitting region 51a of the halftone mask 50, and a region where the light-shielding paint is not applied may be used as the third light-transmitting region 53a, such that the first light-transmitting region 51a has a light transmittance greater than that of the second light-transmitting region 52a and less than that of the third light-transmitting region 53 a. In the present embodiment, the halftone mask 50 is obtained by processing the original mask, and the manufacturing cost and steps of the halftone mask 50 are eliminated. Moreover, the halftone mask 50 is obtained on the basis of the original mask, has high adaptability with other manufacturing equipment, and cannot influence and damage the manufacturing equipment.

Illustratively, the halftone mask 50 may also be obtained by fabricating regions having different light transmittances on the substrate. Specifically, a first mask layer may be deposited on the substrate, and the first mask layer may be patterned to remove a portion of the first mask layer to form a second mask layer. The region where the second mask layer is located is the second light-transmitting region 52a, and the region where the second mask layer is removed by the first mask layer is the sixth light-transmitting region. And depositing a third mask layer on the second mask layer, wherein the light transmittance of the third mask layer is smaller than that of the second mask layer. The third mask layer may fill the sixth light transmission region. And finally, carrying out patterning treatment on the third mask layer, and removing part of the third mask layer positioned in the sixth light-transmitting area to form a fourth mask layer. The region where the fourth mask layer is located is the first light-transmitting region 51 a. The region corresponding to the removed third mask layer is the third light-transmitting region 53 a.

Understandably, other methods may be adopted to manufacture the halftone mask 50 as long as the halftone mask 50 has three regions with sequentially increased light transmittance, which is not limited in the embodiment of the present application.

Referring to fig. 9, for example, in step S21, a first insulating layer 4 may be deposited on the active layer by Plasma Enhanced Chemical Vapor Deposition (PECVD). The first insulating layer 4 may be made of an oxide, a nitride, or an oxynitride, for example: SiOx, SiNx, SiON, and the like. The reaction gas corresponding to SiOx, SiNx and SiON may be SiH ₄ 、NH ₃ 、N ₂ Or SiH ₂ Cl ₂ 、NH ₃ 、N ₂ . In some other embodiments, the first insulating layer 4 may also be made of an organic insulating material or a High k (High dielectric constant) material, such as: AlOx, HfOx, TaOx, and the like.

Illustratively, the step S3 may further include performing a conductor process on the active layer (31,32) not covered by the gate insulating layer (411,421) to form a source electrode 71 contact region and a drain electrode 72 contact region of the active layer.

Referring to fig. 2, in the present embodiment, after the conductive treatment is performed on the active layers (31,32), the conductivity of the source electrode 71 contact region and the drain electrode 72 contact region of the active layers (31,32) can be improved, and the device characteristics of the transistors (10,20) can be improved. Wherein the conductive treatment of the active layers (31,32) includes, but is not limited to, plasma treatment.

Illustratively, the active layers (31,32) may be made of oxides, elemental silicon, organic materials, etc., such as a-IGZO, ZnON, IZTO, a-Si, p-Si, hexathiophene, polythiophene, etc.

Referring to fig. 7, for example, in the embodiment of the present application, in step S3, the gate electrode (61,62), the source electrode 71 and the drain electrode 72 may also be formed through a single patterning process. In the embodiment, the gate electrodes (61,62), the source electrode 71 and the drain electrode 72 do not need to be prepared by patterning for multiple times, so that the patterning times and the production time in the manufacturing process of the TFT array substrate 100 can be further saved, and the manufacturing cost can be reduced.

The specific process is as follows:

s31: a conductive layer (not shown) is deposited on the sides of the first gate insulating layer 411 and the second gate insulating layer 421 facing away from the substrate 1, covering the plurality of active layers (31,32) and the plurality of gate insulating layers (411, 421). A photoresist layer (not shown) is coated on the conductive layer.

S32: the photoresist layer is exposed by a second exposure light, which is emitted by the ultraviolet light source and irradiated on the photoresist layer through the mask, so that a fourth photoresist region (not shown) and a fifth photoresist region (not shown) are formed on the photoresist layer. Specifically, the fourth photoresist region corresponds to a region where the patterns of the source electrode 71, the drain electrode 72 and the gate electrode (61,62) are located, and the fifth photoresist region corresponds to other regions of the photoresist layer except for the fourth photoresist region.

S33: and developing the exposed photoresist layer, completely removing the photoresist layer in the fifth photoresist region, keeping the thickness of the photoresist layer in the fourth photoresist region unchanged, and forming a fourth photoresist block (not shown).

S34: and etching the conductive layer, and removing the conductive layer which is not covered by the fourth photoresist block to form conductive blocks corresponding to the gate electrodes (61,62), the source electrode 71 and the drain electrode 72.

S35: the fourth photoresist block is removed and the conductive blocks are exposed to form gate electrodes (61,62), source electrodes 71 and drain electrodes 72.

Illustratively, the conductive layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The conductive layer may be a single layer structure or a multi-layer structure. The multilayer structure can be a Cu \ Mo, Ti \ Cu \ Ti, Mo \ Al \ Mo and other structures. The conductive layer can also adopt a stack structure formed by metal and transparent conductive oxide (such as ITO, AZO and the like) such as ITO/Ag/ITO and the like.

Illustratively, the conductive layer may be deposited by sputtering or thermal evaporation.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application; the embodiments and features of the embodiments of the present application may be combined with each other without conflict. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (15)

1. The TFT array substrate is applied to a display screen and is characterized by comprising a substrate and a plurality of transistors arranged at intervals, wherein each transistor comprises a grid electrode, an active layer, a source electrode, a drain electrode and a grid electrode insulating layer arranged between the grid electrode and the active layer, the plurality of transistors comprise a first transistor and a second transistor, and the thickness of the grid electrode insulating layer of the first transistor is smaller than that of the grid electrode insulating layer of the second transistor.

2. The TFT array substrate according to claim 1, wherein the display panel includes a light emitting region, the plurality of transistors are covered with the light emitting region, and a luminance of a first light emitting region corresponding to the first transistor is smaller than a luminance of a second light emitting region corresponding to the second transistor when the gate insulating layer of the first transistor and the gate insulating layer of the second transistor are equal in thickness.

3. The TFT array substrate of claim 2,

the active layer is positioned on one side of the gate insulating layer and comprises a source contact region, a drain contact region and a channel region, and the channel region is positioned between the source contact region and the drain contact region;

the grid electrode is positioned on one side, back to the channel region, of the grid electrode insulating layer; and the number of the first and second groups,

the source electrode and the drain electrode are respectively connected with two ends of the active layer, the source electrode is electrically connected with the source electrode contact region, and the drain electrode is electrically connected with the drain electrode contact region.

4. The TFT array substrate of claim 3, wherein the gate insulating layer corresponds to the channel region.

5. The TFT array substrate of claim 3 or 4, further comprising a dielectric layer covering the plurality of transistors, the dielectric layer being provided with a first via and a second via corresponding to each of the active layers; the source electrode is electrically connected with the source electrode contact region through the first through hole, and the drain electrode is electrically connected with the drain electrode contact region through the second through hole.

6. The TFT array substrate of any one of claims 3 to 5, wherein the substrate is disposed on a side of the active layer facing away from the gate insulating layer, the substrate comprises a barrier layer, a buffer layer, and a base, and the active layer, the barrier layer, the buffer layer, and the base are sequentially stacked.

7. The TFT array substrate of any of claims 1-6, further comprising a passivation layer covering the plurality of transistors.

8. A display panel comprising the TFT array substrate according to any one of claims 1 to 7.

9. A manufacturing method of a TFT array substrate is applied to a display screen and is characterized in that the TFT array substrate comprises a substrate and a plurality of transistors arranged at intervals, the transistors comprise a grid electrode, an active layer, a source electrode, a drain electrode and a grid electrode insulating layer arranged between the grid electrode and the active layer, and the transistors comprise a first transistor and a second transistor;

the display screen comprises a light-emitting area, and a plurality of transistors are covered by the light-emitting area;

the manufacturing method comprises the following steps:

forming a first active layer corresponding to the first transistor and a second active layer corresponding to the second transistor on the substrate;

and forming a first gate insulating layer corresponding to the first active layer and a second gate insulating layer corresponding to the second active layer on one side of the active layers, which faces away from the substrate, wherein the thickness of the first gate insulating layer is smaller than that of the second gate insulating layer.

10. The method of manufacturing a TFT array substrate as set forth in claim 9, wherein the light-emitting region includes a first light-emitting region and a second light-emitting region;

the manufacturing method further comprises the following steps:

judging the magnitude relation between the brightness of the first light-emitting area and the brightness of the second light-emitting area under the condition that the thickness of the first gate insulating layer is equal to that of the second gate insulating layer, and setting the thickness of the gate insulating layer corresponding to the light-emitting area according to the judgment result;

if the brightness of the first light-emitting area is smaller than that of the second light-emitting area, reducing the thickness of the gate insulating layer corresponding to the first light-emitting area; and if the brightness of the first light-emitting area is greater than that of the second light-emitting area, reducing the thickness of the gate insulating layer corresponding to the second light-emitting area.

11. The method for manufacturing the TFT array substrate according to claim 9 or 10, wherein the forming a first gate insulating layer corresponding to the first active layer and a second gate insulating layer corresponding to the second active layer on a side of the plurality of active layers facing away from the substrate includes:

forming a first insulating layer on the substrate, the first insulating layer covering the plurality of active layers;

forming a photoresist layer on one side of the first insulating layer, which faces away from the substrate;

exposing the photoresist layer through a first exposure light, wherein the first exposure light is emitted by an ultraviolet light source and irradiates the photoresist layer through a halftone mask;

developing the exposed photoresist layer to form a photoresist pattern consisting of a plurality of photoresist blocks, wherein the plurality of photoresist blocks comprise a first photoresist block and a second photoresist block; the first photoresist block corresponds to the first active layer, the second photoresist block corresponds to the second active layer, and the thickness of the first photoresist block is smaller than that of the second photoresist block;

transferring the photoresist pattern onto the first insulating layer, specifically, etching the first insulating layer, removing the first insulating layer which is not covered by the photoresist pattern, and forming a first insulating block corresponding to the first active layer and a second insulating block corresponding to the second active layer;

ashing the light resistance pattern, removing the first photoresist block in the light resistance pattern, and enabling the second photoresist block to form a third photoresist block;

etching the plurality of insulating blocks, and thinning the first insulating block to form a first grid insulating layer, wherein the thickness of the first grid insulating layer is smaller than that of the second insulating block;

and removing the third photoresist block to expose the second insulating block to form the second gate insulating layer.

12. The method for manufacturing the TFT array substrate according to claim 11, wherein the patterning the photoresist layer comprises:

the halftone mask comprises a first light-transmitting area, a second light-transmitting area and a third light-transmitting area, wherein the light transmittance of the first light-transmitting area is greater than that of the second light-transmitting area, and the light transmittance of the third light-transmitting area is greater than that of the first light-transmitting area; the first light-transmitting area corresponds to the area where the first photoresist block is located, the second light-transmitting area corresponds to the area where the second photoresist block is located, and a part of the photoresist layer corresponding to the third light-transmitting area is removed.

13. The method of fabricating a TFT array substrate according to any one of claims 9 to 12,

the process of making the substrate includes:

forming a buffer layer on a substrate;

and forming a barrier layer on one side of the buffer layer opposite to the substrate.

14. The method of manufacturing a TFT array substrate according to claim 13, further comprising:

forming a first grid electrode corresponding to the first grid electrode insulating layer and a second grid electrode corresponding to the second grid electrode insulating layer on one side, opposite to the substrate, of the plurality of grid electrode insulating layers, wherein the distance between the first grid electrode and the first active layer is smaller than that between the second grid electrode and the second active layer;

forming a dielectric layer on the substrate, wherein the dielectric layer covers the active layers, the gate insulating layers and the gates, and the dielectric layer is provided with a first through hole and a second through hole corresponding to each active layer;

and forming a source electrode and a drain electrode on one side of the dielectric layer, which faces away from the substrate, wherein the source electrode is electrically connected with the active layer through the first through hole, and the drain electrode is electrically connected with the active layer through the second through hole.

15. The method of manufacturing a TFT array substrate as claimed in claim 14, further comprising:

and forming a passivation film on the side of the dielectric layer opposite to the substrate, wherein the passivation film covers the source electrode, the drain electrode and the dielectric layer.

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