CN115083943A - Semiconductor processing system - Google Patents
Semiconductor processing system Download PDFInfo
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- CN115083943A CN115083943A CN202110267663.XA CN202110267663A CN115083943A CN 115083943 A CN115083943 A CN 115083943A CN 202110267663 A CN202110267663 A CN 202110267663A CN 115083943 A CN115083943 A CN 115083943A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a semiconductor processing system, which relates to the technical field of semiconductor processing and is used for enabling a wafer before processing and a wafer after processing to be in different spaces and removing residual gas on the surfaces of the wafer before processing and the wafer after processing. The semiconductor processing system includes: the device comprises a controller, a processing chamber, a vacuum transmission chamber, a front-end module, a first buffer chamber and a second buffer chamber, wherein the processing chamber, the vacuum transmission chamber, the front-end module, the first buffer chamber and the second buffer chamber are communicated with the controller. The first buffer chamber and the second buffer chamber are both communicated with the processing chamber. The controller is used for controlling the equipment front-end module to load and unload the wafer and controlling the processing chamber to process the wafer. The controller is also used for controlling the first buffer chamber to clean the wafer before the wafer enters the processing chamber, and controlling the second buffer chamber to clean the wafer after the wafer leaves the processing chamber.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a semiconductor processing system.
Background
Currently, most semiconductor processing equipment, such as etching equipment, physical vapor deposition equipment, chemical vapor deposition equipment, etc., require the transfer of wafers between chambers.
In some processes, such as etching, the etching apparatus may perform plasma etching on the wafer using a reactive gas, such as HBr, that is corrosive to the surface of the wafer. After the etching is finished, the reaction gas remains on the surface of the wafer, and when the etched wafer and the etched wafer before etching are placed in the same space, the etched wafer and the etched wafer are subjected to cross contamination.
Disclosure of Invention
The invention aims to provide a semiconductor processing system which is used for enabling a wafer before processing and a wafer after processing to be in different spaces and removing residual gas on the surfaces of the wafer before processing and the wafer after processing.
The invention provides a semiconductor processing system, comprising: the device comprises a controller, a processing chamber communicated with the controller, a front-end module of the device, a first buffer chamber and a second buffer chamber positioned in the front-end module of the device. The first buffer chamber and the second buffer chamber are both communicated with the processing chamber. The controller is used for controlling the equipment front-end module to load and unload the wafer and controlling the processing chamber to process the wafer. The controller is also used for controlling the first buffer chamber to clean the wafer before the wafer enters the processing chamber, and controlling the second buffer chamber to clean the wafer after the wafer leaves the processing chamber.
Compared with the prior art, the semiconductor processing system provided by the invention comprises: the device comprises a controller, a processing chamber communicated with the controller, an equipment front-end module, a first buffer chamber and a second buffer chamber, wherein the first buffer chamber and the second buffer chamber are positioned in the equipment front-end module and are communicated with the processing chamber. The equipment front end module is used for loading and unloading wafers, and the first buffer chamber and the second buffer chamber are used for cleaning the wafers.
In the process of processing the wafer by using the semiconductor processing system, after the wafer is loaded by the front-end module of the equipment, the wafer enters the first buffer chamber before the wafer enters the processing chamber to be processed. The first buffer chamber cleans the wafer, so that the surface of the wafer entering the processing chamber is free from residual gas, and the wafer is ensured not to be polluted in the processing chamber. After the wafer is processed in the processing chamber, the second buffer chamber cleans the processed wafer again to remove residual gas on the surface of the processed wafer, so that the wafer entering the next process flow is in a clean state.
According to the using process, the semiconductor processing system can clean both the wafers before processing and the wafers after processing, and can separate the wafers before processing and the wafers after processing in space, so that the problem of cross contamination between the wafers before processing and the wafers after processing can be effectively solved. Meanwhile, the first buffer chamber and the second buffer chamber are arranged in the front end module of the equipment, so that the auxiliary equipment is simplified, and the initial equipment cost and the later maintenance cost are reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic block diagram of a semiconductor processing system according to an embodiment of the present invention;
fig. 2 is a schematic structural view of a first buffer chamber according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
During semiconductor processing, for example: and (5) semiconductor etching process. A certain amount of process gas remains on the surface of the wafer after processing in the processing chamber. These process gases, if left on the wafer surface for a long period of time, will inevitably cause defects in the wafer.
In the prior art, in order to remove the residual process gas on the surface of the wafer, ashing, photoresist removal or wet cleaning processes are adopted to perform secondary treatment on the etched wafer. However, the wafers before and after etching are all in the same space, which causes cross contamination of the wafers before and after etching.
In view of the above technical problems, embodiments of the present invention provide a semiconductor processing system. Fig. 1 illustrates a schematic structural diagram of a semiconductor processing system according to an embodiment of the present invention. Referring to fig. 1, the semiconductor processing system includes: the system comprises a controller, a processing chamber 1 communicated with the controller, an equipment front end module 2, a first buffer chamber 3 and a second buffer chamber 4 which are positioned in the equipment front end module 2. The first buffer chamber 3 and the second buffer chamber 4 are both in communication with the process chamber 1.
The controller is used for controlling the equipment front end module 2 to load and unload the wafer and controlling the processing chamber 1 to process the wafer. The controller is also used for controlling the first buffer chamber 3 to clean the wafer before the wafer enters the processing chamber 1, and controlling the second buffer chamber 4 to clean the wafer after the wafer leaves the processing chamber 1.
Compared with the prior art, in the process of processing the wafer by using the semiconductor processing system, after the front-end module 2 of the equipment is used for loading the wafer, the wafer enters the first buffer chamber 3 before the wafer enters the processing chamber 1 to be processed. The first buffer chamber 3 cleans the wafer so that the surface of the wafer entering the processing chamber 1 is free from residual gas, thereby ensuring that the wafer is not polluted in the processing chamber 1. After the wafer is processed in the processing chamber 1, the second buffer chamber 4 cleans the processed wafer to remove residual gas on the surface of the processed wafer, so that the wafer entering the next process flow is in a clean state.
According to the using process, the semiconductor processing system can clean both the wafers before and after the process treatment, and can separate the wafers before and after the process treatment in space, so that the problem of cross contamination of the wafers before and after the process treatment can be effectively solved. Meanwhile, the first buffer chamber 3 and the second buffer chamber 4 are arranged in the front end module 2 of the equipment, so that the auxiliary equipment is simplified, and the initial equipment cost and the later maintenance cost are reduced.
In practical applications, after the unprocessed foups are loaded into the loading port 7, the controller is used to control the front end module 2 to load unprocessed wafers. After the processed wafer is cleaned in the second buffer chamber 4, the controller is configured to control the front end module 2 to perform blanking on the processed wafer.
In one example, referring to fig. 1, the semiconductor processing system described above may further include a vacuum transfer chamber 5 and a load lock chamber 6. The vacuum transfer chamber 5 is connected to the first buffer chamber 3 and the second buffer chamber 4 through the load lock chamber 6. The vacuum transfer chamber 5 is used for transferring the wafer between the first buffer chamber 3 and the process chamber 1 or between the second buffer chamber 4 and the process chamber 1 under vacuum conditions. A load lock chamber 6 for equalizing the gas pressure between the vacuum transfer chamber 5 and the first buffer chamber 3, or the vacuum transfer chamber 5 and the second buffer chamber 4.
In practical applications, referring to fig. 1, the semiconductor processing system may include a first load lock chamber having a first load lock module and a second load lock chamber having a second load lock module. The first load lock chamber is connected to the first buffer chamber 3 and the second load lock chamber is connected to the second buffer chamber 4.
The first load lock module converts the gas pressure in the first load lock chamber from atmospheric pressure to vacuum pressure when the wafer is transferred from the first buffer chamber 3 to the first load lock chamber. The second load lock module converts the gas pressure in the second load lock chamber from vacuum pressure to atmospheric pressure when the wafer is transferred from the vacuum transfer chamber 5 to the second load lock chamber.
Referring to fig. 1, the controller may be a controller in a broad sense for controlling the operation states of the first buffer chamber 3, the second buffer chamber 4, the front end module 2, and the process chamber 1.
Referring to fig. 1, the process chamber 1 may include a plurality of chambers. For example: the process chamber 1 may include four. The process chamber 1 may be an etching process chamber 1, but is not limited thereto.
Referring to fig. 1, the front end module 2 of the apparatus can load and unload a plurality of wafers at a time, so as to improve the working efficiency. The first buffer chamber 3 and the second buffer chamber 4 are arranged in the front end module 2 of the equipment, which not only simplifies the accessory equipment, but also reduces the transportation cost of the wafer.
Fig. 2 illustrates a schematic structural diagram of the first buffer chamber 3 provided in the embodiment of the present invention. The first buffer chamber 3 and the second buffer chamber 4 have the same structure, and the first buffer chamber 3 will be described as an example.
Referring to fig. 2, the first buffer chambers 3 may each have a gas purging device 31 therein. The gas purging device 31 is provided with a cleaning station for carrying the wafer, and the gas purging device 31 is used for performing gas purging on the wafer on the cleaning station.
In a specific use process, the semiconductor processing system further comprises a gas generating device, and the gas inlet end of the gas purging device 31 can be communicated with the gas generating device. A gas generating device may be used to provide gas to the gas purging device 31, and the gas may be nitrogen or inert gas, etc. which does not react when contacting the wafer.
In one example, referring to fig. 2, the gas purging device 31 may include a plurality of gas diffusers 311 communicatively connected to the controller, the gas diffusers 311 being configured to diffuse gas entering the first buffer chamber 3 and the second buffer chamber 4 from the gas generating apparatus. The gas diffuser 311 may be disposed at an inlet end of the gas purging device 31, and when the gas generating apparatus supplies gas to the gas purging device 31, the gas diffuser 311 may be used to diffuse the gas generated by the gas generating apparatus into the first buffer chamber 3 and the second buffer chamber 4.
In one example, referring to fig. 2, the gas purging device 31 may further include an automatic flow regulator 312 communicatively coupled to the controller. One end of the automatic flow regulator 312 communicates with the gas generating apparatus, and the other end of the automatic flow regulator 312 communicates with the gas diffuser 311. The automatic flow regulator 312 may be used to regulate the flow of gas within the gas purge device 31. The adjustment range of the gas flow can be controlled between 0.1LPM and 15 LPM.
For example: when the process with the linear dimension below 15nm is performed, the wafer is transferred to the second buffer chamber 4 by the vacuum transfer chamber 5 after the etching process. In this case, the gas flow rate of the gas purge device 31 needs to be reduced in order to prevent the pattern on the wafer from being tilted due to an excessive gas flow rate.
In one example, referring to fig. 2, the gas purge device 31 may further include a throttle valve communicatively connected to the controller, and the throttle valve may be located at the gas outlet end of the gas purge device 31. The throttle valve may be used to regulate the gas pressure within the gas purging device 31.
Referring to fig. 2, in order to accurately adjust the gas pressure inside the gas purging device 31, the gas outlet end of the gas purging device 31 may be installed with a pressure gauge in communication with the controller, so that the gas pressure inside the gas purging device 31 can be obtained in real time. When the pressure gauge obtains the gas pressure in the gas purging device 31, the gas pressure is sent to the controller, and the controller compares the gas pressure in the gas purging device 31 with a preset gas pressure. When the gas pressure in the gas purging device 31 is not consistent with the preset gas pressure, the controller controls the throttle valve to adjust the gas pressure in the gas purging device 31.
In one example, referring to FIG. 2, the gas purge device 31 further includes a heater and temperature sensor in communication with the controller. A heater may be located at the inlet end of the gas purging device 31 to raise the temperature of the gas entering the gas purging device 31 to facilitate more rapid removal of residual gas from the surface of the wafer. The temperature sensor is positioned in the gas purging device 31, so that the gas temperature in the gas purging device 31 can be detected in real time conveniently, and the gas temperature is transmitted to the controller, so that the controller can adjust the heating temperature of the heater timely.
Referring to fig. 2, the heating assembly may include: the heating element and a voltage regulator connected in series with a power supply circuit of the heating element may be communicatively connected to the controller. The controller is configured to control the voltage regulator to adjust the voltage applied to the heating element during heating of the heating element.
In practical use, the Joule's law Q ═ I 2 Rt and ohm's law U ═ IR, it is found that, when resistance value R is constant, current value I increases as voltage value U increases. In this case, the heat generated by the same resistor is increased at the same time.
The heating member may be a thermoelectric element. The thermoelectric element may be made of materials such as bismuth telluride and alloys thereof, lead telluride and alloys thereof, or silicon germanium alloys, but is not limited thereto.
The heating member may be a heating belt type heating member or a winding type heating member, but is not limited thereto, and the embodiment of the present invention is not particularly limited thereto. The heating belt type heating element mainly comprises an electric heating material, an insulating material and the like, wherein the electric heating material is a nichrome belt, the electric heating material has the characteristics of quick heating, high thermal efficiency, long service life and the like, and the insulating material is a multilayer alkali-free glass fiber and has good temperature resistance and reliable insulating property. The hot-wire heating element is formed by winding a metal radiating fin on the surface of a heating pipe, and plays a role in accelerating heat dissipation by increasing the heat dissipation area.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A semiconductor processing system, comprising: the device comprises a controller, a processing chamber communicated with the controller, a front-end equipment module, a first buffer chamber and a second buffer chamber, wherein the first buffer chamber and the second buffer chamber are positioned in the front-end equipment module; the first buffer chamber and the second buffer chamber are both communicated with the processing chamber;
the controller is used for controlling the equipment front-end module to carry out loading and unloading on the wafer and controlling the processing chamber to process the wafer;
the controller is also used for controlling the first buffer chamber to clean the wafer before the wafer enters the processing chamber, and controlling the second buffer chamber to clean the wafer after the wafer leaves the processing chamber.
2. The semiconductor processing system of claim 1, further comprising a vacuum transfer chamber and a load lock chamber; the vacuum transmission chamber is connected with the first buffer chamber and the second buffer chamber through the load lock chamber;
the vacuum transmission chamber is used for transmitting the wafer between the first buffer chamber and the processing chamber or between the second buffer chamber and the processing chamber under the vacuum condition;
the load lock chamber is used for balancing the gas pressure between the vacuum transmission chamber and the first buffer chamber or between the vacuum transmission chamber and the second buffer chamber.
3. The semiconductor processing system of claim 2, wherein a gas purge device is provided in each of the first and second buffer chambers, a cleaning station for carrying the wafers is provided in each of the first and second buffer chambers, and the gas purge device is used for gas purging the wafers on the cleaning station; and/or the presence of a gas in the gas,
the gas adopted by the gas purging device is nitrogen or inert gas.
4. The semiconductor processing system of claim 3, further comprising a gas generation apparatus, the gas inlet of the gas purging device being in communication with the gas generation apparatus.
5. The semiconductor processing system of claim 4, wherein the gas purging device comprises a plurality of gas diffusers communicatively coupled to the controller, the plurality of gas diffusers configured to diffuse gas entering the first and second buffer chambers from the gas generating apparatus.
6. The semiconductor processing system of claim 5, wherein the gas purging device further comprises an automatic flow regulator in communication with the controller, one end of the automatic flow regulator being in communication with the gas generating apparatus and the other end of the automatic flow regulator being in communication with the gas diffuser.
7. The semiconductor processing system of claim 6, wherein the gas flow adjustment range of the automatic flow regulator is between 0.1LPM and 15 LPM.
8. The semiconductor processing system of any of claims 3 to 6, wherein the gas purge device further comprises a throttle valve in communication with the controller, the throttle valve being located at an outlet end of the gas purge device.
9. The semiconductor processing system of claim 3, wherein the gas purge apparatus further comprises a heating assembly and a temperature sensor communicatively connected to the controller, the heating assembly being located at an inlet end of the gas purge apparatus for heating the gas blown out by the gas purge apparatus;
the temperature sensor is positioned in the gas purging device and used for acquiring the gas temperature in the gas purging device.
10. The semiconductor processing system of claim 9, wherein the heating assembly comprises: the heating element and the voltage regulator are connected in series on a power supply loop of the heating element, and the voltage regulator is connected with the controller in a communication mode;
the controller is used for controlling the voltage applied to the heating element by the voltage regulator according to a preset temperature and the gas temperature in the gas purging device acquired by the temperature sensor in the heating process of the heating element; and/or the presence of a gas in the gas,
the heating temperature range of the heating component is 20-150 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110267663.XA CN115083943A (en) | 2021-03-11 | 2021-03-11 | Semiconductor processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110267663.XA CN115083943A (en) | 2021-03-11 | 2021-03-11 | Semiconductor processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115083943A true CN115083943A (en) | 2022-09-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110267663.XA Pending CN115083943A (en) | 2021-03-11 | 2021-03-11 | Semiconductor processing system |
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| CN (1) | CN115083943A (en) |
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2021
- 2021-03-11 CN CN202110267663.XA patent/CN115083943A/en active Pending
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