CN115083908A - Preparation method of BTO structure - Google Patents

Preparation method of BTO structure Download PDF

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Publication number
CN115083908A
CN115083908A CN202210833295.5A CN202210833295A CN115083908A CN 115083908 A CN115083908 A CN 115083908A CN 202210833295 A CN202210833295 A CN 202210833295A CN 115083908 A CN115083908 A CN 115083908A
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layer
oxide layer
silicon oxide
conductive type
groove
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郭亮良
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention provides a preparation method of a BTO structure, which comprises the steps of forming a groove in a first conduction type epitaxial layer, forming a silicon oxide layer in the groove by adopting a CVD method, then forming a silicon nitride layer, removing part of the silicon oxide layer and the silicon nitride layer by an etching method, and then forming a gate oxide layer and a gate polycrystalline silicon layer in the groove; the invention can form a bottom silicon oxide layer with easy control of uniformity and better consistency at the bottom of the groove, and has simple preparation process, low cost and good reproducibility.

Description

Preparation method of BTO structure
Technical Field
The invention relates to the field of semiconductor preparation, in particular to a preparation method of a BTO structure.
Background
A Bottom Thick Oxide (BTO) structure is a common method to reduce the Cgd capacitance of a power insulated gate field effect transistor. The conventional BTO preparation method basically deposits an oxide layer in a High Density Plasma (HDP) manner, and then etches the oxide layer to a required thickness by using chemical mechanical polishing and wet etching methods to form a BTO structure. Since the high density plasma also causes etching of the silicon in the epitaxial layer, this approach can cause fluctuations in the thickness of the oxide layer at the bottom of the trench, which in turn affects the uniformity of the gate structure.
Therefore, it is necessary to provide a method for preparing a novel BTO structure.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a method for preparing a BTO structure, which solves the problem of the prior art that the HDP oxide layer has a fluctuating thickness.
To achieve the above and other related objects, the present invention provides a method for preparing a BTO structure, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type epitaxial layer;
forming a mask layer on the first conductive type epitaxial layer, and patterning the mask layer to define a groove region;
etching the first conductive type epitaxial layer to form a groove;
forming a silicon oxide layer by adopting a CVD method, wherein the silicon oxide layer covers the bottom and the side wall of the groove;
forming a silicon nitride layer covering the silicon oxide layer;
carrying out planarization treatment, and removing the silicon nitride layer and the silicon oxide layer on the surface of the first conductive type epitaxial layer to expose the first conductive type epitaxial layer;
removing the silicon oxide layer on the side wall of the groove by adopting an etching method, and reserving the silicon oxide layer at the bottom of the groove to form a bottom silicon oxide layer;
removing the silicon nitride layer in the groove by adopting an etching method;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove, and the thickness of the bottom silicon oxide layer is larger than that of the gate oxide layer;
forming a gate polysilicon layer, wherein the gate polysilicon layer fills the groove;
and carrying out planarization treatment, and removing the gate polycrystalline silicon layer on the surface of the first conduction type epitaxial layer.
Optionally, the ratio D of the thickness of the bottom silicon oxide layer to the opening width of the trench is formed in a range of 0 < D < 0.5.
Optionally, the thickness of the bottom silicon oxide layer is formed to be 0.01 to 2 micrometers.
Optionally, the topography of the bottom silicon oxide layer formed comprises a U-shape or an arch shape.
Optionally, the method for removing the silicon oxide layer on the sidewall of the trench includes dry etching or wet etching, and the method for removing the silicon nitride layer in the trench includes dry etching or wet etching.
Optionally, the planarization treatment includes one or a combination of a chemical mechanical polishing method and a physical polishing method.
Optionally, the first conductivity type is N-type or the first conductivity type is P-type.
Optionally, the semiconductor base includes a first conductive type substrate located at the bottom and the first conductive type epitaxial layer located on the first conductive type substrate, and a material of the first conductive type substrate includes one of doped silicon, doped silicon germanium and doped silicon carbide.
Optionally, the method further includes a step of forming a first conductivity type buffer layer between the first conductivity type epitaxial layer and the first conductivity type substrate.
Optionally, the mask layer includes one or a combination of a photoresist layer, a silicon oxide layer, and a silicon nitride layer.
As described above, the present invention provides a method for preparing a BTO structure, comprising forming a trench in a first conductivity type epitaxial layer, forming a silicon oxide layer in the trench by a CVD method, then forming a silicon nitride layer, removing a portion of the silicon oxide layer and the silicon nitride layer by an etching method, and then forming a gate oxide layer and a gate polysilicon layer in the trench; the invention can form a bottom silicon oxide layer with easy control of uniformity and better consistency at the bottom of the groove, and has simple preparation process, low cost and good reproducibility.
Drawings
FIG. 1 is a flow chart of a process for fabricating a BTO structure according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a structure after forming a trench in the embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a silicon oxide layer formed in the practice of the present invention.
Fig. 4 is a schematic structural diagram of a silicon nitride layer formed in accordance with an embodiment of the present invention.
FIG. 5 is a schematic view of a structure after planarization in the practice of the present invention.
FIG. 6 is a schematic structural diagram illustrating a bottom silicon oxide layer formed in accordance with an embodiment of the present invention.
FIG. 7 is a schematic view of a structure after removing a silicon nitride layer according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram after a gate oxide layer is formed in the practice of the present invention.
Fig. 9 is a schematic structural diagram of a gate polysilicon layer formed in the embodiment of the invention.
FIG. 10 is a schematic diagram of a BTO structure formed after planarization in accordance with an embodiment of the present invention.
Description of the element reference numerals
100 substrate of a first conductivity type
200 epitaxial layer of first conductivity type
300 groove
400 silicon oxide layer
401 bottom silicon oxide layer
500 silicon nitride layer
600 gate oxide
700 gate polysilicon layer
Thickness of T
Width W
S1-S11
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, in the present embodiment, a trench is formed in a first conductive type epitaxial layer, a silicon oxide layer is formed in the trench by using a CVD method, a silicon nitride layer is then formed, and a gate oxide layer and a gate polysilicon layer are formed in the trench after removing a portion of the silicon oxide layer and the silicon nitride layer by using an etching method; the embodiment can form the bottom silicon oxide layer with easily controlled uniformity and better consistency at the bottom of the groove, and has the advantages of simple preparation process, low cost and good reproducibility.
The preparation of the BTO structure and its structure are described below with reference to fig. 2 to 10.
First, referring to fig. 2, step S1 is executed: a semiconductor substrate is provided which comprises a first conductivity type epitaxial layer 200.
Specifically, the semiconductor base may include a first conductive type substrate 100 located at the bottom and the first conductive type epitaxial layer 200 located on the first conductive type substrate 100, and a material of the first conductive type substrate 100 may include one of doped silicon, doped silicon germanium and doped silicon carbide, which may be selected according to requirements.
In this embodiment, the first conductive type substrate 100 is an N-type substrate 100, and the first conductive type epitaxial layer 200 is a material having the same conductive type as the substrate, that is, the first conductive type epitaxial layer 200 is an N-type epitaxial layer 200, but the present invention is not limited thereto, and the first conductive type substrate 100 and the first conductive type epitaxial layer 200 may also be a P-type substrate as required, which is not limited herein.
Further, a step of forming a first conductive type buffer layer (not shown) between the first conductive type epitaxial layer 200 and the first conductive type substrate 100 may be further included to prevent dopant ions of the first conductive type substrate 100 from diffusing into the first conductive type epitaxial layer 200 during a high temperature process through the first conductive type buffer layer, so as to avoid an increase in the doping concentration of the first conductive type epitaxial layer 200.
Next, step S2 is executed: a mask layer (not shown) is formed on the first conductive type epitaxial layer 200 and patterned to define a trench region.
In this embodiment, a photoresist layer is directly coated on the surface of the first conductive type epitaxial layer 200, and the photoresist layer is exposed and developed according to the distribution and size of the trench 300 to be formed subsequently, so as to form an opening in the photoresist layer, thereby defining a trench region.
Next, step S3 is executed: the first conductive type epitaxial layer 200 is etched to form a trench 300. The etching method of the trench 300, the distribution and size of the trench 300 are not limited herein.
Next, referring to fig. 3, step S4 is executed: a silicon oxide layer 400 is formed by CVD, and the silicon oxide layer 400 covers the bottom and sidewalls of the trench 300.
Specifically, since the silicon oxide layer 400 is formed by the CVD method, when the silicon oxide layer 400 is formed, damage to the first conductive type epitaxial layer 200 can be avoided, and the silicon oxide layer 400 with easily controlled uniformity and excellent uniformity can be formed.
Next, referring to fig. 4, step S5 is executed: a silicon nitride layer 500 is formed, the silicon nitride layer 500 covering the silicon oxide layer 400. The method of forming the silicon nitride layer 500 may include a CVD method.
Next, referring to fig. 5, step S6 is executed: performing a planarization process to remove the silicon nitride layer 500 and the silicon oxide layer 400 on the surface of the first conductive type epitaxial layer 200, so as to expose the first conductive type epitaxial layer 200.
The planarization process may be one or a combination of Chemical Mechanical Polishing (CMP) and physical polishing, and in this embodiment, a CMP process with a better planarization effect is used, but not limited thereto. After the planarization process, the silicon oxide layer 400 in the trench 300 is exposed, thereby facilitating a subsequent etching process.
Next, referring to fig. 6, step S7 is executed: and removing the silicon oxide layer 400 on the side wall of the trench 300 by using an etching method, and remaining the silicon oxide layer 400 at the bottom of the trench 300 to form a bottom silicon oxide layer 401.
The etching method may adopt dry etching or wet etching, and a portion of the silicon oxide layer 400 located at the bottom of the trench 300 may be retained by controlling an etching process to form the bottom silicon oxide layer 401.
As shown in fig. 10, when the opening width of the trench 300 is denoted by W and the thickness of the bottom silicon oxide layer 401 is denoted by T, the ratio D of the thickness T of the bottom silicon oxide layer 401 to the opening width W of the trench 300 may range from 0 < D < 0.5, such as 0.15, 0.2, 0.25, 0.3, 0.4, etc.
The thickness T of the bottom silicon oxide layer 401 may be 0.01 microns to 2 microns, such as 0.01 microns, 0.05 microns, 0.1 microns, 0.15 microns, 0.5 microns, 1 micron, 1.5 microns, 2 microns, and the like, and may be selected according to the requirement, which is not limited herein.
The profile of the bottom silicon oxide layer 401 may include a U-shape or a dome shape, which may be selected according to the requirement, and is not limited herein.
Next, referring to fig. 7, step S8 is executed: and removing the silicon nitride layer 500 in the trench 300 by using an etching method. The removing method may be wet etching with hot phosphoric acid, or dry etching, and is not limited herein.
Next, referring to fig. 8, step S9 is executed: forming a gate oxide layer 600, wherein the gate oxide layer 600 covers the exposed side wall of the trench 300, and the thickness of the bottom silicon oxide layer 401 is greater than that of the gate oxide layer 600.
Specifically, in this embodiment, the gate oxide layer 600 made of silicon oxide is formed by a thermal oxidation method to serve as an insulating dielectric layer of a gate electrode, and the thickness of the gate oxide layer 600 is not limited herein.
Next, referring to fig. 9, step S10 is executed: forming a gate polysilicon layer 700, wherein the gate polysilicon layer 700 fills the trench 300 to serve as a conductive layer of a gate, and a method of forming the gate polysilicon layer 700 may include a CVD method.
Next, referring to fig. 10, step S11 is executed: performing planarization treatment to remove the gate polysilicon layer 700 on the surface of the first conductive type epitaxial layer 200.
In the present embodiment, a CMP process with a better planarization effect is used, but not limited thereto, and after the planarization treatment, a surface with higher flatness can be formed, thereby facilitating the subsequent process.
In summary, in the BTO structure manufacturing method of the present invention, a trench is formed in the first conductive type epitaxial layer, a CVD method is used to form a silicon oxide layer in the trench, and then a silicon nitride layer is formed, and after a portion of the silicon oxide layer and the silicon nitride layer are removed by an etching method, a gate oxide layer and a gate polysilicon layer are formed in the trench; the invention can form a bottom silicon oxide layer with easy control of uniformity and better consistency at the bottom of the groove, and has simple preparation process, low cost and good reproducibility.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A preparation method of a BTO structure is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type epitaxial layer;
forming a mask layer on the first conductive type epitaxial layer, and patterning the mask layer to define a groove region;
etching the first conductive type epitaxial layer to form a groove;
forming a silicon oxide layer by adopting a CVD method, wherein the silicon oxide layer covers the bottom and the side wall of the groove;
forming a silicon nitride layer covering the silicon oxide layer;
carrying out planarization treatment, and removing the silicon nitride layer and the silicon oxide layer on the surface of the first conductive type epitaxial layer to expose the first conductive type epitaxial layer;
removing the silicon oxide layer on the side wall of the groove by adopting an etching method, and reserving the silicon oxide layer at the bottom of the groove to form a bottom silicon oxide layer;
removing the silicon nitride layer in the groove by adopting an etching method;
forming a gate oxide layer, wherein the gate oxide layer covers the exposed side wall of the groove, and the thickness of the bottom silicon oxide layer is larger than that of the gate oxide layer;
forming a gate polysilicon layer, wherein the gate polysilicon layer fills the groove;
and carrying out planarization treatment to remove the gate polysilicon layer on the surface of the first conductive type epitaxial layer.
2. A method of producing a BTO structure according to claim 1, characterized in that: the ratio D of the thickness of the formed bottom silicon oxide layer to the opening width of the groove is in a range of 0 & lt D & lt 0.5.
3. A method of producing a BTO structure according to claim 1, characterized in that: the thickness of the formed bottom silicon oxide layer is 0.01-2 microns.
4. A method of producing a BTO structure according to claim 1, characterized in that: the shape of the formed bottom silicon oxide layer comprises a U shape or an arch shape.
5. A method of producing a BTO structure according to claim 1, characterized in that: the method for removing the silicon oxide layer on the side wall of the groove comprises dry etching or wet etching, and the method for removing the silicon nitride layer in the groove comprises dry etching or wet etching.
6. A method of making a BTO structure according to claim 1, characterized in that: the planarization treatment comprises one or a combination of a chemical mechanical polishing method and a physical polishing method.
7. A method of producing a BTO structure according to claim 1, characterized in that: the first conductivity type is N-type or the first conductivity type is P-type.
8. A method of making a BTO structure according to claim 1, characterized in that: the semiconductor substrate comprises a first conductive type substrate positioned at the bottom and a first conductive type epitaxial layer positioned on the first conductive type substrate, and the first conductive type substrate is made of one of doped silicon, doped germanium silicon and doped silicon carbide.
9. A method of producing a BTO structure according to claim 8, characterized in that: the method further comprises a step of forming a first conductive type buffer layer between the first conductive type epitaxial layer and the first conductive type substrate.
10. A method of producing a BTO structure according to claim 1, characterized in that: the mask layer comprises one or a combination of a photoresist layer, a silicon oxide layer and a silicon nitride layer.
CN202210833295.5A 2022-07-14 2022-07-14 Preparation method of BTO structure Pending CN115083908A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280497A (en) * 2014-07-10 2016-01-27 北大方正集团有限公司 Method of manufacturing groove-type VDMOS and the groove-type VDMOS
CN107017167A (en) * 2017-03-01 2017-08-04 上海华虹宏力半导体制造有限公司 The manufacture method of trench-gate device with shield grid
CN114038751A (en) * 2021-09-30 2022-02-11 上海道之科技有限公司 Manufacturing method of shielded gate MOSFET device with upper and lower structures
CN114242577A (en) * 2021-12-13 2022-03-25 上海华虹宏力半导体制造有限公司 Manufacturing method of trench gate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280497A (en) * 2014-07-10 2016-01-27 北大方正集团有限公司 Method of manufacturing groove-type VDMOS and the groove-type VDMOS
CN107017167A (en) * 2017-03-01 2017-08-04 上海华虹宏力半导体制造有限公司 The manufacture method of trench-gate device with shield grid
CN114038751A (en) * 2021-09-30 2022-02-11 上海道之科技有限公司 Manufacturing method of shielded gate MOSFET device with upper and lower structures
CN114242577A (en) * 2021-12-13 2022-03-25 上海华虹宏力半导体制造有限公司 Manufacturing method of trench gate

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Application publication date: 20220920