CN115080480A - Remote IIC bus communication method, device and system - Google Patents
Remote IIC bus communication method, device and system Download PDFInfo
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Abstract
The application discloses a remote IIC bus communication method, device and system. Wherein, this system includes: the IIC host interface circuit is used for converting an SDA signal required by IIC bus communication into a differential signal; the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting differential signals; the IIC slave interface circuit is electrically connected with the RS485 communication bus and used for restoring the differential signal into an SDA signal and generating an SCL signal required by IIC bus communication, the IIC slave interface circuit is formed by combining the RS485 communication bus and a clock, a microprocessor and protocol conversion are not required to be additionally arranged to realize remote communication, the problem of high communication cost in the related technology can be solved, and the product material cost and the development cost can be reduced.
Description
Technical Field
The application relates to the field of communication, in particular to a remote IIC bus communication method, device and system.
Background
At present, part of high-precision humidity sensors use an IIC bus to read temperature and humidity information, and for some application occasions, the sensors need to be placed at a longer distance for detection.
In view of the problem of high communication cost in the related art, no effective solution has been proposed at present.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned technical deficiencies, and to provide a method, an apparatus and a system for remote IIC bus communication, so as to at least solve the problem of high communication cost in the related art.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
according to an aspect of an embodiment of the present application, there is provided an IIC bus communication system for a long distance, including: the IIC host interface circuit is used for converting an SDA signal required by IIC bus communication into a differential signal; one end of the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting the differential signal received from the IIC host interface circuit; and the IIC slave interface circuit is electrically connected with the other end of the RS485 communication bus and is used for restoring the differential signal received from the RS485 communication bus into the SDA signal and generating an SCL signal required by IIC bus communication.
Optionally, the system further comprises: and the controller is electrically connected with the IIC host interface circuit and is used for simulating and generating the SDA signal.
Optionally, the IIC host interface circuit includes: the first RS485 communication chip is electrically connected with the controller and is used for converting the SDA signal into the differential signal; and the first auxiliary circuit is respectively and electrically connected with the first RS485 communication chip and one end of the RS485 communication bus and is used for transmitting the differential signal to the RS485 communication bus.
Optionally, the first auxiliary circuit comprises: the circuit comprises a first resistor, a second resistor and a control circuit, wherein one end of the first resistor is electrically connected with a first power supply; one end of the second resistor is electrically connected with the other end of the first resistor, and the other end of the second resistor is electrically connected with the first RS485 communication chip; one end of the third resistor is electrically connected with the controller, and the other end of the third resistor is electrically connected with a pin which is arranged on the first RS485 communication chip and used for receiving the SDA signal; one end of the fourth resistor is grounded, and the other end of the fourth resistor is electrically connected with a setting pin of the first RS485 communication chip and an output pin of a setting signal on the controller respectively; one end of the first capacitor is grounded, and the other end of the first capacitor is electrically connected with a second power supply and a power supply pin of the first RS485 communication chip respectively; one end of the second capacitor is grounded with one end of the first capacitor, and the other end of the second capacitor is electrically connected with the other end of the first capacitor; one end of the third capacitor is grounded, and the other end of the third capacitor is electrically connected with a first differential signal output pin of the first RS485 communication chip; one end of the fifth resistor is grounded, and the other end of the fifth resistor is electrically connected with the first differential signal output pin; one end of the sixth resistor is electrically connected with the first differential signal output pin, and the other end of the sixth resistor is electrically connected with the RS485 communication bus; a first transient suppression diode, one end of the first transient suppression diode being electrically connected to the other end of the sixth resistor, the other end of the first transient suppression diode being grounded; one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is electrically connected with a second differential signal output pin of the first RS485 communication chip; one end of the seventh resistor is connected with the second power supply, and the other end of the seventh resistor is electrically connected with the second differential signal output pin; one end of the eighth resistor is electrically connected with the second differential signal output pin, and the other end of the eighth resistor is electrically connected with the RS485 communication bus; and one end of the second transient suppression diode is electrically connected with the other end of the eighth resistor, and the other end of the second transient suppression diode is grounded.
Optionally, the system further comprises: the IIC sensor is electrically connected with the IIC slave interface circuit and used for replying data when receiving a starting signal composed of the SDA signal and the SCL signal from the IIC slave interface circuit.
Optionally, the IIC slave interface circuit includes: the second RS485 communication chip is electrically connected with the RS485 communication bus and used for reducing the differential signal into the SDA signal; and the second auxiliary circuit is respectively and electrically connected with the second RS485 communication chip and the other end of the RS485 communication bus and is used for transmitting the SDA signal to the IIC sensor.
Optionally, the second auxiliary circuit comprises: one end of the ninth resistor is electrically connected with the RS485 communication bus, and the other end of the ninth resistor is electrically connected with a first differential signal input pin of the second RS485 communication chip; a third transient suppression diode, one end of the third transient suppression diode being electrically connected to one end of the ninth resistor, and the other end of the third transient suppression diode being grounded; one end of the tenth resistor is electrically connected with the RS485 communication bus, and the other end of the tenth resistor is electrically connected with a second differential signal input pin of the second RS485 communication chip; one end of the fourth transient suppression diode is electrically connected with one end of the tenth resistor, and the other end of the fourth transient suppression diode is grounded; one end of the fifth capacitor is grounded, and the other end of the fifth capacitor is electrically connected with the first differential signal input pin; one end of the eleventh resistor is grounded, and the other end of the eleventh resistor is electrically connected with the first differential signal input pin; one end of the sixth capacitor is grounded, and the other end of the sixth capacitor is electrically connected with the second differential signal input pin; one end of the twelfth resistor is electrically connected with the second power supply, and the other end of the twelfth resistor is electrically connected with the second differential signal input pin; one end of the seventh capacitor is grounded, and the other end of the seventh capacitor is electrically connected with the second power supply and the power supply pin of the second RS485 communication chip respectively; one end of the eighth capacitor is grounded with one end of the seventh capacitor, and the other end of the eighth capacitor is electrically connected with the other end of the seventh capacitor; one end of the thirteenth resistor is electrically connected with the second RS485 communication chip; a fourteenth resistor, one end of which is electrically connected to the other end of the thirteenth resistor; a fifteenth resistor, one end of which is electrically connected with the other end of the thirteenth resistor; one end of the diode is electrically connected with the other end of the thirteenth resistor, and the other end of the diode is electrically connected with the IIC sensor and outputs the SDA signal; one end of the sixteenth resistor is electrically connected with the second RS485 communication chip; a seventeenth resistor, one end of which is electrically connected to the other end of the diode; and a first end of the triode is electrically connected with the other end of the fifteenth resistor, a second end of the triode is electrically connected with the other end of the seventeenth resistor, and a third end of the triode is electrically connected with the other end of the sixteenth resistor and grounded.
Optionally, the IIC slave interface circuit further includes: and the clock oscillation circuit is respectively and electrically connected with the IIC sensor and the second auxiliary circuit and is used for generating an SCL signal required by the IIC bus communication.
Optionally, the clock oscillator circuit includes: the clock generation chip is used for generating an SCL signal required by IIC bus communication with the aid of the peripheral circuit.
Optionally, the RS485 communication bus is an RS485 communication bus with a power supply.
According to another aspect of the embodiments of the present application, the present invention further provides an electronic device, including: a processor and a memory; the memory has stored thereon a computer readable program executable by the processor; the processor, when executing the computer readable program, implements the steps in the method described above.
According to another aspect of embodiments of the present application, the present invention also provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps in the above-described method.
In the embodiment of the present application, a system including: the IIC host interface circuit is used for converting an SDA signal required by IIC bus communication into a differential signal; the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting the differential signal; the IIC slave interface circuit is electrically connected with the RS485 communication bus and used for restoring the differential signal into the SDA signal and generating an SCL signal required by IIC bus communication, and the IIC slave interface circuit is formed by combining the RS485 communication bus and a clock without additionally adding a microprocessor and protocol conversion to realize remote communication, so that the problem of high communication cost in the related technology can be solved, and the product material cost and the development cost can be reduced.
Drawings
FIG. 1 is a schematic diagram of an alternative long-range IIC bus communication system according to embodiments of the present application;
FIG. 2 is a schematic diagram of an alternative IIC host interface circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative IIC slave interface circuit according to an embodiment of the present application;
FIG. 4 is a flow chart of an alternative remote IIC bus communication method according to embodiments of the present application;
FIG. 5 is a schematic diagram of an alternative remote IIC bus communication device according to embodiments of the present application; and the number of the first and second groups,
fig. 6 is a block diagram of a terminal according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an aspect of an embodiment of the present application, an embodiment of an IIC bus communication system over a long distance is provided. Fig. 1 is a schematic diagram of an alternative long-range IIC bus communication system according to an embodiment of the present application, which, as shown in fig. 1, may include:
the IIC host interface circuit 101 is used for converting SDA signals required by IIC bus communication into differential signals;
one end of the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting the differential signal received from the IIC host interface circuit;
the IIC slave interface circuit 103 is electrically connected with the other end of the RS485 communication bus and used for restoring the differential signal received from the RS485 communication bus into an SDA signal and generating an SCL signal required by IIC bus communication.
Through the scheme, the system comprises the following parts: the IIC host interface circuit is used for converting an SDA signal required by IIC bus communication into a differential signal; the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting differential signals; the IIC slave interface circuit is electrically connected with the RS485 communication bus and used for restoring the differential signal into an SDA signal and generating an SCL signal required by IIC bus communication, the IIC slave interface circuit is formed by combining the RS485 communication bus and a clock, a microprocessor and protocol conversion are not required to be additionally arranged to realize remote communication, the problem of high communication cost in the related technology can be solved, and the product material cost and the development cost can be reduced.
As an alternative example, the following further details the technical solution of the present application in a specific implementation manner with reference to fig. 2 and fig. 3.
Optionally, the system further comprises: and the controller is electrically connected with the IIC host interface circuit and is used for simulating and generating the SDA signal.
Optionally, the IIC host interface circuit comprises: the first RS485 communication chip (such as MAX487EEPA) is electrically connected with the controller and used for converting the SDA signal into a differential signal; and the first auxiliary circuit is respectively and electrically connected with the first RS485 communication chip and one end of the RS485 communication bus and is used for transmitting the differential signal to the RS485 communication bus.
Optionally, the first auxiliary circuit comprises: a first resistor R209, one end of which is electrically connected with a first power supply (3.3V power supply); one end of the second resistor R257 is electrically connected with the other end of the first resistor, and the other end of the second resistor R257 is electrically connected with the first RS485 communication chip; one end of the third resistor is electrically connected with the controller, and the other end of the third resistor is electrically connected with a pin for receiving the SDA signal on the first RS485 communication chip; one end of the fourth resistor R211 is grounded, and the other end of the fourth resistor R211 is electrically connected with a setting pin of the first RS485 communication chip and an output pin of a setting signal on the controller respectively; one end of the first capacitor is grounded, and the other end of the first capacitor is electrically connected with a second power supply (5V power supply) and a power supply pin of the first RS485 communication chip respectively; one end of the second capacitor is grounded with one end of the first capacitor, and the other end of the second capacitor is electrically connected with the other end of the first capacitor; one end of the third capacitor is grounded, and the other end of the third capacitor is electrically connected with a first differential signal output pin of the first RS485 communication chip; one end of the fifth resistor R258 is grounded, and the other end of the fifth resistor R is electrically connected with the first differential signal output pin; one end of the sixth resistor R213 is electrically connected with the first differential signal output pin, and the other end of the sixth resistor R is electrically connected with the RS485 communication bus; the first transient suppression diode TVS12, one end of the first transient suppression diode is electrically connected with the other end of the sixth resistor, and the other end of the first transient suppression diode is grounded; one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is electrically connected with a second differential signal output pin of the first RS485 communication chip; one end of the seventh resistor R259 is connected with the second power supply, and the other end of the seventh resistor R259 is electrically connected with the second differential signal output pin; one end of the eighth resistor is electrically connected with the second differential signal output pin, and the other end of the eighth resistor is electrically connected with the RS485 communication bus; and one end of the second transient suppression diode TVS9 is electrically connected with the other end of the eighth resistor, and the other end of the second transient suppression diode is grounded.
Optionally, the system further comprises: and the IIC sensor is electrically connected with the IIC slave interface circuit and used for replying data when receiving a starting signal consisting of an SDA signal and an SCL signal from the IIC slave interface circuit.
Optionally, the IIC slave interface circuit includes: the second RS485 communication chip is electrically connected with the RS485 communication bus and used for reducing the differential signal into an SDA signal; and the second auxiliary circuit is respectively and electrically connected with the second RS485 communication chip and the other end of the RS485 communication bus and is used for transmitting the SDA signal to the IIC sensor.
Optionally, the second auxiliary circuit comprises: one end of the ninth resistor is electrically connected with the RS485 communication bus, and the other end of the ninth resistor is electrically connected with a first differential signal input pin of the second RS485 communication chip; a third transient suppression diode current TVS6, one end of the third transient suppression diode current being electrically connected to one end of the ninth resistor, the other end of the third transient suppression diode current being grounded; one end of the tenth resistor R126 is electrically connected with the RS485 communication bus, and the other end of the tenth resistor R is electrically connected with a second differential signal input pin of the second RS485 communication chip; a fourth transient suppression diode TVS7, one end of the fourth transient suppression diode being electrically connected to one end of the tenth resistor, the other end of the fourth transient suppression diode being grounded; one end of the fifth capacitor is grounded, and the other end of the fifth capacitor is electrically connected with the first differential signal input pin; one end of the eleventh resistor is grounded, and the other end of the eleventh resistor is electrically connected with the first differential signal input pin; one end of the sixth capacitor is grounded, and the other end of the sixth capacitor is electrically connected with the second differential signal input pin; one end of the twelfth resistor is electrically connected with the second power supply, and the other end of the twelfth resistor is electrically connected with the second differential signal input pin; one end of the seventh capacitor is grounded, and the other end of the seventh capacitor is electrically connected with a second power supply (5V power supply) and a power supply pin of the second RS485 communication chip respectively; an eighth capacitor C71, one end of the eighth capacitor being connected to one end of the seventh capacitor, the other end of the eighth capacitor being electrically connected to the other end of the seventh capacitor; one end of the thirteenth resistor R152 is electrically connected with the second RS485 communication chip; a fourteenth resistor R109, one end of which is electrically connected to the other end of the thirteenth resistor; a fifteenth resistor R116, one end of which is electrically connected to the other end of the thirteenth resistor; one end of the diode D22 is electrically connected with the other end of the thirteenth resistor, and the other end of the diode is electrically connected with the IIC sensor and outputs an SDA signal; one end of the sixteenth resistor R191 is electrically connected with the second RS485 communication chip; a seventeenth resistor R122, one end of which is electrically connected to the other end of the diode; and a first end of the triode Q3 is electrically connected with the other end of the fifteenth resistor, a second end of the triode Q3 is electrically connected with the other end of the seventeenth resistor, and a third end of the triode Q3 is electrically connected with the other end of the sixteenth resistor and grounded.
Optionally, the IIC slave interface circuit further comprises: and the clock oscillation circuit is electrically connected with the IIC sensor and the second auxiliary circuit respectively and is used for generating an SCL signal required by IIC bus communication.
Optionally, the clock oscillator circuit includes: the peripheral circuit is connected with the clock generation chip NE555 and the peripheral circuit, and the clock generation chip is used for generating SCL signals required by IIC bus communication under the assistance of the peripheral circuit.
Optionally, the RS485 communication bus is an RS485 communication bus with a power supply.
The clock that this application combines 485 communication and 555 oscillating circuit to form can realize long-range IIC device and read the operation, has solved the IIC device and need increase microprocessor in addition and protocol conversion just can realize long-range communication's problem. As an alternative example, the technical solution of the present application is further described below with reference to specific embodiments. The present application mainly consists of the following parts (corresponding to fig. 2):
MCU: the singlechip microprocessor kernel is used as a control host of the IIC, and simulates and outputs an SDA1 signal, and the signal can be generated through an IO port capable of being input and output without a special IIC interface.
When the interface circuit of the IIC host computer outputs the SDA1 signal, the signal is converted into a differential signal through the interface circuit and is transmitted to the 485 communication bus.
The 485 communication bus with the power supply is used for transmitting communication signals, and the 485 communication bus with the power supply +12VDC and GND are used for supplying power for the IIC sensor and the IIC slave interface circuit.
And the IIC slave interface circuit is used for restoring the differential SDA1 signal into a single-ended signal SDA through the interface circuit, and the SDA is connected to the data pin of the IIC sensor. Meanwhile, the interface circuit is also connected with a square wave generating circuit consisting of NE555, and the generated square wave is a clock signal with known frequency, is used for simulating an SCL signal and is connected to a clock pin of the IIC sensor.
And the IIC sensor collects temperature and humidity signals, responds to host roll calling and replies host data.
The control process is as follows:
1) when the SDA1 needs to be output, the MCU sets the RS485_ DE pin (high level), and controls the output of the SDA1 according to a preset clock frequency f, wherein the corresponding clock period is t-1/f.
Specifically, after t _ rst time, SDA1 sends a low level, after t _ rst time, it sends a high level (this process is mainly to achieve that the slave NE555 is charged out of a reset state), after t _ rst + t/2 (NE555 outputs a high level at this time, and the SCL signal of the corresponding slave is a high level), SDA1 sends a low level (start bit) first, triggers IIC to send a start signal, and sets a timer, and when the timer starts to count t/4, SDA1 outputs bit0 of transmission data, when the timer counts t/2, it is considered that the SCL of the slave IIC is simulated as low level to high level, SDA1 is kept unchanged, when the timer counts t, it is considered that the SCL of the slave IIC is simulated as high level to low level, SDA1 data is kept unchanged, when t + t/4, SDA1 outputs bit1 of transmission data, when the cycle is sent to 8t, the master has finished sending data, at the moment, the response of the slave computer needs to be detected, the MCU controls the RS485_ DE pin to be reset (low level), and the 485 communication chip of the host computer IIC circuit enters a receiving state, so that the 485 bus is in an idle state. In the IIC interface circuit of the slave, when the IIC device receives the first eight bits, the SDA is in an input state (the SDA is in a high level when the 485 bus is idle due to a pull-up resistor), and when the R0 inputs a low level, the 485DE pin is in a low level. When the RO input is high, SDA is high, Q3 is on, and pin 485DE is low. Therefore, the 485 is in a receiving state during data receiving, the IIC device sends a response in the 9 th clock cycle after correctly receiving the host roll name, an SDA low level signal is output, at the moment, Q3 is not conducted, the RO is high level because the bus is idle, 485DE is high level, 485 is in a sending state, DI is pulled down to the ground, 485 bus is low level, when SDA outputs high level, Q3 is conducted, 485DE is low level, 485 is in a receiving state, and bus is high level. The SDA of the IIC device can normally return to the bus.
2) The clock oscillator circuit formed by the NE555 is used for generating a square wave signal with the frequency f and outputting the square wave signal SCL to the sensor chip, when the resistance values of the R260 and the R261 are equal, a square wave with the duty ratio of 50% is generated, and the frequency f can be adjusted by adjusting the resistance values of the R260 and the R261 and the capacitance value of the C190. When the 485 bus is in an idle state, the R0 outputs a high level, the Q4 is turned on, at this time, the RS terminal voltage of the NE555 is at a low level, so that the NE555 is always in a reset state, when the R0 outputs a low level (at this time, the host sends an SDA signal start bit), the RS terminal voltage of the NE555 is at a low level, the Q4 is not turned on, the RS terminal gradually rises along with the charging of the C189, after t _ rst time, the RS terminal is identified as a high level, the NE555 is out of the reset state, the NE555 outputs a low level to the SCL first, and after timing 1/2f, the high level is output, so that a clock signal with the frequency f can be simulated, and the SDA signal transmission of the host is matched, so that the IIC device can be read.
3) t _ rst is the charging time of C192, which can be calculated from the values of R210 and C192, and can be compensated for by actual measurement. In addition, R119 and C192 form a discharge circuit, the discharge time is t _ dis, which can be calculated by the values of R210 and C192, and in this embodiment, t _ dis > is 200t, which ensures that the IIC communication has more than 200 clock cycles for the IIC communication. When R0 of 485 is in idle state, Q4 is no longer conductive, after discharge time t _ dis, the voltage at RS end drops to low level, and NE555 resumes reset state.
4) The period t of the clock signal generated by the NE555 is jointly determined by R260, R261 and C190, a SCL signal t value can be obtained through theoretical calculation and actual measurement and stored in the host, when the IIC sensor responds, the transmitted SDA signal carries t information of the clock signal, if a low level of a bit in response data is detected, the duration of the low level is equal to t, if the possible element difference and aging of the R260, R261 and C190 are considered, the duration of the low level can be detected in the host IIC interface circuit and used for correcting the SCL signal t value of the host.
Through long-distance transmission data signal SDA of 485 communication differential signal, set up the clock signal SCL that the circuit formed at IIC chip local through 555 oscillating circuit to under the circumstances that IIC chip end does not increase microprocessor, also can produce the wave form that satisfies the IIC agreement, realize long-distance IIC device and read the operation.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
According to another aspect of the embodiment of the application, a long-distance IIC bus communication method is further provided. As shown in fig. 4, the method may include:
step S1, converting the SDA signal required by the IIC bus communication into a differential signal by using the IIC host interface circuit;
step S2, transmitting the differential signal received from the IIC host interface circuit by using an RS485 communication bus;
step S3, the IIC slave interface circuit is used to restore the differential signal received from the RS485 communication bus to the SDA signal and generate an SCL signal required for the IIC bus communication, for example, a clock oscillator circuit in the IIC slave interface circuit is used to generate an SCL signal required for the IIC bus communication.
According to another aspect of the embodiment of the application, an apparatus for implementing the method is also provided. As shown in fig. 5, the apparatus may include:
a conversion unit 51, configured to convert an SDA signal required for IIC bus communication into a differential signal by using an IIC host interface circuit;
the transmission unit 53 is configured to transmit the differential signal received from the IIC host interface circuit by using an RS485 communication bus;
and the initialization unit 55 is configured to restore the differential signal received from the RS485 communication bus to the SDA signal by using an IIC slave interface circuit, and generate an SCL signal required for IIC bus communication.
It should be noted that the modules described above are the same as examples and application scenarios realized by corresponding steps, but are not limited to what is disclosed in the foregoing embodiments. It should be noted that the modules as a part of the apparatus may run in a corresponding hardware environment, and may be implemented by software, or may be implemented by hardware, where the hardware environment includes a network environment.
According to another aspect of the embodiment of the present application, there is also provided a server or a terminal for implementing the above method.
Fig. 6 is a block diagram of a terminal according to an embodiment of the present application, and as shown in fig. 6, the terminal may include: one or more processors 601 (only one shown), memory 603, and transmission means 605. as shown in fig. 6, the terminal may also include input-output device 607.
The memory 603 may be used to store software programs and modules, such as program instructions/modules corresponding to the methods and apparatuses in the embodiments of the present application, and the processor 601 executes the software programs and modules stored in the memory 603 to execute various functional applications and data processing, so as to implement the above-described methods. The memory 603 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 603 may further include memory located remotely from the processor 601, which may be connected to the terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The above-mentioned transmission device 605 is used for receiving or sending data via a network, and may also be used for data transmission between a processor and a memory. Examples of the network may include a wired network and a wireless network. In one example, the transmission device 605 includes a Network adapter (NIC) that can be connected to a router via a Network cable and other Network devices to communicate with the internet or a local area Network. In one example, the transmission device 605 is a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.
Among them, the memory 603 is used to store an application program, in particular.
The processor 601 may call the application stored in the memory 603 through the transmission device 605 to perform the following steps:
converting SDA signals required by IIC bus communication into differential signals by using an IIC host interface circuit;
transmitting the differential signal received from the IIC host interface circuit by using an RS485 communication bus;
and restoring the differential signal received from the RS485 communication bus into the SDA signal by using an IIC slave interface circuit, and generating an SCL signal required by IIC bus communication.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment is not described herein again.
It can be understood by those skilled in the art that the structure shown in fig. 6 is only an illustration, and the terminal may be a terminal device such as a smart phone (e.g., an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, and a Mobile Internet Device (MID), a PAD, etc. Fig. 6 is a diagram illustrating the structure of the electronic device. For example, the terminal may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in FIG. 6, or have a different configuration than shown in FIG. 6.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
Embodiments of the present application also provide a storage medium. Alternatively, in the present embodiment, the storage medium may be used for program codes for executing the method.
Optionally, in this embodiment, the storage medium may be located on at least one of a plurality of network devices in a network shown in the above embodiment.
Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps:
converting SDA signals required by IIC bus communication into differential signals by using an IIC host interface circuit;
transmitting the differential signal received from the IIC host interface circuit by using an RS485 communication bus;
and restoring the differential signal received from the RS485 communication bus into the SDA signal by using an IIC slave interface circuit, and generating an SCL signal required by IIC bus communication.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment is not described herein again.
Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and various media capable of storing program codes.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The integrated unit in the above embodiments, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in the above computer-readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing one or more computer devices (which may be personal computers, servers, network devices, or the like) to execute all or part of the steps of the methods described in the embodiments of the present application.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (15)
1. A remote IIC bus communication system, comprising:
the IIC host interface circuit is used for converting an SDA signal required by IIC bus communication into a differential signal;
one end of the RS485 communication bus is electrically connected with the IIC host interface circuit and is used for transmitting the differential signal received from the IIC host interface circuit;
and the IIC slave interface circuit is electrically connected with the other end of the RS485 communication bus and is used for restoring the differential signal received from the RS485 communication bus into the SDA signal and generating an SCL signal required by IIC bus communication.
2. The system of claim 1, further comprising:
and the controller is electrically connected with the IIC host interface circuit and is used for simulating and generating the SDA signal.
3. The system of claim 2, wherein the IIC host interface circuit comprises:
the first RS485 communication chip is electrically connected with the controller and is used for converting the SDA signal into the differential signal;
and the first auxiliary circuit is respectively electrically connected with the first RS485 communication chip and one end of the RS485 communication bus and used for transmitting the differential signal to the RS485 communication bus.
4. The system of claim 3, wherein the first auxiliary circuit comprises:
the circuit comprises a first resistor, a second resistor and a control circuit, wherein one end of the first resistor is electrically connected with a first power supply;
one end of the second resistor is electrically connected with the other end of the first resistor, and the other end of the second resistor is electrically connected with the first RS485 communication chip;
one end of the third resistor is electrically connected with the controller, and the other end of the third resistor is electrically connected with a pin which is arranged on the first RS485 communication chip and used for receiving the SDA signal;
one end of the fourth resistor is grounded, and the other end of the fourth resistor is electrically connected with a setting pin of the first RS485 communication chip and an output pin of a setting signal on the controller respectively;
one end of the first capacitor is grounded, and the other end of the first capacitor is electrically connected with a second power supply and a power supply pin of the first RS485 communication chip respectively;
one end of the second capacitor is grounded with one end of the first capacitor, and the other end of the second capacitor is electrically connected with the other end of the first capacitor;
one end of the third capacitor is grounded, and the other end of the third capacitor is electrically connected with a first differential signal output pin of the first RS485 communication chip;
one end of the fifth resistor is grounded, and the other end of the fifth resistor is electrically connected with the first differential signal output pin;
one end of the sixth resistor is electrically connected with the first differential signal output pin, and the other end of the sixth resistor is electrically connected with the RS485 communication bus;
a first transient suppression diode, one end of the first transient suppression diode being electrically connected to the other end of the sixth resistor, the other end of the first transient suppression diode being grounded;
one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is electrically connected with a second differential signal output pin of the first RS485 communication chip;
one end of the seventh resistor is connected with the second power supply, and the other end of the seventh resistor is electrically connected with the second differential signal output pin;
one end of the eighth resistor is electrically connected with the second differential signal output pin, and the other end of the eighth resistor is electrically connected with the RS485 communication bus;
and one end of the second transient suppression diode is electrically connected with the other end of the eighth resistor, and the other end of the second transient suppression diode is grounded.
5. The system of claim 1, further comprising:
the IIC sensor is electrically connected with the IIC slave interface circuit and used for replying data when receiving a starting signal composed of the SDA signal and the SCL signal from the IIC slave interface circuit.
6. The system of claim 5, wherein the IIC slave interface circuit comprises:
the second RS485 communication chip is electrically connected with the RS485 communication bus and used for reducing the differential signal into the SDA signal;
and the second auxiliary circuit is respectively and electrically connected with the second RS485 communication chip and the other end of the RS485 communication bus and is used for transmitting the SDA signal to the IIC sensor.
7. The system of claim 6, wherein the second auxiliary circuit comprises:
one end of the ninth resistor is electrically connected with the RS485 communication bus, and the other end of the ninth resistor is electrically connected with a first differential signal input pin of the second RS485 communication chip;
a third transient suppression diode, one end of the third transient suppression diode being electrically connected to one end of the ninth resistor, and the other end of the third transient suppression diode being grounded;
one end of the tenth resistor is electrically connected with the RS485 communication bus, and the other end of the tenth resistor is electrically connected with a second differential signal input pin of the second RS485 communication chip;
one end of the fourth transient suppression diode is electrically connected with one end of the tenth resistor, and the other end of the fourth transient suppression diode is grounded;
one end of the fifth capacitor is grounded, and the other end of the fifth capacitor is electrically connected with the first differential signal input pin;
one end of the eleventh resistor is grounded, and the other end of the eleventh resistor is electrically connected with the first differential signal input pin;
one end of the sixth capacitor is grounded, and the other end of the sixth capacitor is electrically connected with the second differential signal input pin;
one end of the twelfth resistor is electrically connected with a second power supply, and the other end of the twelfth resistor is electrically connected with the second differential signal input pin;
one end of the seventh capacitor is grounded, and the other end of the seventh capacitor is electrically connected with the second power supply and the power supply pin of the second RS485 communication chip respectively;
one end of the eighth capacitor is grounded with one end of the seventh capacitor, and the other end of the eighth capacitor is electrically connected with the other end of the seventh capacitor;
one end of the thirteenth resistor is electrically connected with the second RS485 communication chip;
a fourteenth resistor, one end of which is electrically connected to the other end of the thirteenth resistor;
a fifteenth resistor, one end of which is electrically connected with the other end of the thirteenth resistor;
one end of the diode is electrically connected with the other end of the thirteenth resistor, and the other end of the diode is electrically connected with the IIC sensor and outputs the SDA signal;
one end of the sixteenth resistor is electrically connected with the second RS485 communication chip;
a seventeenth resistor, one end of which is electrically connected to the other end of the diode;
and a first end of the triode is electrically connected with the other end of the fifteenth resistor, a second end of the triode is electrically connected with the other end of the seventeenth resistor, and a third end of the triode is electrically connected with the other end of the sixteenth resistor and grounded.
8. The system of claim 6, wherein the IIC slave interface circuit further comprises:
and the clock oscillation circuit is respectively and electrically connected with the IIC sensor and the second auxiliary circuit and is used for generating an SCL signal required by the IIC bus communication.
9. The system of claim 8, wherein the clock oscillator circuit comprises:
the clock generation chip is used for generating an SCL signal required by IIC bus communication with the aid of the peripheral circuit.
10. The system of any one of claims 1-9, wherein the RS485 communication bus is an RS485 communication bus with a power supply.
11. A method for remote IIC bus communication, comprising:
converting SDA signals required by IIC bus communication into differential signals by using an IIC host interface circuit;
transmitting the differential signal received from the IIC host interface circuit by using an RS485 communication bus;
and restoring the differential signal received from the RS485 communication bus into the SDA signal by using an IIC slave interface circuit, and generating an SCL signal required by IIC bus communication.
12. The system of claim 10, wherein generating the SCL signal required for the IIC bus communication comprises:
and generating an SCL signal required by the IIC bus communication by using a clock oscillating circuit in the IIC slave interface circuit.
13. A remote IIC bus communication device, comprising:
the conversion unit is used for converting an SDA signal required by IIC bus communication into a differential signal by using an IIC host interface circuit;
the transmission unit is used for transmitting the differential signal received from the IIC host interface circuit by utilizing an RS485 communication bus;
and the initialization unit is used for restoring the differential signal received from the RS485 communication bus into the SDA signal by using an IIC slave interface circuit and generating an SCL signal required by IIC bus communication.
14. An electronic device, comprising: a processor and a memory;
the memory has stored thereon a computer readable program executable by the processor;
the processor, when executing the computer readable program, implements the steps in the method of any of claims 11-12.
15. A computer-readable storage medium, storing one or more programs, the one or more programs being executable by one or more processors to perform the steps of the method of any one of claims 11-12.
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| CN202210805993.4A CN115080480B (en) | 2022-07-08 | 2022-07-08 | Remote IIC bus communication method, device and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210805993.4A CN115080480B (en) | 2022-07-08 | 2022-07-08 | Remote IIC bus communication method, device and system |
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| US20180373662A1 (en) * | 2017-06-21 | 2018-12-27 | Linear Technology Holding Llc | I2c device extender for inter-board communication over a single-channel bidirectional link |
| CN209358569U (en) * | 2019-02-18 | 2019-09-06 | 广州市正宏泰科贸有限公司 | Differential signaling bus circuit |
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| US6463496B1 (en) * | 1998-07-27 | 2002-10-08 | Richard Wolf Gmbh | Interface for an I2C bus |
| CN101576868A (en) * | 2009-05-18 | 2009-11-11 | 艾默生网络能源有限公司 | I2C bus communication drive circuit |
| CN205427836U (en) * | 2016-03-01 | 2016-08-03 | 王志红 | Communication interface circuit |
| US20180373662A1 (en) * | 2017-06-21 | 2018-12-27 | Linear Technology Holding Llc | I2c device extender for inter-board communication over a single-channel bidirectional link |
| CN209358569U (en) * | 2019-02-18 | 2019-09-06 | 广州市正宏泰科贸有限公司 | Differential signaling bus circuit |
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| CN115080480B (en) | 2024-04-02 |
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