CN115080206B - High-speed echo data real-time recording system and method based on multithreading mechanism - Google Patents
High-speed echo data real-time recording system and method based on multithreading mechanism Download PDFInfo
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Abstract
The invention discloses a high-speed echo data real-time recording system and a high-speed echo data real-time recording method based on a multithreading mechanism. The invention aims to solve the problem that the existing method can not realize real-time accurate recording of a large amount of high-speed echo data generated by different interfaces. The system comprises: a high-speed data acquisition board card and an upper computer; the board card comprises an FPGA, a DDR and a peripheral interface; the upper computer comprises a PCIe slot, a hard disk and user software; user software arranged in the upper computer uses a multithreading mechanism to divide a plurality of tasks, each processor executes a thread in the multi-core processor, and the tasks can be executed in parallel; the multithreading mechanism comprises a main thread and an auxiliary thread; the main thread is used for displaying, updating and responding to user operation of the user interface; the auxiliary thread is used for collecting, caching and writing into the hard disk. The invention is used in the technical field of electronic measurement.
Description
Technical Field
The invention relates to the technical field of electronic measurement, in particular to a high-speed echo data real-time recording system and a high-speed echo data real-time recording method based on a multithreading mechanism.
Background
Phased array radar consists of a fairly dense array of antennas that changes the beam scanning direction by changing the way the beams emitted by the array of antenna surfaces are synthesized. Under the working mode, a large amount of echo data can be generated, the industrial field is to process a large amount of high-speed data, serial transmission technologies such as 10Gbit Ethernet, fiber Channel and SRIO are advanced and developed, and an interface scheme is provided for data acquisition. Meanwhile, in some practical tasks, in order to monitor the system in real time, real-time requirements are also put forward on the acquisition record of high-speed data. The method accurately records a large amount of high-speed echo data generated by different interfaces in real time, and becomes an important problem to be solved by the radar system.
Disclosure of Invention
The invention aims to solve the problem that the existing method cannot accurately record a large amount of high-speed echo data generated by different interfaces in real time, and provides a high-speed echo data real-time recording system and a high-speed echo data real-time recording method based on a multithreading mechanism.
A high-speed echo data real-time recording system based on a multithreading mechanism, comprising: a high-speed data acquisition board card and an upper computer;
the board card comprises an FPGA, a DDR and a peripheral interface;
the upper PC mainly comprises a PCIe slot, a hard disk and user software;
the FPGA is used for realizing the connection of network ports, optical fibers and PCIe peripheral interfaces and the acquisition and transmission functions of data; the DDR is used for increasing the data transmission bandwidth and is responsible for the first level buffer memory of the FPGA for receiving data;
the PCIe slot arranged in the upper PC is used for connecting a data acquisition board card;
the hard disk arranged in the upper computer PC is used for storing data;
user software arranged in the upper computer PC is used for controlling the data acquisition board card;
user software arranged in the upper computer PC is designed based on a National Instrument LabWindows/CVI platform;
dividing a plurality of tasks in LabWindows/CVI software by using a multithreading mechanism, wherein each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel;
the multithreading mechanism comprises a main thread and an auxiliary thread;
the main thread is used for displaying, updating and responding to user operation of a user interface;
the auxiliary thread worker thread is used for collecting, caching and writing into a hard disk;
the auxiliary threads comprise an auxiliary thread worker thread1, an auxiliary thread worker thread2 and an auxiliary thread worker thread3;
the thread is a thread;
opening up N data buffer areas for received data, wherein the capacity of each data buffer area is 1 frame, and storing the first address of the data buffer area buffer in an array queue;
storing the id of the buffer in the array queue, writing the corresponding id into the queue after 1 buffer is written from the buffer0 by a write assist thread work thread2, taking the id which is already written by the buffer from the queue by a read assist thread work thread3, and then reading data from the corresponding buffer and writing the data into a disk;
the thread1 is used for reading the state_fifo of the board card, and if the state_fifo is empty, the board card waits for updating; if not, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), and transmitting the data to an upper computer PC through a PCI-e bus of a data acquisition board card;
the thread2 is used for enabling i=0, reading a command cmd from a Queue, selecting to read C2H data into a buffer [ data [ cmd ] i ] of the data [ cmd ] according to the value of the command cmd, writing the data [ cmd ] i into a Queue after reading, judging whether the value of i is N-1, and ending if yes; if not, letting i=i+1, continuing to read the command cmd from the Queue, selecting to read the data of C2H into a buffer [ data [ cmd ] i of the data [ cmd ] according to the value of the command cmd, and writing the data [ cmd ] i into the Queue after reading;
the Thread3 is used for taking out the id of the buffer from the queue, then writing the data in the buffer into the hard disk, judging whether the value of i is N-1, if so, ending; if not, letting i=i+1, continuing to take out the id of the buffer from the queue, and then writing the data in the buffer into the hard disk until the value of i is N-1;
n is the number of buffers in the data buffer.
The method for recording the high-speed echo data in real time based on the multithreading mechanism comprises the following specific processes:
step one, receiving high-speed echo data by adopting a data acquisition board card;
step two, the PCI-e bus interface is adopted to transmit the received high-speed echo data to software in the PC of the upper computer;
the software LabWindows in the upper computer PC is designed based on a CVI platform of National Instrument;
a multithreading mechanism is used in the software LabWindows/CVI to divide a plurality of tasks, each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel and simultaneously;
the multithreading is more than or equal to 2 threads;
the multi-core is 8 cores or 16 cores;
the multithreading mechanism comprises a main thread and an auxiliary thread;
and step three, writing the data received by the internal software of the PC into the hard disk.
The invention has the beneficial effects that:
the FPGA-based hardware platform can realize rich peripheral interface functions, can complete high-speed data acquisition tasks under various transmission protocols, and the real-time performance of an acquisition system is enhanced by the parallel processing capability of the FPGA; real-time data recording software is designed on the basis of a multithreading mechanism in LabWindows/CVI, so that the performance of the software can be enhanced by fully utilizing multi-core processors, and each processor independently executes one thread to ensure that a real-time acquisition task is not interrupted by other factors; meanwhile, the data buffer area is designed by matching with the memory, and the data is written into the buffer area and then sequentially read out and stored in the hard disk, so that the situation that the data is lost due to the fact that the thread scheduling is not time-consuming caused by system factors is avoided, and the integrity of the data is ensured. The method solves the problem that the existing method can not realize real-time accurate recording of a large amount of high-speed echo data generated by different interfaces.
Drawings
FIG. 1 is a general block diagram of the hardware of the present invention;
FIG. 2 is a diagram of a multithreaded software architecture in accordance with the present invention;
FIG. 3 is a diagram of a data buffer structure according to the present invention;
FIG. 4a is a main thread flow diagram in the multithreading software of the present invention;
FIG. 4b is a flow chart of a secondary thread in the multithreading software of the present invention.
Detailed Description
The first embodiment is as follows: the high-speed echo data real-time recording system based on a multithreading mechanism of the embodiment comprises: a high-speed data acquisition board card and an upper computer;
the transmission rate of the single-path support of the high-speed transceiver of the FPGA chip on the data acquisition board card is 0.5-13.1 Gbps;
the board card mainly comprises an FPGA, a DDR and a peripheral interface;
the upper PC mainly comprises a PCIe slot, a hard disk and user software;
the FPGA is used for realizing the connection of peripheral interfaces such as network ports, optical fibers, PCIe (peripheral component interconnect express) and the like and the acquisition and transmission functions of data; the DDR is used for increasing the data transmission bandwidth and is responsible for the first level buffer memory of the FPGA for receiving data;
the acquisition system is built based on the FPGA, and the overall hardware block diagram is shown in figure 1.
The PCIe slot arranged in the upper PC is used for connecting a data acquisition board card;
the hard disk arranged in the upper computer PC is used for storing data;
user software arranged in the upper computer PC is used for controlling the data acquisition board card;
user software arranged in the upper computer PC is designed based on a National Instrument LabWindows/CVI platform;
dividing a plurality of tasks in LabWindows/CVI software by using a multithreading mechanism, wherein each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel; three tasks of data acquisition, user data display and data writing in a hard disk can be simultaneously executed;
the multithreading mechanism comprises a main thread and an auxiliary thread;
the main thread is used for displaying, updating and responding to user operation of a user interface;
the auxiliary thread worker thread is used for collecting, caching and writing into a hard disk;
the auxiliary threads comprise an auxiliary thread worker thread1, an auxiliary thread worker thread2 and an auxiliary thread worker thread3;
the thread is a thread;
the FIFO is implemented in the FPGA by hardware, and can be understood as a buffer in which the content can be accessed first and then read when needed by the user.
Opening up N data buffer areas for the received high-speed echo data, wherein the capacity of each data buffer area is 1 frame (4 MB), and storing the first address of the data buffer area buffer in an array queue;
storing the id (0-N-1) of the buffer in the array queue, writing the corresponding id into the queue after 1 buffer is written from the buffer0 by a write assist thread worker thread2, taking the id which is already written by the buffer from the queue by the read assist thread worker thread3, and then reading data from the corresponding buffer and writing the data into a disk;
the thread1 is used for reading the state_fifo of the board card, and if the state_fifo is empty, the board card waits for updating; if not, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), and transmitting the data to an upper computer PC through a PCI-e bus of a data acquisition board card;
the thread2 is used for enabling i=0, reading a command cmd from a Queue, selecting to read data of C2H (board card to host) into a buffer [ data [ cmd ] i of data [ cmd ] according to the value of the command cmd, writing the data [ cmd ] i into a Queue after the reading is finished, judging whether the value of i is N-1, and ending if the value of i is N-1; if not, letting i=i+1, continuing to read the command cmd from the Queue, selecting to read the data of C2H (board card to host) into a buffer [ data [ cmd ] i of the data [ cmd ], and writing the data [ cmd ] i into a Queue after reading;
the Thread3 is used for taking out the id of the buffer from the queue, then writing the data in the buffer into the hard disk, judging whether the value of i is N-1, if so, ending; if not, letting i=i+1, continuing to take out the id of the buffer from the queue, and then writing the data in the buffer into the hard disk until the value of i is N-1;
n is the number (setting) of buffers in the data buffer.
The LabWindows/CVI software program uses a thread pool technology in the high-speed echo data real-time recording software;
the LabWindows/CVI thread safety queue is used for protecting data and helping to safely transfer data between threads.
The second embodiment is as follows: the present embodiment differs from the specific embodiment in that the number of threads is 2 or more.
Other steps and parameters are the same as in the first embodiment.
And a third specific embodiment: this embodiment differs from the first or second embodiments in that the multi-core is 8-core or 16-core.
Other steps and parameters are the same as in the first or second embodiment.
The specific embodiment IV is as follows: the method for recording the high-speed echo data in real time based on the multithreading mechanism comprises the following specific processes:
step one, receiving high-speed echo data by adopting a data acquisition board card;
step two, the PCI-e bus interface is adopted to transmit the received high-speed echo data to software in the PC of the upper computer;
the software LabWindows in the upper computer PC is designed based on a CVI platform of National Instrument;
a multithreading mechanism is used in the software LabWindows/CVI to divide a plurality of tasks, each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel and simultaneously; the three tasks of data acquisition, user data display and data writing in the hard disk can be simultaneously executed;
the multithreading is more than or equal to 2 threads;
the multi-core is 8 cores or 16 cores;
the multithreading mechanism comprises a main thread and an auxiliary thread;
and step three, writing the data received by the internal software of the PC into the hard disk.
Fifth embodiment: the fourth difference between the present embodiment and the specific embodiment is that the specific execution process of the main thread is as follows:
step 1: judging whether the main program user interface is loaded successfully, if so, executing the step 2; if not, executing the step 4;
step 2: creating an auxiliary thread, judging whether the auxiliary thread is successfully created, and if so, executing the step 3; if not, executing the step 4;
step 3: responding to the user operation, judging whether to exit, if not, continuing responding to the user operation; if yes, executing the step 4;
step 4: and releasing the memory.
Other steps and parameters are the same as in the fourth embodiment.
Specific embodiment six: the difference between this embodiment and the fourth or fifth embodiment is that the specific execution process of the auxiliary thread in the step 2 is as follows:
step 21, writing a state_fifo after the data acquisition board completes receiving one frame of data each time, wherein the size of one frame of data is 4MB;
the user software reads whether the state_fifo of the data acquisition board card is empty or not, if so, the user software waits for updating; no, go to step 22;
the FIFO is implemented in the FPGA by hardware, and can be understood as a buffer in which the content can be accessed first and then read when needed by the user.
Step 22, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), transmitting the data to the upper computer PC through the PCI-e bus of the data acquisition board card, and executing step 23;
queue (secure Queue) is a software mechanism for CVI multi-threaded data protection.
The former thread generates data and adds the data into a safety queue; the latter thread displays data and reads the security queue;
step 23, let i=0, read command cmd from Queue (cmd) of step 22, choose to read the data of C2H (board card to host) into buffer [ data [ cmd ] i ] buffer of data [ cmd ] according to the value of command cmd, write data [ cmd ] i into Queue after reading, judge whether buffer [ i ] buffer is full, if yes, go to step 24; if not, repeating the step 23;
step 24, making i=i+1, updating state_fifo of the data acquisition board card, taking out id of the buffer from the queue, writing data in the buffer into the hard disk, judging whether the value of i is N-1, if yes, ending; if not, executing step 24 until the value of i is N-1;
n is the number (setting) of buffers in the data buffer area;
other steps and parameters are the same as those of the fourth or fifth embodiment.
The upper computer software selects the LabWindows/CVI development platform of National Instrument, and the program for data acquisition often comprises a plurality of other tasks such as user interface display, data writing into a disk and the like, and one or more of the tasks has strict time requirements and is easy to be interfered by other tasks. While data collection is a time critical task, it is also likely to be interrupted by the user interface task. Therefore, the multi-threading technology is designed to be used in the LabWindows/CVI software program to divide a plurality of tasks; placing the data acquisition operation in one thread and the user interface processing in another thread; when a user operates an interface, the operating system switches threads and provides time for completing tasks for the data acquisition threads; the situation that when a user operates on an interface, a thread cannot return to a data acquisition task, so that overflow of a data acquisition buffer area is caused is avoided. And software performance may be improved by running a multi-threaded program with a multi-processor computer. One thread may be executed by each processor on the computer, enabling the simultaneous execution of both user data display and data writing tasks to disk.
In a multithreaded program, the program notifies the operating system to create other threads, in addition to the main thread, which are referred to as auxiliary threads. The auxiliary thread in the program is responsible for acquiring data, and the main thread reads the data when it is available and then analyzes the display data. LabWindows/CVI provides two high-level mechanisms for running code in auxiliary processes, thread pools and asynchronous timers, respectively. The thread pool is adapted to perform tasks that are performed several times or within one cycle, while the asynchronous timer is adapted to tasks that are performed periodically. Thread pool techniques are used in the high-speed echo data real-time recording software. In addition, the thread-safe queues provided by the CVI may be used to protect data, helping to transfer data securely between threads. When data needs to be collected by one thread and processed by another thread, the thread safety queue can process all data locks inside.
The thread structure of the software is shown in fig. 2, and the functions of each thread are as follows:
main thread (MainThread): display of UI, update, response of user operation.
Read-1, read the state_fifo of the card, and write the data to the corresponding cmd_fifo, let the card start uploading the data.
And (2) when the front end queue is not empty, reading the data on the board card C2H, and writing the data into the corresponding data queue according to the cmd value.
Thread3, read the data of the front end queue, write to SSD.
The cmtnwfreadtpool function is used in the main function to create a 3-thread pool and the CmtDiscardThreadPool (Poolhandle) function is used to release the thread pool after the entire program is completed. The following code illustrates data collection in the main thread using the auxiliary thread.
int CVICALLBACK ReadDataThreadFunction(void*functionData)；
int main(int argc,char*argv[])
{…
CmtScheduleThreadPoolFunction(DEFAULT_THREAD_POOL_HANDLE,ReadDataThreadFunction,NULL,&functionId)；
…}
int CVICALLBACK ReadDataThreadFunction(void*functionData)
{
while(！quit)
{
Acquire(...)；
}
}
The main Thread calls the CmtSchedulThreadPoolFunction function, and the helper Thread-2 function name readDataThreadFunction of writing data into the buffer zone is imported, and other helper threads are similarly imported. In a Windows system, the priority at which each thread works may be specified. When multiple threads need to run, the thread with the highest priority runs first. When a CmtScheduleThreadFunctionAdv function is used to schedule a function to run in a thread pool, the priority of the thread executing the scheduled function may be specified. The thread pool changes thread priority before running the scheduled function. After the function finishes running, the thread pool restores the thread priority to the original priority. Depending on the system configuration and current state, the thread pool may create new threads to execute, may use existing idle processes, or may wait for an active thread to become idle and then use.
The main thread returns from the CmtScheduleThreadPoolFunction function without waiting for the auxiliary thread function to complete. The readdatathread function in the auxiliary thread is executed concurrently with the call in the main thread. Therefore, when the user performs mouse click drag operation on the user interface in the main thread or performs real-time update display on the data, the auxiliary thread can continuously operate to perform data acquisition, write the data into the buffer area through reading the card state FIFO acquisition instruction, and finally sequentially and circularly read out from the buffer area and store the data into the disk.
Aiming at the radar system which needs to process a large amount of data and feed back the data to the user through an interface, the high-speed echo data recording method based on the multithreading mechanism can fully exert the advantages of multithreading design, enhance the software performance and ensure that data acquisition is not interrupted by other factors. Meanwhile, a data buffer area is designed by matching with a memory, and the mode that data is written into the buffer area and then sequentially read out of the memory is adopted, so that the situation that the data is lost due to the fact that the thread scheduling is not time-consuming caused by system factors is avoided, and the integrity of echo data is ensured.
The present invention is capable of other and further embodiments and its several details are capable of modification and variation in light of the present invention, as will be apparent to those skilled in the art, without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. A high-speed echo data real-time recording system based on a multithreading mechanism is characterized in that: the system comprises: a high-speed data acquisition board card and an upper computer;
the board card comprises an FPGA, a DDR and a peripheral interface;
the upper PC mainly comprises a PCIe slot, a hard disk and user software;
the FPGA is used for realizing the connection of network ports, optical fibers and PCIe peripheral interfaces and the acquisition and transmission functions of data; the DDR is used for increasing the data transmission bandwidth and is responsible for the first level buffer memory of the FPGA for receiving data;
the PCIe slot arranged in the upper PC is used for connecting a data acquisition board card;
the hard disk arranged in the upper computer PC is used for storing data;
user software arranged in the upper computer PC is used for controlling the data acquisition board card;
user software arranged in the upper computer PC is designed based on a LabWindows/CVI platform of a national Instrument;
dividing a plurality of tasks in LabWindows/CVI software by using a multithreading mechanism, wherein each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel;
the multithreading mechanism comprises a main thread and an auxiliary thread;
the main thread is used for displaying, updating and responding to user operation of a user interface;
the auxiliary thread workerthread is used for collecting, caching and writing into a hard disk;
the auxiliary threads comprise an auxiliary thread workerthread1, an auxiliary thread workerthread2 and an auxiliary thread workerthread3;
the thread is a thread;
opening up N data buffer areas for received data, wherein the capacity of each data buffer area is 1 frame, and storing the first address of the data buffer area buffer in an array queue;
storing the id of a buffer in the array queue, writing the corresponding id into the queue after 1 buffer is written by a write assist thread work 2 from the buffer0, taking the id which is already written by the buffer out of the queue by the read assist thread work 3, and then reading data from the corresponding buffer and writing the data into a disk;
the thread1 is used for reading the state_fifo of the board card, and if the state_fifo is empty, the board card waits for updating; if not, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), and transmitting the data to an upper computer PC through a PCI-e bus of a data acquisition board card;
the thread2 is used for enabling i=0, reading a command cmd from a Queue, selecting to read C2H data into a buffer [ data [ cmd ] i ] of the data [ cmd ] according to the value of the command cmd, writing the data [ cmd ] i into a Queue after reading, judging whether the value of i is N-1, and ending if yes; if not, letting i=i+1, continuing to read the command cmd from the Queue, selecting to read the data of C2H into a buffer [ data [ cmd ] i of the data [ cmd ] according to the value of the command cmd, and writing the data [ cmd ] i into the Queue after reading;
the thread3 is used for taking out the id of the buffer from the queue, then writing the data in the buffer into the hard disk, judging whether the value of i is N-1, if so, ending; if not, letting i=i+1, continuing to take out the id of the buffer from the queue, and then writing the data in the buffer into the hard disk until the value of i is N-1;
n is the number of buffers in the data buffer area;
the data of the C2H is the data from the board card to the host.
2. The multithreading-based high-speed echo data real-time recording system according to claim 1, wherein: the multithreading is more than or equal to 2 threads.
3. The multithreading-based high-speed echo data real-time recording system according to claim 2, wherein: the multi-core is 8-core or 16-core.
4. A method for real-time recording of high-speed echo data based on a multithreading mechanism based on the system of claim 1, characterized in that: the method comprises the following specific processes:
step one, receiving high-speed echo data by adopting a data acquisition board card;
step two, the PCI-e bus interface is adopted to transmit the received high-speed echo data to software in the PC of the upper computer;
the software LabWindows in the upper computer PC is designed based on a CVI platform of the national Instrument;
a multithreading mechanism is used in the software LabWindows/CVI to divide a plurality of tasks, each processor executes a thread in a multi-core processor, and the tasks can be executed in parallel and simultaneously;
the multithreading is more than or equal to 2 threads;
the multi-core is 8 cores or 16 cores;
the multithreading mechanism comprises a main thread and an auxiliary thread;
writing data received by internal software of the PC into the hard disk; the specific process is as follows:
opening up N data buffer areas for received data, wherein the capacity of each data buffer area is 1 frame, and storing the first address of the data buffer area buffer in an array queue;
storing the id of a buffer in the array queue, writing the corresponding id into the queue after 1 buffer is written by a write assist thread work 2 from the buffer0, taking the id which is already written by the buffer out of the queue by the read assist thread work 3, and then reading data from the corresponding buffer and writing the data into a disk;
the thread1 is used for reading the state_fifo of the board card, and if the state_fifo is empty, the board card waits for updating; if not, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), and transmitting the data to an upper computer PC through a PCI-e bus of a data acquisition board card;
the thread2 is used for enabling i=0, reading a command cmd from a Queue, selecting to read C2H data into a buffer [ data [ cmd ] i ] of the data [ cmd ] according to the value of the command cmd, writing the data [ cmd ] i into a Queue after reading, judging whether the value of i is N-1, and ending if yes; if not, letting i=i+1, continuing to read the command cmd from the Queue, selecting to read the data of C2H into a buffer [ data [ cmd ] i of the data [ cmd ] according to the value of the command cmd, and writing the data [ cmd ] i into the Queue after reading;
the Thread3 is used for taking out the id of the buffer from the queue, then writing the data in the buffer into the hard disk, judging whether the value of i is N-1, if so, ending; if not, letting i=i+1, continuing to take out the id of the buffer from the queue, and then writing the data in the buffer into the hard disk until the value of i is N-1;
n is the number of buffers in the data buffer area;
the data of the C2H is the data from the board card to the host.
5. The method for real-time recording of high-speed echo data based on a multithreading mechanism according to claim 4, wherein the method comprises the following steps: the specific execution process of the main thread is as follows:
step 1: judging whether the main program user interface is loaded successfully, if so, executing the step 2; if not, executing the step 4;
step 2: creating an auxiliary thread, judging whether the auxiliary thread is successfully created, and if so, executing the step 3; if not, executing the step 4;
step 3: responding to the user operation, judging whether to exit, if not, continuing responding to the user operation; if yes, executing the step 4;
step 4: and releasing the memory.
6. The method for real-time recording of high-speed echo data based on a multithreading mechanism according to claim 5, wherein the method comprises the following steps: the specific execution process of the auxiliary thread in the step 2 is as follows:
step 21, writing a state_fifo after the data acquisition board completes receiving one frame of data each time, wherein the size of one frame of data is 4MB;
the user software reads whether the state_fifo of the data acquisition board card is empty or not, if so, the user software waits for updating; no, go to step 22;
step 22, writing the data state_data into corresponding commands cmd_fifo and Queue (cmd), transmitting the data to the upper computer PC through the PCI-e bus of the data acquisition board card, and executing step 23;
step 23, let i=0, read command cmd from Queue (cmd) of step 22, choose to read the data of C2H into buffer [ data [ cmd ] i ] buffer of data [ cmd ] according to the value of command cmd, write data [ cmd ] i into the Queue after finishing reading, judge whether buffer [ i ] buffer is full, yes, go to step 24; if not, repeating the step 23;
step 24, making i=i+1, updating state_fifo of the data acquisition board card, taking out id of the buffer from the queue, writing data in the buffer into the hard disk, judging whether the value of i is N-1, if yes, ending;
if not, executing step 24 until the value of i is N-1;
n is the number of buffers in the data buffer.
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