CN115079944A

CN115079944A - Method and device for improving performance of solid state disk and electronic equipment

Info

Publication number: CN115079944A
Application number: CN202210645766.XA
Authority: CN
Inventors: 赵健雄
Original assignee: Alibaba China Co Ltd
Current assignee: Alibaba China Co Ltd
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2022-09-20

Abstract

The embodiment of the specification provides a method and a device for improving performance of a solid state disk and electronic equipment. The solid state disk comprises a plurality of flash memory chips, the flash memory chips comprise a plurality of physical storage units, and the method comprises the following steps: packaging received IO data from a requester into a logic storage unit, and caching the logic storage unit into a cache space reserved by the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data; splitting a logic storage unit in the cache space into a plurality of data units, and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit; and responding to the fact that the residual storage capacity of the cache space meets a writing condition, and writing the data units in the cache space into corresponding physical storage units for persistent storage according to the mapping relation between the data units and the physical storage units.

Description

Method and device for improving performance of solid state disk and electronic equipment

Technical Field

The embodiment of the specification relates to the technical field of computers, in particular to a method and a device for improving the performance of a solid state disk and electronic equipment.

Background

A Solid State Disk (SSD), also called Solid State Drive, is a hard Disk made of an array of Solid State electronic memory chips.

Solid state disks can be generally classified into Flash Memory (Flash) -based solid state disks and Dynamic Random Access Memory (DRAM) -based solid state disks according to storage media. The solid state disk based on the flash memory has a simple internal structure, so that the market occupation rate is high.

Solid state drives have many advantages over conventional mechanical drives, the most important of which is the security of the stored data. For example, the solid state disk is shaken during use without fear of damaging stored data; and for example, the data in the solid state disk can not be lost when the power is suddenly cut off in the using process. Based on this, the solid state disk is widely applied to various complex working environments, such as a high availability server; in addition, the storage device is also ideal for individual users.

However, the solid state disk is not completely free of defects, and for example, a solid state disk using a flash memory as a storage medium has a problem of poor read-write performance for small IO data.

Disclosure of Invention

The method and the device for improving the performance of the solid state disk and the electronic device are used for solving the problem that the small IO data read-write performance of the solid state disk is poor.

According to a first aspect of embodiments of the present specification, a method for improving performance of a solid state disk is provided, where the solid state disk includes a plurality of flash memory chips, and the flash memory chips include a plurality of physical storage units, the method including:

packaging received IO data from a requester into a logic storage unit, and caching the logic storage unit into a cache space reserved by the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data;

splitting a logic storage unit in the cache space into a plurality of data units, and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit;

and responding to the fact that the residual storage capacity of the cache space meets a writing condition, and writing the data units in the cache space into corresponding physical storage units for persistent storage according to the mapping relation between the data units and the physical storage units.

Optionally, before splitting the logical storage unit in the cache space into a plurality of data units, the method further includes:

allocating a virtual storage address field for the logic storage unit, and binding a plurality of physical storage address fields for the virtual storage address field; wherein, each physical memory address segment corresponds to different physical memory units;

mapping the split data unit to a plurality of physical storage units includes:

and uniformly mapping the split data units to the physical storage units according to the physical storage units respectively corresponding to the physical storage address fields bound by the logical storage unit.

Optionally, the uniformly mapping the split data units to the plurality of physical storage units includes:

and mapping the split data units to different physical storage addresses in the plurality of physical storage units respectively according to the corresponding sorting sequence of the data units in the logical storage units.

Optionally, the number of the split data units is an integer multiple of the number of the plurality of physical storage units;

the mapping the split data units to different physical storage addresses in the plurality of physical storage units respectively includes:

dividing the split data unit into a plurality of groups corresponding to the number of the plurality of physical storage units;

and sequentially mapping the data units in each group to different physical storage addresses in the plurality of physical storage units.

Optionally, the virtual storage address segment is a logically continuous virtual storage address; the storage capacity of the virtual storage address field is equal to the storage capacity of the logical storage unit;

the physical storage address segment is a physical continuous physical storage address; the sum of the capacities of the plurality of physical memory address segments is equal to the storage capacity of the logical memory unit.

Optionally, the physical storage addresses corresponding to the plurality of physical storage units belong to a page table of the same plane page.

Optionally, the method further includes:

and when a data query request is received, the stored data units are read from the plurality of physical storage units concurrently, and the data units are combined into IO data and then returned to the requester.

Optionally, the software architecture of the solid state disk includes a front-end processing layer and a flash memory chip conversion layer; the front-end processing layer comprises a packaging unit, and the flash memory chip conversion layer comprises a distribution unit;

the packaging unit is used for packaging IO data from a requester into a logic storage unit;

the allocation unit is used for allocating a virtual storage address field for the logic storage unit and binding a plurality of physical storage address fields for the virtual storage address field.

Optionally, the data size of the IO data includes 64KB, 32KB or 16 KB; the storage capacity of the logical storage unit comprises 64 KB; the storage capacity of the data unit comprises 4 KB.

Optionally, the physical storage unit includes a wafer in the flash memory chip; the Flash memory chip comprises a NAND Flash chip; the cache space comprises a Write Buffer Group; the logic storage unit comprises a Buffer Node; the DATA unit includes a DATA TAG.

According to a second aspect of the embodiments of the present specification, there is provided an apparatus for improving performance of a solid state disk, where the solid state disk includes a plurality of flash memory chips, the flash memory chips include a plurality of physical storage units, and the apparatus includes:

the cache module encapsulates the received IO data from the requester into a logic storage unit and caches the logic storage unit to a cache space reserved by the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data;

the mapping module is used for splitting the logic storage unit in the cache space into a plurality of data units and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit;

and the writing module is used for responding to the fact that the residual storage capacity of the cache space meets the writing condition, and writing the data units in the cache space into the corresponding physical storage units for persistent storage according to the mapping relation between the data units and the physical storage units.

Optionally, the mapping module further includes:

the distribution submodule distributes a virtual storage address field for the logic storage unit and binds a plurality of physical storage address fields for the virtual storage address field; wherein, each physical memory address segment corresponds to different physical memory units;

the splitting submodule splits the logic storage unit in the cache space into a plurality of data units;

and the mapping submodule is used for uniformly mapping the split data units to the physical storage units according to the physical storage units corresponding to the physical storage address fields bound by the logic storage unit.

Optionally, the mapping sub-module further maps the split data units to different physical storage addresses in the plurality of physical storage units according to a corresponding sorting order of the data units in the logical storage unit.

the mapping submodule further comprises a plurality of groups which are used for dividing the split data unit into a plurality of groups corresponding to the number of the plurality of physical storage units; and sequentially mapping the data units in each group to different physical storage addresses in the plurality of physical storage units.

the physical storage address segment is a physically continuous physical storage address; the sum of the capacities of the plurality of physical memory address segments is equal to the storage capacity of the logical memory unit.

Optionally, the apparatus further comprises:

and the query module is used for reading the stored data units from the plurality of physical storage units concurrently when receiving the data query request, combining the data units into IO data and returning the IO data to the requester.

According to a sixth aspect of embodiments herein, there is provided an electronic apparatus comprising:

a processor;

a memory for storing processor-executable instructions;

the processor is configured to be the method for improving the performance of the solid state disk.

The embodiment of the present specification provides a scheme for improving performance of a solid state disk, where IO data received from a requester is encapsulated into a logical storage unit, and the logical storage unit is cached in a cache space reserved in the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data; splitting a logic storage unit in the cache space into a plurality of data units, and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit; and responding to the fact that the residual storage capacity of the cache space meets a writing condition, and writing the data units in the cache space into corresponding physical storage units for persistent storage according to the mapping relation between the data units and the physical storage units. Therefore, IO data are split into the physical storage units, and the physical storage units are utilized to execute read-write operation in parallel, so that the number of serial read-write operation can be reduced, the delay of the read-write operation is effectively reduced, and the read-write performance of the solid state disk is improved.

For example, if there are 16 IO data and the IO data are allocated to 1 physical storage unit according to the existing manner, the processing needs to be performed 16 times according to the existing serial execution, and according to the scheme provided in this specification, the 16 IO data may be split into 4 physical storage units, each physical storage unit is responsible for processing 4 IO data, and the IO data may be processed through 4 concurrent processes. Compared with the prior art which needs 16 times of processing under serial execution, the read-write performance of the system is improved by 4 times.

Drawings

Fig. 1 is a schematic diagram of a solid state disk provided in an embodiment of the present specification;

FIG. 2 is a diagram illustrating serially performing read and write operations according to an embodiment of the present disclosure;

fig. 3 is a flowchart of a method for improving performance of a solid state disk according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating parallel execution of read and write operations, according to an embodiment of the present disclosure;

fig. 5 is a hardware structure diagram of an apparatus for improving performance of a solid state disk according to an embodiment of the present disclosure;

fig. 6 is a block diagram of an apparatus for improving performance of a solid state disk according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.

The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Referring to the schematic diagram of the solid state disk shown in fig. 1, as shown in fig. 1, from a physical aspect, the solid state disk may include a plurality of Flash memory chips (Flash), and each Flash memory chip may further encapsulate a plurality of physical memory units (DIE, also called wafers). The data in the solid state disk is stored in physical storage units on the flash memory chip.

The solid state disk may further include a control chip and a cache chip in addition to a flash memory chip for storing data.

The control chip is used for controlling the read-write operation of the solid state disk, and corresponding software programs are written in the control chip. From the software level, the software architecture of the control chip in the solid state disk may include a Front End processing Layer (FE) and a Flash memory chip translation Layer (FTL).

The FE layer is responsible for interacting with the outside (e.g., receiving IO data of the requester) and pre-processing the outside data. The FTL layer is mainly used for completing the conversion between the virtual memory address and the physical memory address. The physical memory address is used herein to describe a physical memory address in a physical memory location.

The cache chip is used for caching the received IO data of the requester and waiting for writing the cached IO data into the flash memory chip.

In actual operation, the FE layer of the solid state disk may send the IO data requested to be divided to the FTL layer, and the FTL layer converts the virtual storage address corresponding to the IO data into a physical storage address, so that the IO data is written into the physical storage unit of the flash memory chip based on the physical storage address.

Wherein, IO data is ordered sequentially (according to the sequence of entering the FTL) when entering the FTL layer; if the data amount of the IO data is small, for example, less than or equal to 64K (generally, data less than or equal to 64K may be referred to as small IO data), many small IO data may be allocated to the same physical memory cell for storage. Since the same physical memory cell can only execute read-write operations in series, it is necessary to execute multiple read-write operations in series to complete the storage of the small IO data. And each time of pointing to the read-write operation has a certain delay, so that the overall read-write performance is low.

Referring to the schematic diagram of serially performing read/write operations shown in FIG. 2, assume that there are 4 IO data, each IO data has a size of 16KB, and there is 64KB in total; since the size of the 4 IO data is much smaller than the storage capacity of 1 data storage unit, the 4 IO data are stored in the same DIE. At this time, 4 read and write operations need to be performed serially. As shown in fig. 2, assuming that the basic storage granularity of the data storage unit is 4KB, 1 IO data can be stored in the data storage unit by one read-write operation; when the 1 st read-write operation is executed to store the 1 st IO data, the other 3 IO data need to wait; when the 2 nd read-write operation is executed to store the 2 nd IO data, the 3 rd and 4 th IO data need to wait; when the 3 rd read-write operation is executed to store the 3 rd IO data, the 4 th IO data needs to wait; when the 4 th read-write operation is executed to store the 4 th IO data, all the 4 IO data are stored. Assuming that the time duration required by one read/write operation is T, the total read/write time duration needs 4T when the 4 read/write operations are executed serially.

Therefore, when the solid state disk aims at small IO data, the problem of poor read-write performance is caused due to the fact that a large number of serial read-write operations exist.

In order to solve the above problems, the present specification aims to provide a scheme for improving the read-write performance of a solid state disk, and specifically, IO data is split into a plurality of physical storage units, and the plurality of physical storage units are used to execute read-write operations in parallel, so that the number of serial read-write operations can be reduced, thereby effectively reducing the delay of the read-write operations and improving the read-write performance of the solid state disk.

Please refer to the flowchart of the method for improving the read/write performance of the solid state disk shown in fig. 3, which can be applied to the solid state disk shown in fig. 1; the solid state disk comprises a plurality of flash memory chips, and each flash memory chip comprises a plurality of physical storage units; the method comprises the following steps:

step 310, encapsulating received IO data from a requester into a logic storage unit, and caching the logic storage unit into a cache space reserved by the solid state disk; and the storage capacity of the logic storage unit is an integral multiple of the IO data.

In this specification, after receiving IO data from a request segment, the solid state disk may encapsulate the IO data into a logical storage unit. Typically, the data size of the IO data includes 64KB, 32KB, or 16 KB.

When the IO data is encapsulated into the logical storage Unit, the IO data may be subjected to data alignment based on a related encapsulation technology, such as aumap (aligned Unit mapping), so as to align the data size to the storage capacity of the logical storage Unit, thereby encapsulating the aligned data into the logical storage Unit.

For example, assuming that the storage capacity of the logical storage unit is 64KB and the data size of the IO data is 32KB, when data alignment is performed on the IO data by the AUMAP, 2 IO data may be used as a group (exactly 64KB), and the IO data in the group is encapsulated to obtain 1 logical storage unit.

Further, a cache space may be disposed in the solid state disk, and the cache space is used for caching the logic storage unit obtained by encapsulation.

Wherein the cache space may include Write Buffer Group (WBG). Generally, the buffer capacity of the buffer space may be an integer multiple of the logical storage unit.

Step 320, splitting the logical storage unit in the cache space into a plurality of data units, and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit.

In this specification, after the logical storage unit is cached in the cache space, the logical storage unit may be split into a plurality of data units.

In the solid state disk, the basic storage granularity is generally 4KB, that is, a 4KB of data may correspond to a data unit; such data units may be referred to as dtag (data tag); accordingly, the logical storage unit may refer to bn (buffer node).

Typically, the storage capacity of the logical storage unit comprises 64 KB; the storage capacity of the data unit comprises 4 KB.

That is, 1 logical storage unit may include 16 data units inside, and thus 1 logical storage unit may be split into 16 data units.

The purpose of mapping the split data unit to the plurality of physical storage units is to improve the read-write performance in a manner that the plurality of physical storage units concurrently execute the read-write operation because the data is scattered to the plurality of physical storage units when the read-write operation is performed on the data in the logical storage unit.

In order to obtain higher read-write performance, the data units may be uniformly allocated to the physical storage units as much as possible, so that the number of data units processed by each physical storage unit is the same or equivalent, and thus, the waiting time is reduced as much as possible in the case of concurrent execution. For example, mapping 16 data units to 4 physical memory units, each of which is responsible for processing 4 data units, the 16 data units can be processed by 4 concurrent processes. Compared with the prior art which needs 16 times of processing under serial execution, the read-write performance of the system is improved by 4 times.

In this specification, the physical storage unit may include a wafer DIE in the flash memory chip; the Flash memory chip can comprise a NAND Flash chip and a NOR Flash chip. The NAND Flash chip adopts a nonlinear macro-unit mode, and has the advantages of large storage capacity, low manufacturing cost and the like; and thus is suitable for use in scenarios with high data storage density requirements, such as large servers.

In an exemplary embodiment, before splitting the logical storage unit in the cache space into several data units, the method may further include:

accordingly, the mapping the split data unit to a plurality of physical storage units may include:

In this specification, in the process of writing data into a solid state disk, it is necessary to allocate a virtual storage address to the data, convert the virtual storage address into a plurality of physical storage addresses (for example), and finally write the data into a plurality of physical storage units corresponding to the plurality of physical storage addresses.

The virtual storage Address may include a Fake PDA (Physical Data Address), which is a self-defined logical storage Address; the physical memory address corresponding to the data may then include the Real PDA, which is a physical memory address used to describe the data in flash memory.

The virtual memory address segment is a logically continuous virtual memory address; the continuous virtual memory addresses can improve the read-write efficiency of data. The storage capacity of the virtual storage address field is equal to the storage capacity of the logical storage unit; therefore, the 1 virtual storage address segment just contains a plurality of data units after the 1 logic storage unit is split, and the waste of virtual storage address resources is avoided.

The physical storage address segment is a physically continuous physical storage address; the continuous physical memory addresses can improve the reading and writing efficiency of data. The sum of the capacities of the plurality of physical storage address segments is equal to the storage capacity of the logical storage unit; therefore, the plurality of physical storage address segments just contain the plurality of data units after the splitting of the 1 logic storage unit, and the waste of physical storage address resources is avoided.

In addition, as shown in the foregoing, the solid state disk may further include a control chip in addition to the flash memory chip for storing data. The control chip is used for controlling the read-write operation of the solid state disk, and corresponding software programs are written in the control chip. From the software level, the software architecture of the solid state disk can comprise a front-end processing layer and a flash memory chip conversion layer; the front-end processing layer may further include an encapsulation Unit (AUMAP), and the flash memory chip conversion layer may further include an Allocation Unit (AU);

the packaging unit is used for packaging IO data from a requester into a logic storage unit; as shown in the foregoing embodiment, IO data is data-aligned based on the AUMAP to align the data size to the storage capacity of the logical storage unit, so that the aligned data is encapsulated into the logical storage unit.

The allocation unit is used for allocating a virtual storage address field for the logic storage unit and binding a plurality of physical storage address fields for the virtual storage address field; that is, the allocation unit executes the aforementioned allocation of the virtual storage address field to the logical storage unit, and binds a plurality of physical storage address fields to the virtual storage address field.

In an exemplary embodiment, the uniformly mapping the split data unit to the plurality of physical storage units may include:

and mapping the split data units to the physical storage addresses in the plurality of physical storage units respectively according to the corresponding sorting sequence of the data units in the logical storage units.

For example, assuming that there are 16 split data units, the 16 data units may be sequentially mapped to physical memory addresses in the 16 physical memory units according to a sequence.

Of course, in practical applications, if the number of the split data units is an integer multiple of the number of the plurality of physical storage units;

then, the mapping the split data unit to the physical storage addresses in the plurality of physical storage units respectively may include:

sequentially mapping the data units in each group to the same physical storage addresses in the plurality of physical storage units.

The following description will be made by taking the schematic diagram of parallel read/write operation shown in FIG. 4 as an example.

In fig. 4, taking the logic storage unit BN 0 as an example, splitting BN 0 may obtain 16 data units DTAG; suppose that the data of the physical memory unit DIE is 4; then the process of mapping the 16 DTAGs to 4 DIE may include:

the 16 DTAGs are sequentially divided into 4 groups according to 4 groups, wherein the first group is DTAG 1, DTAG 2, DTAG 3 and DTAG 4, the second group is DTAG 5, DTAG 6, DTAG 7 and DTAG 8, the second group is DTAG 9, DTAG 10, DTAG 11 and DTAG 12, and the fourth group is DTAG 13, DTAG 14, DTAG 15 and DTAG 16;

the DTAGs in each group are then mapped to the same physical memory addresses in the 4 DIEs in turn:

a first group: mapping the DTAG 1 to a physical storage address 1 in a 1 st physical storage unit DIE 0; mapping the DTAG 2 to a physical storage address 1 in a 2 nd physical storage unit DIE 1; mapping the DTAG 3 to a physical storage address 1 in a 3 rd physical storage unit DIE 2; mapping the DTAG 4 to a physical storage address 1 in a 4 th physical storage unit DIE 3;

second group: mapping the DTAG 5 to a physical storage address 2 in a 1 st physical storage unit DIE 0; mapping the DTAG 6 to a physical storage address 2 in a 2 nd physical storage unit DIE 1; mapping the DTAG 7 to a physical storage address 2 in a 3 rd physical storage unit DIE 2; mapping the DTAG 8 to a physical storage address 2 in a 4 th physical storage unit DIE 3;

third group: mapping the DTAG 9 to a physical storage address 3 in a 1 st physical storage unit DIE 0; mapping the DTAG 10 to a physical memory address 3 in a 2 nd physical memory unit DIE 1; mapping the DTAG 11 to a physical memory address 3 in a 3 rd physical memory unit DIE 2; mapping the DTAG 12 to a physical memory address 3 in a 4 th physical memory unit DIE 3;

third group: mapping the DTAG 13 to a physical storage address 4 in a 1 st physical storage unit DIE 0; mapping the DTAG 14 to a physical memory address 4 in a 2 nd physical memory unit DIE 1; mapping the DTAG 15 to a physical memory address 4 in a 3 rd physical memory unit DIE 2; the DTAG 16 is mapped to physical memory address 4 in the 4 th physical memory location DIE 3.

The above-mentioned way of mapping in sequence after grouping may also be referred to as cross mapping. Therefore, the data units are uniformly distributed to the physical storage units, so that the number of the data units which are processed by each physical storage unit is the same or equivalent, and the waiting time is reduced as much as possible under the condition of concurrent execution, thereby providing stronger read-write performance.

In an exemplary embodiment, the physical storage addresses corresponding to the plurality of physical storage units belong to a page table of the same plane page. As shown in fig. 4, the mapped physical memory addresses 1 to 4 of the physical memory units DIE 0 to DIE 4 are in the same plane page.

Because the physical storage addresses corresponding to the plurality of physical storage units belong to the page table of the same plane page, the efficiency of inquiring the page table is higher when the read-write operation is executed concurrently, the time delay of the read-write operation can be reduced, and the read-write performance of the solid state disk is further improved.

Step 330, in response to that the remaining storage capacity of the cache space meets the write-in condition, writing the data unit in the cache space into the corresponding physical storage unit for persistent storage according to the mapping relationship between the data unit and the physical storage unit.

In this specification, when the remaining storage capacity of the cache space satisfies the write-in condition, the data unit may be written into the corresponding physical storage unit according to the mapping relationship determined above, so as to complete persistent storage.

Here, the remaining storage capacity of the buffer space satisfies the writing condition, and may include various cases, for example, if the storage capacity of the buffer space is an integer multiple of the logical storage unit, then when the remaining storage capacity is 0, the writing condition is satisfied; and if the storage capacity of the cache space is not an integral multiple of the logical storage units, the writing condition is satisfied when the residual storage capacity is less than 1 logical storage unit. Wherein the writing condition may include a condition of data brushing.

By the embodiment, the IO data is split into the plurality of physical storage units, and the plurality of physical storage units are used for executing the write operation in parallel, so that the number of serial write operations can be reduced, the delay of the write operation is effectively reduced, and the write performance of the solid state disk is improved.

And for a read operation, the method further comprises:

Similar to the foregoing write operation, because IO data is written into a plurality of physical storage units, when reading, a plurality of physical storage units can also be used to perform read operation in parallel, and the number of serial read operations can be reduced, thereby effectively reducing the delay of read operation and improving the read performance of the solid state disk.

To sum up, in the embodiments provided in this specification, IO data received from a requester is encapsulated into a logical storage unit, and the logical storage unit is cached in a cache space reserved in the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data; splitting a logic storage unit in the cache space into a plurality of data units, and mapping the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit; and responding to the fact that the residual storage capacity of the cache space meets a writing condition, and writing the data units in the cache space into corresponding physical storage units for persistent storage according to the mapping relation between the data units and the physical storage units.

Because IO data is divided into a plurality of physical storage units, the plurality of physical storage units can be utilized to execute read-write operation in parallel, and the number of serial read-write operation can be reduced, so that the delay of the read-write operation is effectively reduced, and the read-write performance of the solid state disk is improved. For example, if there are 16 IO data and the IO data are allocated to 1 physical storage unit according to the existing manner, the processing needs to be performed 16 times according to the existing serial execution, but according to the scheme provided in this specification, the 16 IO data may be split into 4 physical storage units, each physical storage unit is responsible for processing 4 IO data, and the IO data may be processed through 4 concurrent processes. Compared with the prior art which needs 16 times of processing under serial execution, the read-write performance of the system is improved by 4 times.

Corresponding to the foregoing method embodiment for improving the performance of the solid state disk, this specification further provides an embodiment of an apparatus for improving the performance of the solid state disk. The device embodiments may be implemented by software, or by hardware, or by a combination of hardware and software. The software implementation is taken as an example, and is formed by reading a corresponding computer program in the nonvolatile memory into the memory for running through a processor of the device where the software implementation is located as a logical means. From a hardware aspect, as shown in fig. 5, for a hardware structure diagram of a device in which the apparatus for improving the performance of the solid state disk is located in this specification, except for the processor, the network interface, the memory, and the nonvolatile memory shown in fig. 5, the device in which the apparatus is located in the embodiment may also include other hardware according to an actual function of improving the performance of the solid state disk, which is not described again.

Referring to fig. 6, a block diagram of an apparatus for improving performance of a solid state disk according to an embodiment of the present disclosure is shown, where the apparatus corresponds to the embodiment shown in fig. 3, the solid state disk includes a plurality of flash memory chips, the flash memory chips include a plurality of physical memory units, and the apparatus includes:

the cache module 610 encapsulates the received IO data from the requester into a logical storage unit, and caches the logical storage unit in a cache space reserved in the solid state disk; the storage capacity of the logic storage unit is an integral multiple of the IO data;

the mapping module 620 splits the logical storage unit in the cache space into a plurality of data units, and maps the split data units to a plurality of physical storage units; wherein the data size of the IO data is an integer multiple of the data unit;

the writing module 630, in response to that the remaining storage capacity of the cache space meets the writing condition, writes the data unit in the cache space into the corresponding physical storage unit for persistent storage according to the mapping relationship between the data unit and the physical storage unit.

By applying the embodiment of the device, IO data are divided into the plurality of physical storage units, and the plurality of physical storage units are utilized to execute read-write operation in parallel, so that the number of serial read-write operation can be reduced, the delay of the read-write operation is effectively reduced, and the read-write performance of the solid state disk is improved.

Optionally, the mapping module 620 further includes:

the distribution submodule is used for distributing a virtual storage address field for the logic storage unit and binding a plurality of physical storage address fields for the virtual storage address field; wherein, each physical memory address segment corresponds to different physical memory units;

By applying the embodiment of the device, the plurality of data units subsequently split from the logical storage unit are written into the physical storage unit based on the bound physical storage address through the binding of the virtual storage address and the physical storage address.

By applying the embodiment of the device, the data units are mapped to the physical storage units according to the sorting sequence, so that the data is prevented from being disordered.

By applying the device embodiment, the plurality of data units can be uniformly distributed to the plurality of physical storage units, so that the number of the data units which are processed by each physical storage unit is the same or equivalent, and the waiting time is reduced as much as possible under the condition of concurrent execution, thereby providing stronger read-write performance.

By applying the device embodiment, the data reading and writing efficiency can be improved through the continuous virtual storage addresses and the continuous physical storage addresses. Moreover, the 1 virtual storage address segment just contains a plurality of data units after the 1 logic storage unit is split, so that the waste of virtual storage address resources is avoided. Similarly, the plurality of physical storage address segments just accommodate a plurality of data units obtained by splitting 1 logical storage unit, so that the waste of physical storage address resources is avoided.

By applying the device embodiment, because the physical storage addresses corresponding to the plurality of physical storage units belong to the page table of the same plane page, the efficiency of searching the page table is higher when the read-write operation is executed concurrently, the time delay of the read-write operation can be reduced, and the read-write performance of the solid state disk is further improved.

Optionally, the apparatus further comprises:

By applying the embodiment of the device, similar to the writing operation, because the IO data is written into the plurality of physical storage units, when reading, the reading operation can be executed in parallel by using the plurality of physical storage units, and the number of serial reading operations can be reduced, thereby effectively reducing the delay of the reading operation and improving the reading performance of the solid state disk.

By applying the device embodiment, a mode for IO data encapsulation and virtual storage address and physical virtual storage address conversion is provided from a software layer of the solid state disk, so that data encapsulation and storage address allocation binding are realized.

With the above device embodiment, for 64KB, 32KB or 16KB small IO data, 64KB logical storage units are set for storing the encapsulated small IO data, and 4KB data units are set for storing data mapped into physical storage units.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

The specific details of the implementation process of the functions and actions of each unit in the above device are the implementation processes of the corresponding steps in the above method, and are not described herein again.

For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution in the specification. One of ordinary skill in the art can understand and implement it without inventive effort.

With reference to fig. 6, an internal functional module and a structural schematic of an apparatus for improving performance of a solid state disk are described, where a substantial execution subject of the apparatus may be an electronic device, and the apparatus includes:

a processor;

a memory for storing processor-executable instructions;

the processor is configured to execute any of the above embodiments of the method for improving the performance of the solid state disk.

In the above embodiments of the electronic device, it should be understood that the Processor may be a CPU, and may also be other general-purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), and so on. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor, and the memory may be a read-only memory (ROM), a Random Access Memory (RAM), a flash memory, a hard disk, or a solid state disk. The steps of a method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiment of the electronic device, since it is substantially similar to the embodiment of the method, the description is simple, and for the relevant points, reference may be made to part of the description of the embodiment of the method.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.

It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

Claims

1. A method for improving the performance of a solid state disk, wherein the solid state disk comprises a plurality of flash memory chips, the flash memory chips comprise a plurality of physical storage units, and the method comprises the following steps:

2. The method of claim 1, further comprising, prior to splitting the logical storage unit in the cache space into the data units:

mapping the split data unit to a plurality of physical storage units includes:

3. The method of claim 2, the evenly mapping the split data units to the plurality of physical storage units, comprising:

4. The method of claim 3, the number of the split data units being an integer multiple of the number of the plurality of physical storage units;

5. The method of claim 2, the virtual memory address segment being a logically contiguous virtual memory address; the storage capacity of the virtual storage address segment is equal to the storage capacity of the logical storage unit;

6. The method of claim 4, wherein the physical memory addresses of the plurality of physical memory units belong to a page table of the same plane page.

7. The method of claim 1, further comprising:

8. The method of claim 2, wherein the software architecture of the solid state disk comprises a front end processing layer and a flash chip translation layer; the front-end processing layer comprises a packaging unit, and the flash memory chip conversion layer comprises a distribution unit;

9. The method of claim 1, the data size of the IO data comprising 64KB, 32KB, or 16 KB; the storage capacity of the logical storage unit comprises 64 KB; the storage capacity of the data unit comprises 4 KB.

10. The method of claim 1, the physical storage unit comprising a wafer in the flash memory chip; the Flash memory chip comprises a NAND Flash chip; the cache space comprises a Write Buffer Group; the logic storage unit comprises a Buffer Node; the DATA unit includes a DATA TAG.

11. The utility model provides a promote device of solid state hard disk performance, solid state hard disk includes a plurality of flash memory chips, the flash memory chip includes a plurality of physical memory cell, the device includes:

12. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to perform the method of any of the preceding claims 1-10.

13. A computer-readable storage medium whose instructions, when executed by a processor of an electronic device, enable the electronic device to perform the method of any of claims 1-10.