CN115065329A - Grid voltage switching dual-channel selective power amplifier circuit - Google Patents
Grid voltage switching dual-channel selective power amplifier circuit Download PDFInfo
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- CN115065329A CN115065329A CN202210859212.XA CN202210859212A CN115065329A CN 115065329 A CN115065329 A CN 115065329A CN 202210859212 A CN202210859212 A CN 202210859212A CN 115065329 A CN115065329 A CN 115065329A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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Abstract
The invention discloses a grid voltage switching dual-channel selection power amplifier circuit, which integrates two matching circuits with different output powers and different working frequencies by designing a matching circuit structure. Meanwhile, the grid voltage bias network of the final-stage tube core of the amplifier circuit is divided into two networks, different final-stage tube cores are respectively controlled, and the monolithic integrated power amplifier circuit with dual-channel operation is realized by switching the grid voltage. The invention can integrate two power amplifier circuits with different output powers and different working frequencies into one chip, thereby greatly reducing the design cost of the chip, reducing the complexity of the system, reducing the loss of a matching link and improving the flexibility of the system application.
Description
Technical Field
The invention relates to a monolithic microwave integrated circuit, in particular to a grid voltage switching dual-channel selection power amplifier circuit.
Background
With further complexity of application scenes and requirements, higher requirements are provided for a new generation of radar, integration of multiple functions is required to be realized, and the system complexity is greatly improved. Conventional single-function radars need to complete multiple tasks by multiple radar antennas, which not only occupies a large amount of space, but also consumes a large amount of resources. Pure broadband high power can cause the performance of a transmitting link to be reduced, and under the condition of a limited power supply system, enough detection distance cannot be ensured. Therefore, switching the working modes according to different task requirements is a good solution to the problem.
The conventional single-function power amplifier can only work in one state and outputs fixed power, and the final stage and the last stage circuit are shown in figures 1 and 2. Taking the number of the last stage tube cells as 4 as an example, 116 is a grid voltage power-on bonding point of a last stage tube core, the grids of 4 tube cores 103 are all controlled by the same grid voltage switch, and the last stage matching circuit matches the output impedance of the tube cores 103 to 50 omega, so that the operating frequency and the output power of the obtained power amplifier are fixed values. The radar using the single-function power amplifier needs a plurality of radar antennas to complete the tasks of detection, communication, interference and the like, not only occupies a large amount of space, but also consumes a large amount of resources.
Disclosure of Invention
In order to solve the technical problems mentioned in the background art, the invention provides a gate voltage switching dual-channel selection power amplifier circuit.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
the utility model provides a power amplifier circuit is selected to grid voltage switching binary channels, includes the substrate, forms grid voltage switching last-stage matching network circuit, active area, big or small power amplifier high efficiency sharing last-stage matching circuit, first grid voltage add briquetting VG1 and second grid voltage add briquetting VG2 on the substrate, grid voltage switching last-stage matching network circuit with insert after the active area is connected big or small power amplifier high efficiency sharing last-stage matching circuit, the active area includes two sets of last stage die of mirror image distribution: the first final-stage die FET1, the second final-stage die FET2, the fourth capacitor C4 and the sixth capacitor C6, the grid of the first final-stage die FET1 is respectively connected with one end of the fourth capacitor C4 and a grid voltage adding voltage block VG1, the grid of the second final-stage die FET2 is respectively connected with one end of the sixth capacitor C6 and a second grid voltage adding voltage block VG2, the other ends of the fourth capacitor and the sixth capacitor are grounded, the grid voltage adding voltage block outputs different feeding voltages to control the number of work of the final-stage die, and therefore the final-stage matching circuit is shared by controlling the high efficiency of the large and small power amplifiers to output different powers.
Preferably, the two mirror-distributed last-stage die each comprise 2 n And single junction transistors connected in parallel in sequence.
Preferably, the high-efficiency shared final-stage matching circuit with large and small power amplifiers comprises a first circuit unit M1, a second circuit unit M2, a second capacitor C2 and a third capacitor C3, the first circuit unit M1 and the second circuit unit M2 are distributed in a mirror image manner, the first circuit unit M1 comprises a MIN capacitor C1, a first microstrip line L1, a second microstrip line L2 and a third microstrip line L3, the MIM capacitor C1, the first microstrip line L1 and the second microstrip line L2 in the first circuit unit M1 are sequentially connected in series, a dc feed circuit network bonding voltage point VD is connected to a common end of the capacitor C1 and the first microstrip line L1, the common ends of the first microstrip line L1 and the second microstrip line L2 are connected to a midpoint of the microstrip line L7, one end of the third microstrip line L3 is connected to a drain of the first final-stage FET1, the other end of the second microstrip line L1 is connected to a drain of the MIM capacitor M1, the mirror image unit M1 and the second microstrip line M36 32 in the first microstrip line 1 are connected to each other, the common end of the second microstrip line L2 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 serves as an output end, and the second microstrip line L2 is connected to the common end of the third capacitor C3 and the second capacitor C2, and then grounded.
Preferably, the microwave power signals of the mirror points in the first circuit unit M1 and the second circuit unit M2 have the same amplitude and phase.
Preferably, the gate voltage switching end-stage matching network circuit includes a third circuit unit M3, a fourth circuit unit M4, and an eighth capacitor C8, the third circuit unit M3 and the fourth circuit unit M4 are distributed in a mirror image, the third circuit unit M3 includes a 51 st capacitor C51, a 52 th capacitor C52, a seventh capacitor C7, and a fourth microstrip line L4, one end of the 51 st capacitor C51 is connected to the gate of the first last-stage die FET1, one end of the 52 th capacitor C52 is connected to the gate of the second last-stage die FET2, the other end of the 51 st capacitor C51 is connected to the other end of the 52 th capacitor C52, common ends of the 51 st capacitor C51 and the 52 th capacitor C52 are respectively connected to one end of the seventh capacitor C7 and one end of the fourth microstrip line L4, and the other end of the seventh capacitor serves as an output end of a signal.
Preferably, the input signal is split into two paths after passing through the 51 st capacitor C51 and the 52 th capacitor C52 and then input into the first final stage die FET1 and the second final stage die FET2, and the 51 st capacitor C51 and the 52 th capacitor C52 gate-voltage-isolate the final stage die FET1 and the final stage die FET2, and switch the gate-voltage mode.
Preferably, when both gate voltage supply blocks VG1 and VG2 output an operating supply voltage, the final die FET1 and final die FET2 operate normally when the circuit is in a high power mode, and when voltage block VG1 outputs a cutoff supply voltage, the final die FET1 is off when the circuit is in a low power mode.
Preferably, the frequency of the high-power working mode is 8-12GHz, and the output power is 20W; the frequency of the low-power working mode is 6-18GHz, and the output power is 38 dBm.
Preferably, the grid voltage switching dual-channel selective power amplifier circuit adopts a GaAs or GaN material as a substrate.
Preferably, the grid voltage switching dual-channel selection power amplifier circuit chip is manufactured by a 0.25 mu m or 0.2 mu m process, the substrate is 80 mu m thick, and the upper surface gold layer is 3.3 mu m thick.
The technical effects brought by adopting the technical scheme are as follows:
a topological circuit structure is designed, output circuits with different frequencies and different output powers are fused together, double-channel selection of a broadband matching circuit is achieved, and loss of an amplifier output matching network is reduced.
The grid bias circuit of the tube core is separated, the purpose of double-channel selection can be realized only by controlling grid voltage, the complexity of the system is reduced, and the loss of a matching link is reduced.
The grid voltage is switched according to different task requirements, so that the requirements of a new generation of multifunctional radar and multifunctional integration are met.
Drawings
FIG. 1 is a circuit layout of a conventional single-output microwave and millimeter wave monolithic integrated power amplifier;
FIG. 2 is a schematic circuit diagram of a conventional single output microwave and millimeter wave monolithic integrated power amplifier;
FIG. 3 is a circuit layout of the multi-functional microwave and millimeter wave monolithic integrated power amplifier of the present invention;
FIG. 4 is a schematic circuit diagram of a multi-functional microwave and millimeter wave monolithic integrated power amplifier of the present invention;
fig. 5 is a graph of the output power of a gate voltage switched power amplifier.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention discloses a grid voltage switching dual-channel selection power amplifier circuit which comprises a large power amplifier and a small power amplifier high-efficiency shared last-stage matching circuit, a last-stage matching network capable of carrying out grid voltage switching and a preceding-stage matching network. As shown in fig. 3.
The final stage matching circuit of the circuit is formed by M1 and M2 mirror image circuit units, C2 and C3 after microstrip synthesis from the drain electrodes of the FTE1 and the FET2, and the amplitude and the phase of microwave power signals of each mirror image point in the two units are consistent.
Taking the number of the last stage tube cells as 4 as an example, when the high-power mode is operated, the tube cells FTE1 and the FET2 both work normally, the output impedance of the last stage tube cores FTE1 and FET2 is matched to 50 omega by the last stage matching circuit, and the microstrip branch lines L31 and L32 are connected with the tube cores FTE1 and FET2 in series to form the last stage matching circuit. When the chip operates in a low-power mode, the tube cell FET2 operates normally, the FTE1 is cut off, the final stage matching circuit matches the output impedance of the final stage die FET2 to 50 omega, and the microstrip line L31, L32 and the die FTE1 in the cut-off state are connected in series to a ground branch to form the final stage matching circuit of the die FET 2.
In the circuit unit M1, the dc feed circuit network starts from the bonding voltage VD, and goes in parallel with the MIM (metal-insulator-metal) capacitor C11, then in series with the microstrip line L11, connecting the two symmetrical microstrip lines L31 of the branches into the die FTE1 and the drain of the FET 2. The microwave power signal circuit network is connected with a synthesis microstrip L31 passing through the tube core in series from the tube core FTE1 and the drain electrode of the FET2, is connected with a microstrip line L21 in series after being connected with a direct current feed network in parallel, is connected with an MIM (metal-insulator-metal) capacitor C2 in parallel, and is connected with an MIM (metal-insulator-metal) capacitor C3 in series for output. The circuit unit M2 also has the same structure.
The last stage matching network of the circuit can carry out grid voltage switching, and the grid voltage switching control is carried out through grid feeding bonding voltage points VG1 and VG 2. When the appropriate voltage is input to the feed voltage points VG1, VG2, both the die FTE1 and the FET2 operate normally, and in a high power mode. When the appropriate voltage is input to VG2 and the cut-off voltage is input to VG1, the die FET2 operates normally and FET1 turns off, and operates in a low power mode.
The bond point VG1 in the last stage of the circuit is connected in parallel with MIM (metal-insulator-metal) capacitors C41, C42, and then connected in series with resistors to the gate of last stage die FET 1. The bond point VG2 is connected in parallel with MIM (metal-insulator-metal) capacitor C6 and then connected to the gate of final die FET 2. MIM (metal-insulator-metal) capacitors C41, C42, C6 guarantee circuit symmetry.
For M4, signals are input to final stage die FET1 and FET2 in two paths through MIM (metal-insulator-metal) capacitors C53 and C54, and simultaneously, MIM capacitors C53 and C54 isolate gate voltages of die FET1 and FET2, thereby ensuring the implementation of a gate voltage switching mode.
The circuit chip is manufactured by a proper semiconductor technology considering the working frequency band, power, efficiency, uniformity, yield and cost, and the wafer of the circuit chip is made of GaAs or GaN material as the substrate, but the circuit chip is not limited to this.
The circuit chip is manufactured by 0.25 μm or 0.2 μm technology, and the substrate is 80 μm thick. The upper surface gold layer is 3.3 μm thick.
For example, a gate voltage switching channel selection microwave millimeter wave monolithic integrated power amplifier is developed by adopting a 0.20um GaN HEMT process. As shown in FIG. 5, the frequency of the high-power operation mode is 8-12GHz, and the output typical power is 20W; the low power mode of operation has a frequency of 6-18GHz and outputs a typical power of 38 dBm. The power amplifier circuit with two different output powers and different working frequencies is integrated on one chip, so that the integration of functions such as detection, interference, detection, communication and the like is realized, the chip design cost is greatly reduced, the system complexity is reduced, and the flexibility of system application is improved.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (10)
1. The utility model provides a power amplifier circuit is selected to grid voltage switching binary channels, its characterized in that, includes the substrate, forms grid voltage switching last preceding stage matching network circuit, active area, big or small power amplifier high efficiency sharing last stage matching circuit, first grid voltage add briquetting VG1 and second grid voltage add briquetting VG2 on the substrate, grid voltage switching last preceding stage matching network circuit with insert after the active area is connected big or small power amplifier high efficiency sharing last stage matching circuit, the active area includes two sets of last stage die of mirror image distribution: the first final-stage tube core FET1, the second final-stage tube core FET2, a fourth capacitor C4 and a sixth capacitor C6, wherein the grid electrode of the first final-stage tube core FET1 is respectively connected with one end of the fourth capacitor C4 and a grid voltage adding voltage block VG1, the grid electrode of the second final-stage tube core FET2 is respectively connected with one end of the sixth capacitor C6 and a second grid voltage adding voltage block VG2, the other ends of the fourth capacitor and the sixth capacitor are grounded, and the grid voltage adding voltage block outputs different feed voltages to control the number of the final-stage tube cores in work, so that the high-efficiency shared final-stage matching circuit of the large power amplifier and the small power amplifier outputs different powers.
2. The gate-voltage-switched dual-channel selective power amplifier circuit of claim 1, wherein the two mirror-distributed groups of last stage dies each comprise 2 n And single junction transistors connected in parallel in sequence.
3. The gate voltage switching dual-channel selective power amplifier circuit according to claim 1, wherein the large-power-amplifier high-efficiency shared final stage matching circuit comprises a first circuit unit M1, a second circuit unit M2, a second capacitor C2 and a third capacitor C3, the first circuit unit M1 and the second circuit unit M2 are distributed in a mirror image manner, the first circuit unit M1 comprises a capacitor C1, a first microstrip line L1, a second microstrip line L2 and a third microstrip line L3, the MIM capacitor C1, the first microstrip line L1 and the second microstrip line L2 in the first circuit unit M1 are sequentially connected in series, a bonding voltage VD of a DC feed circuit network is connected to a common end of the MIM capacitor C1 and the first microstrip line L1, a common end of the first microstrip line L1 and the second microstrip line L2 is connected to a midpoint of the microstrip line L3, and one end of the third microstrip line VD 3 is connected to an end of the FET drain terminal 1 of the first FET, the other end of the microstrip line L3526 is connected to the drain of the second last-stage die FET2, the microstrip line L2 in the first circuit unit M1 is connected to the mirror-image microstrip line in the second circuit unit M2, the common end of the second microstrip line L2 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is used as an output end, and the second microstrip line L2 is connected to the common end of the third capacitor C3 and the second capacitor C2 respectively and then grounded.
4. The gate voltage switching dual channel selective power amplifier circuit as claimed in claim 3, wherein the microwave power signals at the mirror points in the first circuit unit M1 and the second circuit unit M2 have the same amplitude and phase.
5. The gate voltage switching dual channel selective power amplifier circuit of claim 1, the grid voltage switching last stage matching network circuit comprises a third circuit unit M3, a fourth circuit unit M4 and an eighth capacitor C8, the third circuit unit M3 and the fourth circuit unit M4 are distributed in a mirror image manner, the third circuit unit M3 includes a 51 st capacitor C51, a 52 th capacitor C52, a seventh capacitor C7 and a fourth microstrip line L4, one end of the 51 st capacitor C51 is connected to the gate of the first last stage die FET1, one end of the 52 nd capacitor C52 is connected to the gate of the second last stage die FET2, the other end of the 51 st capacitor C51 is connected to the other end of the 52 th capacitor C52, the common end of the 51 st capacitor C51 and the 52 th capacitor C52 is connected to one end of the seventh capacitor C7 and one end of the fourth microstrip line L4, respectively, and the other end of the seventh capacitor is used as a signal output end.
6. The gate voltage switching dual-channel selective power amplifier circuit as claimed in claim 5, wherein the input signal is divided into two paths after passing through a 51 st capacitor C51 and a 52 nd capacitor C52 and then input into a first final stage die FET1 and a second final stage die FET2, and the 51 st capacitor C51 and the 52 nd capacitor C52 are used for gate voltage isolation of the final stage die FET1 and the final stage die FET2, and the gate voltage mode is switched.
7. The gate voltage switching dual channel selective power amplifier circuit as claimed in claim 1, wherein the final die FET1 and final die FET2 operate normally when the two gate voltage adding voltage blocks VG1 and VG2 output the operating feed voltage, the circuit is in high power mode, the final die FET1 is off when the voltage block VG1 outputs the off feed voltage, and the circuit is in low power mode.
8. The gate voltage switching dual channel selective power amplifier circuit as claimed in claim 7, wherein the high power operating mode frequency is 8-12GHz, and the output power is 20W; the frequency of the low-power working mode is 6-18GHz, and the output power is 38 dBm.
9. The gate voltage switching dual channel selective power amplifier circuit of claim 1, wherein the gate voltage switching dual channel selective power amplifier circuit uses GaAs or GaN material as a substrate.
10. The circuit of claim 1, wherein the die of the gate voltage switching dual channel selective power amplifier circuit is fabricated by a 0.25 μm or 0.2 μm process, the substrate is 80 μm thick, and the gold layer on the top surface is 3.3 μm thick.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210859212.XA CN115065329A (en) | 2022-07-20 | 2022-07-20 | Grid voltage switching dual-channel selective power amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210859212.XA CN115065329A (en) | 2022-07-20 | 2022-07-20 | Grid voltage switching dual-channel selective power amplifier circuit |
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| Publication Number | Publication Date |
|---|---|
| CN115065329A true CN115065329A (en) | 2022-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210859212.XA Pending CN115065329A (en) | 2022-07-20 | 2022-07-20 | Grid voltage switching dual-channel selective power amplifier circuit |
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| Country | Link |
|---|---|
| CN (1) | CN115065329A (en) |
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- 2022-07-20 CN CN202210859212.XA patent/CN115065329A/en active Pending
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