CN115064533A - Array substrate, display panel, display device and preparation method of array substrate - Google Patents
Array substrate, display panel, display device and preparation method of array substrate Download PDFInfo
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- CN115064533A CN115064533A CN202210608464.5A CN202210608464A CN115064533A CN 115064533 A CN115064533 A CN 115064533A CN 202210608464 A CN202210608464 A CN 202210608464A CN 115064533 A CN115064533 A CN 115064533A
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 3
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 5
- 230000003068 static effect Effects 0.000 abstract description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 4
- 238000013461 design Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000011161 development Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The application discloses an array substrate, a display panel, a display device and a preparation method of the array substrate. The embodiment of the application provides an array substrate, and the array substrate comprises an electrostatic discharge assembly, a first lead and a second lead. The electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals, and the plurality of electrostatic discharge blocks are arranged to realize electrostatic protection on the array substrate. The first lead connects the static electricity releasing block with the second lead, so that the static electricity releasing block is conducted with the second lead through the first lead. The second lead impedance is less than the first lead impedance, increasing the resistance of the overall line. Adopt the great first lead wire of impedance to connect the quick and second lead wire of electrostatic discharge to reduce the electric current in the circuit, avoid causing the display panel to turn green because of the electric current is too big.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate, a display panel, a display device and a preparation method of the array substrate.
Background
With the rapid development of display technology, in order to meet the high requirements of people on the display function of the display panel, the quality of the display panel is higher and higher.
To ensure the quality of the display panel, a series of reliability tests including a dependency test of the display panel are performed on the display panel in the process. For example, in the 8585 test, the display panel is operated at 85 degrees centigrade and 85% relative humidity continuously for 240 hours. Currently, after the 8585 test, the heavy-duty screen of the display panel will appear green.
Disclosure of Invention
The embodiment of the application provides an array substrate, a display panel, a display device and a preparation method of the array substrate, and aims to solve the problem that the display panel is green due to overlarge current.
An embodiment of a first aspect of the present application provides an array substrate, which includes: the electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals; one end of the first lead segment is connected with at least one electrostatic discharge block; and the second lead is connected to one end of the first lead, which is far away from the electrostatic discharge block, and the impedance of the second lead is smaller than that of the first lead.
Embodiments of the second aspect of the present application provide a display panel, which includes the array substrate of any one of the above embodiments.
Embodiments of a third aspect of the present application provide a method for manufacturing an array substrate, including:
preparing an electrostatic discharge assembly, wherein the electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals;
preparing a conductor material layer, and carrying out patterning treatment to obtain a first lead, wherein one end of a first lead segment is connected to at least one electrostatic discharge block;
and preparing a metal material layer on one side of the conductor material layer, and carrying out patterning treatment to obtain a second lead, wherein the second lead is connected to one end of the first lead, which is far away from the electrostatic discharge block, and the impedance of the second lead is smaller than that of the first lead.
According to the array substrate of the embodiment of the application, the array substrate comprises an electrostatic discharge assembly, a first lead and a second lead. The electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals, and the plurality of electrostatic discharge blocks are arranged to realize electrostatic protection on the array substrate. The first lead connects the static electricity releasing block with the second lead, so that the static electricity releasing block is conducted with the second lead through the first lead. The first lead impedance is greater than the second lead impedance, increasing the resistance of the overall line. Adopt the great first lead wire of impedance to connect static electricity discharge piece and second lead wire to reduce the electric current in the circuit, avoid causing the display panel to turn green because of the electric current is too big.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of a first aspect of the present application;
FIG. 2 is an enlarged partial schematic view of FIG. 1 at Q;
FIG. 3 is a partial enlarged view of the structure at Q in another embodiment;
FIG. 4 is a partial enlarged view of the structure at Q in still another embodiment;
FIG. 5 is a partial enlarged view of the structure at Q in still another embodiment;
FIG. 6 is a schematic view of a partial enlarged structure at Q in still another embodiment;
FIG. 7 is a partial cross-sectional view taken at Q of FIG. 1;
fig. 8 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the fourth aspect of the present application.
Description of reference numerals:
10. a display panel; 11. an array substrate;
100. an electrostatic discharge assembly; 101. a first electrostatic discharge block; 102. a second electrostatic discharge block;
110. a first lead; 120. a second lead; 121. a first segment; 122. a second section; 130. a third lead; 140. a fourth lead;
200. a connection point; 210. straight line
300. A gate metal layer; 400. a source drain metal layer;
x, a first direction; y, second direction.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
For electronic devices such as mobile phones and tablet computers, it is necessary to perform a dependency test on the display panel 10 before the product is shipped, and in some related technologies, a 8585 test, a so-called 8585 test, is performed on the display panel 10, in which a screen continuously operates for 240 hours at 85 degrees celsius and 85% relative humidity. After the 8585 test is performed on the display panel 10, the display panel 10 may be heavily green.
In order to solve the above problems, embodiments of the present application provide an array substrate 11, a display panel 10, a display device, and a method for manufacturing the array substrate 11, and embodiments of the array substrate 11, the display panel 10, the display device, and the method for manufacturing the array substrate 11 will be described below with reference to the accompanying drawings.
Referring to fig. 1 and fig. 2 together, fig. 1 is a schematic structural diagram of a display panel 10 according to an embodiment of the first aspect of the present application; fig. 2 is a partially enlarged schematic view of a structure at Q in fig. 1.
In some alternative embodiments, the display panel 10 has a display area and a non-display area, and the present application is described with respect to the Q region in the non-display area. In some embodiments, the Q region is a shaped region or a C-angle region located in the non-display area.
The array substrate 11 provided by the embodiment of the first aspect of the present application includes an electrostatic discharge assembly 100, a first lead 110, and a second lead 120, where the electrostatic discharge assembly 100 includes a plurality of electrostatic discharge blocks arranged at intervals. One end of the first lead 110 is connected to at least one electrostatic discharge block, the second lead 120 is connected to one end of the first lead 110 away from the electrostatic discharge block, and the impedance of the second lead 120 is smaller than that of the first lead 110.
According to the array substrate 11 of the embodiment of the present application, the array substrate 11 includes an electrostatic discharge assembly 100, a first lead 110, and a second lead 120. The electrostatic discharge assembly 100 includes a plurality of electrostatic discharge blocks arranged at intervals, and the plurality of electrostatic discharge blocks are arranged to implement electrostatic protection of the array substrate 11. The first lead 110 connects the electrostatic discharge block with the second lead 120, so that the electrostatic discharge block is conducted with the second lead 120 through the first lead 110. The impedance of the first leg 110 is greater than the impedance of the second leg 120, increasing the overall line resistance. The first lead 110 with high impedance is used to connect the electrostatic discharge block 101 and the second lead 120, so as to reduce the current in the circuit and avoid the display panel 10 from turning green due to the excessive current.
Referring to fig. 3, fig. 3 is a schematic diagram of a partial enlarged structure at Q in another embodiment.
In some optional embodiments, the array substrate 11 further includes a third lead 130 and a fourth lead 140, the plurality of electrostatic discharge blocks includes a first electrostatic discharge block 101 and a second electrostatic discharge block 102, the first electrostatic discharge block 101 is connected to the second lead 120 through the first lead 110, and the second lead 120 and the third lead 130 are connected through a via; the second electrostatic discharge block 102 is connected to the fourth lead 140, and the fourth lead 140 and the third lead 130 are arranged in different layers.
In these alternative embodiments, the third lead 130 is connected to the second lead 120 via a via, and the second lead 120 conducts the first lead 110 and the third lead 130, so that current flows from the second lead 120 to the third lead 130. The first lead 110 connects the first electrostatic discharge block 101 and the second lead 120, and since the impedance of the first lead 110 is greater than that of the second lead 120, the current flowing through the first lead 110 is reduced, so that the current in the whole circuit is reduced, and the phenomenon that the display panel 10 turns green due to excessive current is avoided. The second electrostatic discharge block 102 is connected to the fourth lead 140, and the second electrostatic discharge block 102 is turned on to implement the electrostatic protection function thereof. The fourth lead 140 and the third lead 130 are arranged in different layers, and the wiring space between the fourth lead 140 and the third lead 130 is large, so that convenience in wire arrangement of the fourth lead 140 is facilitated.
In some alternative embodiments, the second lead 120 and the fourth lead 140 are disposed in the same layer and are the same material.
In these alternative embodiments, the second lead 120 and the fourth lead 140 are disposed in the same layer, the second lead 120 and the fourth lead 140 can be simultaneously manufactured, so that the manufacturing process is simplified, and the second lead 120 and the fourth lead 140 are made of the same material.
Referring to fig. 3, in some alternative embodiments, the third lead 130 is located on one side of the electrostatic discharge device 100 in the first direction X, and the first electrostatic discharge block 101 is located on one side of the second electrostatic discharge block 102 facing the third lead 130
In these alternative embodiments, the third lead 130 is located at one side of the electrostatic discharging block in the first direction X, and since the electrostatic discharging blocks are arranged at intervals in the second direction Y, the space at one side of the electrostatic discharging block in the first direction X is larger, which facilitates the wiring of the third lead 130. The first electrostatic discharge block 101 is located on one side of the second electrostatic discharge block 102 facing the third lead 130, so that the first electrostatic discharge block 101 is directly connected with the first lead 110, and the distance between the first electrostatic discharge block 101 and the first lead 110 is reduced, thereby reducing the design complexity, reducing the design cost, and ensuring that the first lead 110 has a larger resistance, so as to reduce the current in the circuit and avoid the display panel 10 from being green due to the excessive current.
In some optional embodiments, the plurality of first electrostatic discharge blocks 101 are spaced along the second direction Y, the plurality of second electrostatic discharge blocks 102 are spaced along the second direction Y, and the plurality of first electrostatic discharge blocks 101 are located at a side of the plurality of second electrostatic discharge blocks 102 facing the third lead 130 in the first direction X.
In these alternative embodiments, the plurality of first electrostatic discharge blocks 101 and the plurality of second electrostatic discharge blocks 102 are both distributed at intervals along the second direction Y, so that both have a larger space on one side of the first direction X, facilitating the wiring of the first lead 110 and the second lead 120. The plurality of first electrostatic discharge blocks 101 are located on one side of the plurality of second electrostatic discharge blocks 102 facing the third lead 130, so that the first electrostatic discharge blocks 101 are directly connected with the first lead 110, and the distance between the first electrostatic discharge blocks 101 and the first lead 110 is reduced, thereby reducing the design complexity, facilitating the wiring of the first lead 110, reducing the design cost, ensuring that the first lead 110 has larger resistance, reducing the current in the circuit, and avoiding the green color of the display panel 10 caused by the overlarge current.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a partial enlarged structure at Q in another embodiment.
In some optional embodiments, the second lead 120 includes a first segment 121 and a second segment 122, the first segment 121 is located on one side of the first electrostatic discharge block 101 in the second direction Y, the second segment 122 is connected to the first lead 110 and extends away from the first electrostatic discharge block 101 in the first direction X, the second segment 122 extends obliquely toward the electrostatic discharge block in the second direction Y, the first lead 110 is connected to one side of the first electrostatic discharge block 101 in the first direction X, and the first lead 110 is connected between the second segment 122 and the first electrostatic discharge block 101.
In these alternative embodiments, the first segment 121 is located on one side of the first electrostatic discharge blocks 101 in the second direction Y, and the space between two adjacent first electrostatic discharge blocks 101 is fully utilized, so that the space utilization rate is improved. The second segment 122 is connected to the first lead 110 and extends away from the first electrostatic discharge block 101 in the first direction X, the second lead 120 is connected to the first lead 110 in the second segment 122, when the second segment 122 extends towards the electrostatic discharge block in the second direction Y, the first lead 110 is connected between the second segment 122 and the first electrostatic discharge block 101, so that the distance between the second segment 122 and the first electrostatic discharge block 101 is reduced, and the second segment 122 is connected with the first electrostatic discharge block 101 by using the first lead 110 which is relatively short, which not only reduces the design complexity and the design cost, but also ensures that the first lead 110 has relatively large resistance to reduce the current in the line and avoid the display panel 10 from turning green due to the excessive current. The first lead 110 is connected to one side of the first electrostatic discharge block 101 in the first direction X, and since the electrostatic discharge blocks are arranged at intervals in the second direction Y, a space on one side of the electrostatic discharge block in the first direction X is large, which is convenient for wiring the first lead 110.
In some alternative embodiments, each second segment 122 is at the same angle to the second direction Y.
In these alternative embodiments, the second segments 122 are the same in direction, so as to reduce the complexity of design and facilitate uniform wiring.
In some optional embodiments, the first lead 110 extends along the first direction X, and the first lead 110 extends along the first direction X to form the straight line 210, which not only reduces the complexity of the design, facilitates the wiring of the first lead 110, and reduces the design cost, but also ensures that the first lead 110 has a larger resistance, so as to reduce the current in the line and avoid the display panel 10 from turning green due to the excessive current.
Referring to fig. 5 and 6, fig. 5 is a schematic diagram illustrating a partial enlarged structure at Q in yet another embodiment;
fig. 6 is a partial enlarged structural view at Q in still another embodiment.
In some alternative embodiments, the first lead 110 is in a zigzag shape or the first lead 110 extends in a serpentine shape along a meandering path.
In these alternative embodiments, the first lead 110 is located in the limited space between the first electrostatic discharge block 101 and the second segment 122, and the length of the first lead 110 is increased as much as possible, so that the first lead 110 has a larger resistance, and the current in the line is reduced, thereby preventing the display panel 10 from turning green due to an excessive current.
Referring to fig. 6, in some alternative embodiments, the connection point 200 of the first lead 110 and the second lead 120 corresponding to the first electrostatic discharge blocks 101 is located on a straight line 210 extending in the second direction Y. The straight line 210 is a reference line, and the straight line 210 does not form a limitation on the structure of the array substrate of the present application.
In these optional embodiments, the connection point 200 of the first electrostatic discharge block 101 and the first lead 110 is located on the same straight line 210 in the second direction Y, and the structural design of the connection point is the same, so that the design complexity is reduced, the wiring of the first lead 110 is facilitated, and the design cost is reduced.
Optionally, the distances between adjacent connection points 200 are all equal. The distances between the connection points 200 are the same, the distribution rule is regular, the design complexity is reduced, the wiring of the first lead 110 is facilitated, and the design cost is reduced.
Alternatively, the first leads 110 are identical in shape. Each first lead 110 shape is the same, is convenient for unify the design wiring, reduces the loaded down with trivial details degree of design, is convenient for first lead 110's wiring, reduces design cost.
Alternatively, the total length of each first lead 110 is the same. On the one hand, the lengths of the first leads 110 are the same, so that unified design and wiring are facilitated, the design complexity is reduced, the wiring of the first leads 110 is facilitated, and the design cost is reduced. On the other hand, the first leads 110 have the same resistance, so that the currents in all sections are the same, and the uniformity of the circuit is ensured.
Alternatively, the first and second leads 110 and 120 are stacked on each other. The first lead 110 and the second lead 120 are located at different layers, so that wiring congestion of the two leads is avoided, and the design complexity is reduced.
Alternatively, the shape of each first lead 110 is different. On the premise that the wiring space is allowed, the first lead 110 is designed according to the size of the wiring space, so that the wiring space is fully utilized, and the space utilization rate is improved.
Referring to fig. 7, fig. 7 is a partial cross-sectional view taken at Q in fig. 1.
In some optional embodiments, the array substrate 11 further includes a gate metal layer 300 and a source-drain metal layer 400, and the third lead 130 is located on the gate metal layer 300; the source-drain metal layer 400 and the gate metal layer 300 are stacked and insulated from each other, and the second and fourth leads 120 and 140 are located on the source-drain metal layer 400.
In these alternative embodiments, the second lead 120 and the fourth lead 140 are disposed in the same layer, and the second lead 120 and the fourth lead 140 can be simultaneously manufactured, thereby simplifying the manufacturing process. The third lead 130 and the second lead 120 are arranged in different layers, so that the wiring congestion between the third lead and the second lead is avoided, and the design complexity is reduced.
Optionally, the source-drain metal layer 400 is directly laid on the conductor layer where the first lead 110 is located, so that the second lead 120 located in the source-drain metal layer 400 is directly connected with the first lead 110, resistance fluctuation caused by a via hole existing between the first lead 110 and the second lead 120 is avoided, and stability of overall impedance of the line is ensured.
Optionally, the thickness of the source-drain metal layer 400 where the second lead 120 is located is greater than that of the conductor layer where the first lead 110 is located, so that the possibility of wire breakage between the first lead 110 and the second lead 120 is reduced, and the stability of the circuit is ensured.
An embodiment of the second aspect of the present invention further provides a display panel 10, including the array substrate 11 of any of the embodiments of the first aspect. The display panel 10 may be an Organic Light Emitting Diode (OLED) display panel 10. Since the display panel 10 provided in the embodiment of the second aspect of the present invention includes the array substrate 11 of any one of the embodiments of the first aspect, the display panel 10 provided in the embodiment of the second aspect of the present invention has the beneficial effects of the array substrate 11 of any one of the embodiments of the first aspect, and details thereof are not repeated herein.
Embodiments of the third aspect of the present invention also provide a display device comprising the display panel 10 of the embodiment of the second aspect. Since the display device provided by the embodiment of the third aspect of the present invention includes the display panel 10 of the embodiment of the second aspect, the display device provided by the embodiment of the third aspect of the present invention has the beneficial effects of the display panel 10 of the embodiment of the second aspect, and details are not repeated here.
The display device in the embodiment of the present invention includes, but is not limited to, a mobile phone, a Personal Digital Assistant (PDA), a tablet computer, an electronic book, a television, a door lock, a smart phone, a console, and other devices having a display function.
Referring to fig. 8, fig. 8 is a schematic flow chart illustrating a manufacturing method of an array substrate 11 according to an embodiment of the present disclosure. The array substrate 11 may be the array substrate 11 provided in any of the above embodiments of the first aspect.
Referring to fig. 8 and the array substrate 11 shown in fig. 1 to 7, a method for manufacturing the array substrate 11 includes:
step S01: an electrostatic discharge assembly 100 is prepared, the electrostatic discharge assembly 100 including a plurality of electrostatic discharge blocks arranged at intervals.
Step S02: preparing a conductor material layer, and performing patterning to obtain a first lead 110, wherein one end of the first lead 110 is connected to at least one electrostatic discharge block.
Step S03: preparing a metal material layer on one side of the conductor material layer, and performing patterning to obtain a second lead 120, where the second lead 120 is connected to one end of the first lead 110 far away from the electrostatic discharge block, and the impedance of the second lead 120 is smaller than that of the first lead 110.
In the method for manufacturing the array substrate 11 according to the embodiment of the present application, first, the electrostatic discharge assembly 100 is manufactured through step S01, where the electrostatic discharge assembly 100 includes a plurality of electrostatic discharge blocks arranged at intervals, and the plurality of electrostatic discharge blocks are arranged to implement electrostatic protection on the array substrate 11. Then, the first lead 110 is prepared through step S02, and one end of the first lead 110 is connected to at least one electrostatic discharge block. Finally, the second lead 120 is prepared through step S03, one end of the first lead 110 is connected to at least one electrostatic discharge block, and the first lead 110 connects the electrostatic discharge block with the second lead 120, so that the electrostatic discharge block is conducted with the second lead 120 through the first lead 110. The second leg 120 impedance is less than the first leg 110 impedance, increasing the overall line resistance. The first lead 110 with a large impedance is used to connect the fast electrostatic discharge and the second lead 120 to reduce the current in the circuit and avoid the display panel 10 from turning green due to an excessive current.
In accordance with the embodiments described herein above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (18)
1. An array substrate, comprising:
the electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals;
one end of the first lead segment is connected to at least one electrostatic discharge block;
and the second lead is connected to one end, far away from the electrostatic discharge block, of the first lead, and the impedance of the second lead is smaller than that of the first lead.
2. The array substrate of claim 1, further comprising a third lead and a fourth lead, wherein the plurality of electrostatic discharge blocks comprises a first electrostatic discharge block and a second electrostatic discharge block, the first electrostatic discharge block is connected to the second lead through the first lead, and the second lead is connected to the third lead through a via hole;
the second electrostatic discharge block is connected to the fourth lead, and the fourth lead and the third lead are arranged in different layers.
3. The array substrate of claim 2, wherein the second lead and the fourth lead are disposed in the same layer and are made of the same material.
4. The array substrate of claim 2, wherein the third lead is located on a side of the electrostatic discharge block in the first direction, and the first electrostatic discharge block is located on a side of the second electrostatic discharge block facing the third lead.
5. The array substrate of claim 4, wherein the first electrostatic discharge blocks are spaced along the second direction, the second electrostatic discharge blocks are spaced along the second direction, and the first electrostatic discharge blocks are located on a side of the second electrostatic discharge blocks facing the third lead in the first direction.
6. The array substrate of claim 3, wherein the second lead comprises a first segment and a second segment, the first segment is located at one side of the first electrostatic discharge block in the second direction, the second segment is connected to the first lead and extends away from the first electrostatic discharge block in the first direction, the second segment extends obliquely toward the electrostatic discharge block in the second direction, the first lead is connected to one side of the first electrostatic discharge block in the first direction, and the first lead is connected between the second segment and the first electrostatic discharge block.
7. The array substrate of claim 6, wherein each of the second segments has an equal angle with the second direction.
8. The array substrate of claim 2, wherein the first lead extends along the first direction.
9. The array substrate of claim 2, wherein the first lead is a zigzag or serpentine extending along a meandering path.
10. The array substrate of claim 2, wherein a connection point of the first lead and the second lead corresponding to the first electrostatic discharge blocks is located on a straight line extending in the second direction.
11. The array substrate of claim 10, wherein the distances between the adjacent connection points are all equal.
12. The array substrate of claim 10, wherein the first leads are identical in shape.
13. The array substrate of claim 10, wherein the total length of each of the first leads is the same.
14. The array substrate of claim 1, wherein the first lead and the second lead are stacked on top of each other.
15. The array substrate of claim 2, further comprising:
the third lead is positioned on the grid metal layer;
and the source and drain metal layers are stacked with the grid metal layer and are insulated from each other, and the second lead and the fourth lead are positioned on the source and drain metal layers.
16. A display panel comprising the array substrate according to any one of claims 1 to 15.
17. A display device characterized by comprising the display panel according to claim 16.
18. A preparation method of an array substrate is characterized by comprising the following steps:
preparing an electrostatic discharge assembly, wherein the electrostatic discharge assembly comprises a plurality of electrostatic discharge blocks which are arranged at intervals;
preparing a conductor material layer, and carrying out patterning treatment to obtain a first lead, wherein one end of the first lead segment is connected to at least one electrostatic discharge block;
preparing a metal material layer on one side of the conductor material layer, and carrying out patterning treatment to obtain a second lead, wherein the second lead is connected to one end, far away from the electrostatic discharge block, of the first lead, and the impedance of the second lead is smaller than that of the first lead.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024092510A1 (en) * | 2022-11-01 | 2024-05-10 | 京东方科技集团股份有限公司 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024092510A1 (en) * | 2022-11-01 | 2024-05-10 | 京东方科技集团股份有限公司 | Display panel and display device |
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