CN115062786A - Quantum bit mapping and quantum gate scheduling method for quantum computer - Google Patents

Quantum bit mapping and quantum gate scheduling method for quantum computer Download PDF

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CN115062786A
CN115062786A CN202210995617.6A CN202210995617A CN115062786A CN 115062786 A CN115062786 A CN 115062786A CN 202210995617 A CN202210995617 A CN 202210995617A CN 115062786 A CN115062786 A CN 115062786A
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CN115062786B (en
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张昱
李永尚
陈铭瑜
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University of Science and Technology of China USTC
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Abstract

The invention relates to a quantum bit mapping and quantum gate scheduling method for a quantum computer, which comprises the following steps: step S1, inputting quantum wire data; step S2, initializing a scheduling state in the computer; step S3, based on the quantum circuit, adopting a scheduling sequence optimization generation method to generate a scheduling sequence executed by the quantum gate in parallel; the quantum gate is used as scheduling granularity by adopting a heuristic scheduling mechanism, and the execution duration of the quantum gate is supported to be non-uniform and configurable; a heuristic greedy algorithm is constructed based on the evaluation of the cost function of the dispatchable gate, so that the problem of parallel scheduling of the quantum gates is solved quickly; a heuristic greedy algorithm is embedded into a Monte Carlo tree parallel search frame, and a better parallel scheduling result can be given; and step S4, running the quantum computation process in the quantum computer according to the generated scheduling sequence. The invention generates legal high-efficiency quantum gate scheduling sequence for gate-level quantum circuit to shorten the execution time of quantum circuit on quantum computer.

Description

Quantum bit mapping and quantum gate scheduling method for quantum computer
Technical Field
The invention relates to the field of quantum computers and scheduling and computing of quantum computing programs, in particular to a quantum bit mapping and quantum gate scheduling method for a neutral atom quantum computer.
Background
Quantum computers are computing devices that store and process quantum information based on the principle of quantum mechanics. Existing quantum computers can be implemented by optical means and the like.
In a quantum computer, where quantum computation processes are generally represented in the form of quantum wires, the present invention employs Directed Acyclic Graphs (DAG) to represent the quantum wires, fig. 1 illustrates an example of a DAG representation of four quantum gates, with the left side being a fragment of an OpenQASM program that contains four quantum gates, the right side being a corresponding DAG representation of the program, and in the right side DAG, each node represents a quantum gate, for example: directed edge<CX q 2 ,q 3 ,CX q 1 ,q 2 >And qubit q on the edge 2 Representing arc-head node CX q 1 ,q 2 Dependent on arc tail node CX q 2 ,q 3 Performing, edge-attached qubits q 2 The representation is a qubit that is shared by the corresponding two quantum gates.
At present and in the future, the quantum hardware in the period belongs to the NISQ era, and the quantum hardware in the period has a plurality of hardware limitations, less bit number, low fidelity of the calculation process and long coherence time. How to maximize the value of quantum computers in the NISQ era becomes an important research problem.
Quantum computers based on various physical systems exist, mainly including superconductors, ions, neutral atoms, silicon-based semiconductors, and the like.
Quantum hardware has some limitations and features, while quantum programs are hardware independent. Quantum programs are to be run on devices, need to be compiled into operations supported by hardware, and are optimized sufficiently to improve the running efficiency and fidelity. It is first converted into low-level quantum line through the front-end and hardware independent optimization process and then converted into hardware supported operation through the hardware dependent optimization process.
Both superconducting and neutral atom quantum computers possess qubit connectivity limitations that require a multi-bit gate to act on k qubits, which must be connected two by two.
The superconducting qubit connectivity is described by a qubit connectivity graphThere are edge-connected qubits that are connected. For NAQC, however, the maximum operating distance between qubits is typically setR b I.e. a qubit and its Euclidean distance smaller thanR b Are connected.
Current quantum computers do not satisfy qubit full connectivity, which means that any two qubits are connected. One common coping strategy for this is: for an input logic circuit, a compiler establishes and maintains a mapping relation from logic bits to physical bits in the execution process, a quantum gate in the logic circuit is called a working gate, the execution process of the quantum circuit is the alternate execution of the working gate and a SWAP gate, and when a certain working gate does not meet the quantum bit connection limit, the quantum bit mapping can be changed by executing a plurality of SWAP gates, so that the working gate meets the bit connectivity. The SWAP gate is able to change the qubit mapping because it can SWAP the states of the two physical bits it acts on, thus corresponding to swapping the mapping of the two physical bits to logical bits. We refer to the process of inserting SWAP gates into logic as qubit mapping.
Referring to fig. 2, an example of a superconducting Quantum Computer (QC) (direct connection between qubits in physical implementation) is shown:
FIG. 3 shows an example of a neutral superconducting quantum computer (maximum working distance of long-range link)R b =2)：
In the above-mentioned manner,Q i (q j )representing logical bitsq j Mapping to physical bitsQ i . The qubits in the logic circuit are all logic bits, CX is a two-bit gate, and if the qubits are three-bit gates or four-bit gates, the connection limit is satisfied by the pairwise distance of the qubits which are required to be acted by the logic circuit.
The neutral atom quantum computer has parallel limitation, and requires that any multi-control gate has a certain limitation area, and the gates with overlapped limitation areas can not be parallel. As shown in fig. 4, quantum gates CX Q2, Q3 cannot be executed in parallel with CX Q0, Q1. The restricted area is a physical area, and if the restricted area of a logic gate (working gate) is to be considered, the logic gate is converted into a corresponding physical gate according to the qubit mapping, and the restricted area of the corresponding physical gate is the restricted area of the logic gate.
The procedure for determining the restricted area is as follows: order tog.regRepresenting a multi-bit gategThe quantum gate's limiting radius is half the maximum distance of any two qubits it acts on, i.e.:
Figure 77099DEST_PATH_IMAGE001
function(s)dThe euclidean distances between two points in space are calculated,Q i .pos: physical bitQ i Position coordinates in space;
thengThe limiting regions of (a) are:
U Q g.reg∈ {p|d(p,Q.pos)≤r(g) P is a point in the restricted area, i.e. a point within the restricted area needs to be satisfiedd(p,Q.pos)≤r(g) I.e. p togThe distance of a certain quantum bit Q of the effect is not more thangThe limiting radius of (a); intuitively, the limited area takes the quantum bit of the gate effect as the center of a circle,r(g) Circles are drawn for the radii.
Disclosure of Invention
The invention provides a quantum bit mapping and quantum gate scheduling method adaptive to a neutral atom quantum computer, aiming at hardware constraints that connectivity of neutral atom quantum bits is based on long-range interaction of a Reedberg and quantum gates with overlapped limiting regions cannot be executed in parallel. It generates legal high-efficiency quantum gate scheduling sequence for input gate-level quantum circuit to shorten execution time of quantum circuit on neutral atom quantum computer. The heuristic scheduling mechanism provided by the invention takes the quantum gate as the scheduling granularity, and supports that the execution duration of the quantum gate is not uniform and configurable; a heuristic greedy algorithm constructed based on the proposed cost function for evaluating the dispatchable gate can solve the scheduling problem of the quantum gate more quickly; and a heuristic greedy algorithm is embedded into a further proposed Monte Carlo tree parallel search framework, so that a better parallel scheduling result can be given.
The technical scheme of the invention is as follows: a method of qubit mapping and quantum gate scheduling for a quantum computer, comprising the steps of:
step S1, inputting quantum wire data;
step S2, initializing a scheduling state in the computer;
step S3, based on the quantum circuit, adopting a scheduling sequence optimization generation method to generate a scheduling sequence executed by the quantum gate in parallel; the quantum gate is used as a scheduling granularity by adopting a heuristic scheduling mechanism, thereby meeting the quantum bit connectivity constraint (direct connection or long-range connection in a certain range), supporting the inconsistent and configurable execution duration of the quantum gate, and supporting the limit constraint on the quantum bit operation of the peripheral area of the multi-bit quantum gate during the execution period; a heuristic greedy algorithm is constructed based on the proposed cost function for evaluating the dispatchable gates, so that the problem of parallel scheduling of the quantum gates is solved quickly; a heuristic greedy algorithm is embedded into a Monte Carlo tree parallel search frame, and a better parallel scheduling result can be given;
and step S4, running the quantum computation process in the quantum computer according to the generated scheduling sequence.
Further, in step S3, generating the scheduling sequence by using a scheduling sequence optimization generation method means that a heuristic greedy algorithm is used to generate the scheduling sequence, and the method specifically includes:
step 311, assigning weights to the quantum gates in the quantum wires;
step 312, generating a current dispatchable gate set according to the current dispatching state, adding quantum gates which are not predecessors in a non-dispatched line and meet connection restrictions into the dispatchable gate set, adding all SWAP gates meeting bit connection restrictions into the dispatchable gate set, and screening the SWAP gates;
step 313, selecting a schedulable gate with the minimum cost according to the cost function, and recording the schedulable gate as a target scheduling gate;
step 314, setting the starting execution time of the target scheduling gate as the time for releasing all the required computing resources, adding the target scheduling gate and the starting execution time thereof into the scheduling sequence, updating the time for releasing the computing resources in the current scheduling state, deleting the target scheduling gate from a non-scheduling line in the current scheduling state if the target scheduling gate is a working gate, and updating the qubit mapping in the current scheduling state if the target scheduling gate is a SWAP gate;
step 315, if the current scheduling state is the termination state, outputting the generated scheduling sequence, otherwise, returning to step 311.
Further, generating the scheduling sequence by using a scheduling sequence optimization generation method, which means generating the scheduling sequence by using a monte carlo tree search algorithm to generate the scheduling sequence, specifically includes:
step 321, constructing a root node according to the initial scheduling state;
step 322, if the scheduling state of the root node is the termination state, outputting the scheduling sequence of the running state of the root node, and ending; otherwise, the iteration times are reset to 0;
step 323, calling a selection function to select a plurality of nodes;
step 324, executing a simulation function to simulate in parallel the plurality of nodes selected by the selection function;
step 325, executing a return function, updating the attribute values of all nodes in the search tree, increasing the iteration times, and turning to step 326 if the iteration times exceed a preset constant; otherwise go to step 323;
and step 326, executing a decision function to update the root node of the search tree, then entering the next iteration, and turning to step 322.
Further, the method adapts both superconducting quantum computers and neutral atomic quantum computers.
The invention relates to a quantum bit mapping and quantum gate scheduling method adaptive to a neutral atom quantum computer, which generates a legal efficient quantum gate scheduling sequence for an input gate-level quantum circuit so as to shorten the execution time of the quantum circuit on the neutral atom quantum computer. The heuristic scheduling mechanism provided by the invention takes the quantum gate as the scheduling granularity, and supports that the execution duration of the quantum gate is not uniform and configurable; a heuristic greedy algorithm constructed based on the proposed cost function for evaluating the dispatchable gate can solve the quantum gate dispatching problem quickly; and a heuristic greedy algorithm is embedded into a further proposed Monte Carlo tree parallel search framework, so that a better parallel scheduling result can be given.
Drawings
FIG. 1: examples of DAG representations of quantum wires;
FIG. 2: examples of bit-connection limitations for superconducting quantum computers;
FIG. 3: bit-connected constrained examples of neutral atomic quantum computers;
FIG. 4: examples of confinement regions for quantum gates of neutral atomic quantum computers;
FIG. 5: examples of weighted quantum wires;
FIG. 6: the Heuristic Greedy Algorithm (HGA) process of the invention;
FIG. 7: a flow representing a Monte Carlo tree search framework;
FIG. 8: a selection functionSelectionExamples of execution.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
According to an embodiment of the present invention, a method for quantum bit mapping and quantum gate scheduling for a quantum computer is provided, which includes the following steps:
step S1, inputting quantum wire data;
step S2, initializing a scheduling state in the computer;
step S3, based on the quantum circuit, adopting a scheduling sequence optimization generation method to generate a scheduling sequence executed by the quantum gate in parallel; the quantum gate is used as a scheduling granularity by adopting a heuristic scheduling mechanism, thereby meeting the quantum bit connectivity constraint (direct connection or long-range connection in a certain range), supporting the inconsistent and configurable execution duration of the quantum gate, and supporting the limit constraint on the quantum bit operation of the peripheral area of the multi-bit quantum gate during the execution period; a heuristic greedy algorithm is constructed based on the proposed cost function for evaluating the dispatchable gates, so that the problem of parallel scheduling of the quantum gates is solved quickly; a heuristic greedy algorithm is embedded into a Monte Carlo tree parallel search frame, and a better parallel scheduling result can be given;
and step S4, running the quantum computation process in the quantum computer according to the generated scheduling sequence.
The above method will be described in detail below.
According to the embodiment of the invention, the quantum bit mapping and quantum gate scheduling method provided by the invention is simultaneously adapted to superconducting QC and neutral atom QC, the following symbols are introduced for convenient description, and the specific definitions of the following symbols are different for the two QCs:
Figure 259819DEST_PATH_IMAGE002
: representing a set of physical qubits (physical bits for short) owned in a quantum computer,
Figure 822912DEST_PATH_IMAGE003
；
Q i .pos: physical bitQ i Position coordinates in space, which are variables introduced for neutral atom QC;
Figure 483700DEST_PATH_IMAGE004
: representing a quantum bit connected graph, wherein nodes are physical bits, edges among the nodes are undirected, and all the edges are 1; edge (Q,Q ' )∈EE is the set of all edges, if and only ifQAndQ ' satisfy the requirement ofQubit connectivity. The superconducting qubit connectivity graph is directly given by the hardware configuration; for NAQC, a quantum bit connected graph, edge (b) and edge (c) need to be constructed according to the coordinates of all physical bitsQ,Q ' )∈EIf and only if qubitsQ,Q ' Has Euclidean distance of less than or equal to the maximum action distanceR b ；
D: mapping
Figure 829231DEST_PATH_IMAGE005
And R is a real number set and represents a mapping table of the distance between every two quantum bits. For the case of a superconducting QC, the,D(Q,Q ' ) Representing physical bitsQAndQ ' shortest path distance on a bit connectivity graph; in the case of the neutral atom QC,D(Q,Q ' ) Representing physical bitsQAndQ ' euclidean distance in space;
P: computing a set of resources; for the case of a superconducting QC, the,
Figure 917272DEST_PATH_IMAGE006
(ii) a For neutral atom QC, a set of uniform sampling points representing the qubit distribution space is satisfied
Figure 449885DEST_PATH_IMAGE007
,Q.pos∈P(Here, theQ.posRepresenting physical qubitsQThe coordinates of the dots) the quantum bits may be arranged in a 1D, 2D or 3D geometry; for the neutral atom QC, because the quantum gate of the neutral atom QC has a limited region (mentioned above), the invention uniformly samples a group of point sets in the region of quantum bit distribution and uses the point sets as a computing resource, and if the limited region of a certain gate contains a certain point of the point sets, the invention is called that the gate is used for the point. If the restricted areas of two quantum gates overlap, they must share one or more points, and the present invention uses the point set as an exclusive computational resource to ensure that gates with overlapping restricted areas do not execute in parallel.
z(g): the computational resources required to implement quantum gates: (PA subset of (a); for superconducting QC, quantum gates are representedgA set of contributing physical bits; for neutral atom QC, representationPMiddle falling type quantum doorgThe set of points within the restricted area.
g.τ: representing quantum gatesgThe execution duration of the invention adopts cycle as unit time of the quantum computer, and the execution duration of the quantum gate is integral multiple of the cycle;
π: a mapping table of logical bits to physical bits,π(q) Representing logical bitsqA corresponding physical bit;
I: array of elementsI=[(g 0 ,t 0 ),(g 1 ,t 1 ),…,(g l−1 ,t l−1 )]A legal scheduling sequence representing a quantum wire, (g i ,t i ) Representing quantum gatesg i In thatt i Starting execution at a moment and for any two quantum gatesg i ,g j If there is an intersection between their computing resources, they cannot be executed concurrently, that is, they satisfy:
Figure 914364DEST_PATH_IMAGE008
,
then:t i +g i .τ<t j ||t j +g j .τ<t i ；
wherein, | | represents a logical or; wherein ∀ is a mathematical full term meaning "for arbitrary";
H: mapping of computing resources to times at which they are released
Figure 599555DEST_PATH_IMAGE009
，
Figure 124077DEST_PATH_IMAGE010
Representing a set of natural numbers, is an auxiliary data structure maintained during scheduling,H(p) Representing resourcespThe time at which it is released;pbelong toPAnd belong to the quantum gategThe computational resources that are used are,Pis a collection of computing resources;
according to the embodiment of the invention, for a quantum gate scheduling problem, the input and output are specifically:
the inputs to the qubit mapping and quantum gate scheduling problem are: quantum bit collection
Figure 143986DEST_PATH_IMAGE002
Quantum bit connectivity mapGQuantum bit distance meterDComputing resources of quantum computersPA logic circuitC init Initial qubit mappingπ init 。
The output is: a legal scheduling sequenceI out 。
According to the embodiment of the present invention, the scheduling mechanism is specifically as follows:
scheduling state
Figure 412156DEST_PATH_IMAGE011
Wherein C: the lines that are not to be scheduled,π: qubit mapping, I: generated scheduling sequence, H: calculating a time at which the resource is released;
in the scheduling process, an initial runtime state needs to be constructed first
Figure 201120DEST_PATH_IMAGE012
WhereinI init =Ø,∀p∈P,H init (p) And =0. C: the lines that are not to be scheduled,π: qubit mapping, I: generated scheduling sequence, H: calculating the time when the resource is released, adding an init subscript to represent the initial state;
end state
Figure 411391DEST_PATH_IMAGE013
There may be more than one termination state, one state being a termination state and only ifC end =The end subscript indicates the state at termination;
order to
Figure 918595DEST_PATH_IMAGE014
A set of dispatchable gates is represented,
Figure 459298DEST_PATH_IMAGE015
，
Figure 368348DEST_PATH_IMAGE016
a gate indicating that there is no front-end node in line C that is not scheduled and that satisfies the bit connection constraint,
Figure 969094DEST_PATH_IMAGE017
representing a set of optional SWAP gates.
According to an embodiment of the invention, the scheduler selects one schedulable gate at a timegThen in the statesNext according to the state transfer functiontransition(s,g) A state transition function, the state transition function being described as:
1. if it is notgIs a working door, willgDeleted from line C not scheduled;
2. if it is notgIs a SWAP gate, switchgA mapping value of the quantum bit of the role;
3. computinggStart execution time of
Figure 229174DEST_PATH_IMAGE018
；H(p) Is the time at which the computing resource p is released;
4. will (a) tog,t(s,g) Tuple joins the scheduling sequence;
5. updatingHWhere H is a whole, H (p) is an entry of H, updating H (p) and thus H, ∀p∈z(g),H(p)=t(s,g)+τ(g) I.e. due to scheduling of another oneAnd the release time of the resources occupied by the gate is updated to the end time of the gate, namely the starting execution time + the duration.
Screening of selectable SWAP gate sets according to embodiments of the present invention
Figure 573568DEST_PATH_IMAGE019
The method specifically comprises the following steps:
the quantum gate in the quantum wire C is divided into three layers, the first layerL 1 : all predecessor nodes and gates that satisfy bit connectivity by themselves; second layerL 2 : gates that all predecessor nodes satisfy, but do not satisfy, bit connectivity by themselves; third layerL 3 : other doors.
Defining quantum gategIn the quantum bit mapping ofπThe distance in time is defined as:
Figure 87857DEST_PATH_IMAGE020
setting an optional SWAP gate to map the current quantum bitπIs converted intoπ ' Then, it must satisfy:
1、∀g∈L 1 ,distance(g,π ' )≤distance(g,π)
2、∃g∈L 2 ,distance(g,π ' )<distance(g,π)
according to an embodiment of the present invention, the quantum gate is a weighted quantum gate, and specifically, the weighted quantum gate includes:
giving quantum gate weight in quantum circuit, quantum gategWeight of (2)g.wIs defined as:
Figure 125083DEST_PATH_IMAGE021
where max is taken to mean the maximum value;
succ(g) In the representation linegIs directly followed.
Referring to FIG. 5, assume thatHThe duration of the door is 1cThe duration of the C not gate is 2 cycles.
The weights of the working gates in the line are fixed, but during the scheduling process, the optional SWAP gates are weighted to characterize their contribution. Door with SWAPsgMapping the current quantumπIs converted intoπ ' ，sgThe weight of (d) is defined as:
Figure 341301DEST_PATH_IMAGE022
distance(π,g) Indicating that quantum gate g is mapped in qubits toπThe distance of the time of day is,distance(π ' ,g) Indicating that quantum gate g is mapped in qubits toπ ' The distance of the quantum gate is shortened by the subtraction of the two quantum gates after the mapping is changed by the SWAP gate, and the quantum gate can be regarded as the contribution of the SWAP gate after being multiplied by the weight of the quantum gate;
heuristic greedy algorithm
The algorithm is in an initial states init Initially, a least expensive dispatchable gate is selected at each step and the state is transferred until the termination state is reached. Dispatchable doorgThe cost in the current scheduling state s is calculated by a cost function, which is defined as:
cost(s,g)=β×t(s,g)−α(g)×g.w
wherein, the first and the second end of the pipe are connected with each other,β=1000 is a constant much greater than 1, which is a priority for gates that start executing early. If it is notgIs a working door, and the door is a working door,α(g) = 1; if not, then the mobile terminal can be switched to the normal mode,α(g) =0.001 is a constant much less than 1, in order to ensure that the working gate takes precedence over the SWAP gate.
According to an embodiment of the present invention, in step S3, the generating method by optimizing the scheduling sequence is a method for generating the scheduling sequence by using a heuristic greedy algorithm, and specifically includes:
311, giving weight to each quantum gate in the quantum circuit;
step 312, generating a current dispatchable gate set according to the current dispatching state, adding quantum gates which are not predecessors in a non-dispatched line and meet connection restrictions into the dispatchable gate set, adding all SWAP gates meeting bit connection restrictions into the dispatchable gate set, and screening the SWAP gates;
313, selecting a schedulable gate with the minimum cost according to the cost function, and recording the schedulable gate as a target scheduling gate;
step 314, setting the starting execution time of the target scheduling gate as the time when all the required computing resources are released, adding the target scheduling gate and the starting execution time thereof into the scheduling sequence, updating the time when the computing resources in the current scheduling state are released, if the target scheduling gate is a working gate, deleting the target scheduling gate from the non-scheduling line in the current scheduling state, and if the target scheduling gate is a SWAP gate, updating the qubit mapping in the current scheduling state;
step 315, if the current scheduling state is the termination state, outputting the generated scheduling sequence, otherwise, returning to step 311.
As shown in fig. 6, according to an embodiment of the present invention, the Heuristic Greedy Algorithm (HGA) process may be implemented as follows:
step 1, giving weight to each quantum gate in a quantum circuit;
step 2, according to the current scheduling state
Figure 489385DEST_PATH_IMAGE023
Generating a current dispatchable gate set, adding gates which are not predecessors in a non-dispatched line and meet connection limitation into the dispatchable gate set, adding all SWAP gates meeting bit connection limitation into the dispatchable gate set, and screening the SWAP gates according to the steps;
step 3, selecting the schedulable door with the minimum cost according to the cost functiongAnd is marked as a target dispatching gate;
step 4, transferring the state, limiting the parallelism, and executing the target scheduling gate after the required computing resource is released, so that the starting execution time of the target scheduling gatet(s,g) To calculate the time at which the resources are released,
Figure 373028DEST_PATH_IMAGE024
in this formula: z (g) represents the computational resources required for g, and H (p) is the release time for p. Adding a target scheduling gate and the starting execution time thereof into a scheduling sequence, deleting the target scheduling gate from an unscheduled line in the current scheduling state if the target scheduling gate is a working gate, updating the quantum bit mapping of the current scheduling state if the target scheduling gate is an SWAP gate, and updating the released time of the computational resource in the current scheduling state;
step 5, if the current scheduling statesIs in a certain termination state, outputIOtherwise, returning to the step 1;
according to another embodiment of the present invention, in step 3, a scheduling sequence optimization generation method is adopted, or a monte carlo tree search algorithm may be used to generate a scheduling sequence to generate the scheduling sequence, and a Heuristic Greedy Algorithm (HGA) of the present invention is embedded in a Monte Carlo Tree Search (MCTS) framework to implement secondary optimization, where the HGA is included in the MCTS, and both of the HGA and the MCTS can generate the scheduling sequence, but the MCTS embedded in the HGA can obtain a better scheduling sequence, and the specific process may be implemented as follows:
step 321, constructing a root node according to the initial scheduling state;
step 322, if the scheduling state of the root node is the termination state, outputting the scheduling sequence of the running state of the root node, and ending; otherwise, the iteration times are reset to 0;
step 323, calling a selection function to select a plurality of nodes;
step 324, executing a simulation function to simulate the plurality of nodes selected by the selection function in parallel;
step 325, executing a return function, updating the attribute values of all nodes in the search tree, increasing the iteration times, and turning to step 326 if the iteration times exceed a preset constant; otherwise go to step 323;
step 326, executing the decision function to update the root node of the search tree, and then entering the next iteration to go to step 322.
Further, the method adapts both superconducting quantum computers and neutral atomic quantum computers.
In the Monte Carlo tree search algorithm, firstly, the attributes of the search nodes defined by the invention are as follows:
s: scheduling status represented by the node
Figure 581155DEST_PATH_IMAGE025
；
val: the value of the node;
N: the number of times the node is explored;
imr: immediate reporting of the node;
child: a set of child nodes of the node;
ns: an auxiliary variable representing the number of simulation opportunities acquired;
the main function of the Monte Carlo tree search algorithm is realized as follows:
step 1, according to the initial states init Construction root noder,r.s=s init ,r.val=0,r.N=0,r.imr=0, r.child=The middle section is moved forwards; r represents the root node of the monte carlo search tree,. s: the scheduling status represented by the node; val: value of the node,. imr: immediate revenue for the node; child: a set of child nodes of the node; value of any node n
Figure 284669DEST_PATH_IMAGE026
；
Step 2, ifr.sOutputting a scheduling sequence of the running state of the root node for the termination stater.s.IAnd ending; otherwise, the iteration times are reset to 0;
step 3, calling the selection functionSelection(r,m s ) To selectm s A node, whereinm s Is a preset positive integer constant;
step 4, executing simulation functionSimulation() To simulate in parallel the execution of a selection functionSelectionSelected ofm s A node;
step 5, executing the return functionBackpropagation() Updating the attribute values of all nodes in the search tree;
step 6, iteration times +1, if the iteration times exceed the preset constantm i Go to step 6; otherwise, turning to the step 3;
step 7, executing decision functionDecision() Updating the root node of the search tree, then entering the next iteration, and turning to the step 2;
referring to fig. 7, a flow of the monte carlo tree search framework is shown, and each function module in the framework will be described separately.
In the Monte Carlo tree searching framework, through improvement, the selection module selects a plurality of nodes to be simulated each time, so that the efficiency of parallel computing can be improved; secondly, the heuristic greedy algorithm is called in a simulation module, so that a better scheduling sequence can be obtained;
according to an embodiment of the present invention, the selection function isSelection(n,m s ) Is defined as follows:
the upper confidence interval UCT used by the selection function is formulated as follows:
Figure 488642DEST_PATH_IMAGE027
na certain search node is represented and,Jis a constant value which is preset and is,n ' a sub-node of n is represented,n c representing the selected child node;
according to one embodiment of the invention, selectingSelectionThe purpose of the function is to be based on the UCT formulam s Individual simulation opportunity distribution to nodesnAnd the child nodes thereof, and adding the nodes which obtain the simulation opportunity into the node list to be simulated, which comprises the following specific steps:
step 1, ifn.N=0, descriptionnHas not yet been simulated, willnAdding the list of the nodes to be simulated, m s 1, consuming 1 simulation opportunity, ifm s =0, function returns;
step 2, ifn.child=In other words, the explanation n is not expanded, the child nodes of the explanation n which is not expanded are not considered in the searching process, the child node set is empty, and the expansion is to take the child nodes into the subsequent searching range and add the child nodes into the child node setn.childThen, call expansion function expansion (n);
step 3, ifm s >0, if the simulation opportunity is not distributed, turning to the step 4; otherwise go to step 5;
step 4, selecting a child node of n according to UCT formulan ' Distributing a simulation opportunity ton ' Number of times the node was exploredn.N Plus 1, the number of simulation opportunities obtained by the child node in the current round of selectionn ' . ns Plus 1, the number of remaining simulation opportunitiesm s Minus 1, and then go to step 3;
step 5, ∀n ' ∈n.childIf, ifn ' .ns>0, creating a thread, recursively calling a selection functionSelection(n ' , n ' .ns) Returning the function;
FIG. 8 is a selection functionSelectionExample of execution:
“sel”:Selection,“exp”:Expansion,“sim”:Simulationthe number "x/y" in a node represents the value of the node respectivelyvalAnd the number of times that a subtree rooted at the node is exploredN. T1-T6 are 6 threads, "SO" indicates: and (5) simulating the opportunity. The T1 thread distributes three simulation opportunities to its children and then creates two threads T2, T3. The T2 thread executes becausen 2 The number of times (1) explored is greater than 0, indicating that it has been simulated, so it does not consume simulation opportunities, butn 2 Is not expanded so it will execute firstExpansion(n 2 ) Then will ben 2 The resulting simulation opportunity is distributed to its child nodes, eventually creating T4. T3 is the same flow, all consuming oneThe nodes of the simulation opportunity are selected as the nodes to be simulated.
Spreading functionExpansion(n) Adding the child nodes of the node n into the child node set of the node n, thereby expanding the search range, wherein the search range only comprises the root node at first, and the search range is expanded continuously along with the expansion, the branch and the leaf are scattered, and the search range is defined as follows:
for then.sEach dispatchable door in a stategThe implementation process is as follows:
step 1, constructing a noden ' ；
Step 2,n ' .s=Transition(n.s,g) State of child noden ' .sIs the state of the parent noden.sPassing through the dispatching gategThen converting the obtained state;
step 3, ifgIs a working door, and the door is a working door,n ' .imr=g.wotherwise, otherwisen ' .imr=0；
Step 4, mixingn ' Adding inton.child；
According to one embodiment of the invention, the function is modeledSimulation(): and the simulation function sets the value of the simulated node as the benefit of the simulation scheduling by the simulation scheduling, takes the scheduling state represented by the simulated node as a simulation starting state, and simulates and schedules the unscheduled line by calling the heuristic greedy algorithm until the simulation cost exceeds a certain preset value, wherein the simulation cost is the increment of the execution time of the scheduling sequence in the simulation state relative to the execution time of the scheduling sequence of the root node. The final simulation benefit is the sum of the weights of the work gates scheduled in the simulation scheduling process.
For each node in the list of nodes to be simulatednExecuting the following steps:
step 1,value=0，valueReturn values for simulation execution, i.e. gains for simulation scheduling;
step 2, if the execution duration of the scheduling sequence of the state is simulated>Execution duration of scheduling sequence of root node +h grow The value of n.val is assigned as the value of value, and the function returns;otherwise, turning to the step 3;
step 3, generating a simulation scheduling statesAnd screening SWAP gates in the schedulable gates;
step 4, selecting the schedulable door with the minimum cost according to the cost functiongIf, ifgIs a working door, forvalueIncrease in value ofg.wAs a new value;
step 5, according to the state transfer functiontransition(s,g) Transferring the state, and turning to the step 2;
wherein the content of the first and second substances,h grow is a preset constant;
according to one embodiment of the invention, the passback functionBackpropagation() For updating the value of nodes within the search scope; specifically, all nodes in the search tree are traversed, and their val attributes are updated according to the following formula:
Figure 226790DEST_PATH_IMAGE028
according to one embodiment of the invention, the decision functionDecision() The child node used for setting the maximum value of the root node as a new root node; the method comprises the following specific steps:
ris the current root node of the current node,
Figure 605819DEST_PATH_IMAGE029
will ber new Is set as a new root node of the network,r new is thatrThe child node with the greatest value.
To sum up, the invention provides a quantum bit mapping and quantum gate scheduling method, which can be written in computer languages such as C or C + + and the like during specific implementation, can be operated on a common computer, converts a quantum program into a scheduling sequence, and then the scheduling sequence can be operated on a superconducting and neutral atom quantum computer;
according to an experimental embodiment of the present invention, large and small quantum line data were selected, respectively, and the scheduling method of the present invention was tested. Firstly, a group of large lines including algebraic logic lines, recessive significance bit lines, Hamming coding lines and the like are selected from RevLib, the number of logic bits is 23-112, and the large lines include single-bit gates and 2, 3, 4 and 5-bit gates; the results are shown in table 1:
table 1: algorithm operation comparison result in large-scale line
Figure 796629DEST_PATH_IMAGE030
A set of mini-wires was selected from the qisskit lib: the number of logic bits is 4-16, and comprises a single-bit gate and a 2-bit gate, compared with the current only quantum bit mapping and quantum gate scheduling algorithm, LookAhead Compiler, proposed by Baker et al for neutral atom QC, the results are shown in table 2:
table 2: algorithm operation comparison result in small line
Figure 552095DEST_PATH_IMAGE031
The execution duration unit of the table is cycle number;
Q l a number of logical bits;
G n the number of quantum gates;
T la the cycle number of the scheduling sequence generated by the LookAhead;
T g the cycle number of a scheduling sequence generated by a heuristic greedy algorithm;
T m the cycle number of the generated scheduling sequence is searched by the Monte Carlo tree;
Figure 879172DEST_PATH_IMAGE032
acceleration ratio of a heuristic greedy algorithm relative to the LookAhead Compiler; monte Carlo Tree search vs. heuristic greedyAcceleration ratio of the cardiac algorithm.
According to the table 1, the heuristic greedy algorithm can shorten the execution time of a large-scale line test set by 32% relative to a LookAhead Compiler, and the Monte Carlo search tree algorithm can realize a secondary optimization rate of 16% on the basis; according to the table 2, the heuristic greedy algorithm of the invention can shorten the execution time of the small line test set by 9% compared with the lookup ahead Compiler, and the Monte Carlo search tree algorithm of the invention can realize a secondary optimization rate of 5% on the basis.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but various changes may be apparent to those skilled in the art, and it is intended that all inventive concepts utilizing the inventive concepts set forth herein be protected without departing from the spirit and scope of the present invention as defined and limited by the appended claims.

Claims (4)

1. A method for quantum bit mapping and quantum gate scheduling for a quantum computer, comprising the steps of:
step S1, inputting quantum wire data;
step S2, initializing a scheduling state in the computer;
step S3, generating a scheduling sequence for the quantum gate to execute in parallel by using a scheduling sequence optimization generation method based on the quantum wire, including: generating a scheduling sequence by adopting a heuristic greedy algorithm and generating the scheduling sequence by adopting a Monte Carlo tree search algorithm, wherein the heuristic greedy algorithm adopts a heuristic scheduling mechanism, takes a quantum gate as a scheduling granularity, meets the quantum bit connectivity constraint, supports that the execution duration of the quantum gate is not uniform and configurable, and supports the limit constraint on the quantum bit operation of a peripheral area of the multi-bit quantum gate during the execution period; the heuristic greedy algorithm is constructed based on the cost function of the dispatchable gate;
and step S4, running the quantum computation process in the quantum computer according to the generated scheduling sequence.
2. The method of claim 1, wherein the quantum-bit mapping and quantum-gate scheduling method for quantum computer,
in step S3, generating the scheduling sequence executed in parallel by the quantum gate by using the scheduling sequence optimization generation method means generating the scheduling sequence by using a heuristic greedy algorithm, and specifically includes:
step 311, assigning weights to the quantum gates in the quantum wires;
step 312, generating a current dispatchable gate set according to the current dispatching state, adding quantum gates which are not predecessors in a non-dispatched line and meet connection restrictions into the dispatchable gate set, adding all SWAP gates meeting bit connection restrictions into the dispatchable gate set, and screening the SWAP gates;
313, selecting a schedulable gate with the minimum cost according to the cost function, and recording the schedulable gate as a target scheduling gate;
step 314, setting the starting execution time of the target scheduling gate as the time when all the required computing resources are released, adding the target scheduling gate and the starting execution time thereof into the scheduling sequence, updating the time when the computing resources in the current scheduling state are released, if the target scheduling gate is a working gate, deleting the target scheduling gate from the non-scheduling line in the current scheduling state, and if the target scheduling gate is a SWAP gate, updating the qubit mapping in the current scheduling state;
step 315, if the current scheduling state is the termination state, outputting the generated scheduling sequence, otherwise, returning to step 311.
3. The method according to claim 1, wherein in step S3, the generating of the scheduling sequence for the parallel execution of the quantum gate by using the scheduling sequence optimization generation method means generating the scheduling sequence by using a monte carlo tree search algorithm, and specifically comprises:
step 321, constructing a root node according to the initial scheduling state;
step 322, if the scheduling state of the root node is the termination state, outputting the scheduling sequence of the scheduling state of the root node, and ending; otherwise, the iteration times are reset to 0;
step 323, calling a selection function to select a plurality of nodes;
step 324, executing a simulation function to simulate in parallel the plurality of nodes selected by the selection function;
step 325, executing a return function, updating the attribute values of all nodes in the search tree, increasing the iteration times, and turning to step 326 if the iteration times exceed a preset constant; otherwise go to step 323;
and step 326, executing a decision function to update the root node of the search tree, then entering the next iteration, and turning to step 322.
4. A method of qubit mapping and quantum gate scheduling for a quantum computer according to claim 1, wherein the method adapts a superconducting quantum computer and a neutral atomic quantum computer simultaneously.
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