CN115051704A - Phase locking method, device, equipment and storage medium - Google Patents
Phase locking method, device, equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The application discloses a phase locking method, a phase locking device, equipment and a storage medium, wherein the method comprises the following steps: acquiring the phase difference of an input signal and a feedback signal of the digital phase-locked loop; adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold; compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking.
Description
Technical Field
The embodiment of the application relates to the technical field of electronics, and relates to but is not limited to a phase locking method, a phase locking device, phase locking equipment and a storage medium.
Background
In a Time Division Duplex (TDD) System communication device, a 4G/5G indoor baseband processing Unit (BBU) device needs to be connected to a Global Positioning System (GPS) clock source for Time synchronization, so as to ensure that uplink and downlink timeslots of the System are aligned.
In the case of using a 1 second pulse (PPS) synchronization signal generated by a clock source such as a GPS, a Digital Phase-Locked Loop (DPLL) is usually used to perform frequency locking to generate a clock frequency point, Phase debounce and Phase locking required by a single board. Here, the DPLL is a phase-locked loop formed by digital signal processing technology and digital circuits.
In the case of phase locking using a DPLL, the DPLL has a long locking time (the bandwidth of the loop filter is usually at least smaller than 1/20 of the frequency of the phase detector, tracks 1PPS, the bandwidth of the loop filter cannot be greater than 50mH, and the loop bandwidth is small and tracks slowly) because a Numerically Controlled Oscillator (NCO) in the DPLL freely oscillates to generate an initial 1PPS signal or a signal without 1PPS signal which is lost for a long time, and there is a large phase difference with 1PPS input by the signal source. Thus, the user's requirements for the use of the DPLL output clock cannot be met.
In the prior art, the input signal at the input end of the DPLL is a 1PPS signal rising edge serving as a reset signal, and the output signal and the feedback signal of the DPLL are reset simultaneously, so that the phase alignment of the output signal and the 1PPS of the input signal is realized, but during the reset period, the output end does not output 1PPS, and the problem of lost seconds exists.
Disclosure of Invention
In view of the above, embodiments of the present application provide a phase locking method, apparatus, device and storage medium.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a phase locking method, where the method includes: acquiring the phase difference of an input signal and a feedback signal of the digital phase-locked loop; adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold; compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking.
In a second aspect, an embodiment of the present application provides a phase locking device, including: the acquisition module is used for acquiring the phase difference between the input signal and the feedback signal of the digital phase-locked loop; a first adjusting module, configured to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold; and the compensation module is used for compensating the output signal of the digital phase-locked loop based on the phase difference so as to realize phase locking.
In a third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, where the memory stores a computer program that is executable on the processor, and the processor implements the above method when executing the program.
In a fourth aspect, embodiments of the present application provide a storage medium storing executable instructions for causing a processor to implement the above method when executed.
In the embodiment of the application, firstly, the phase difference between the input signal and the feedback signal of the digital phase-locked loop is obtained; then, in a case where it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal; compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking. In this way, in the case that the phase difference is determined to be greater than the phase difference threshold, the direct compensation of the phase difference in the digital domain based on the phase difference of the input signal and the feedback signal can be achieved, and the phase can be locked quickly.
Drawings
Fig. 1 is a schematic diagram of a DPLL architecture according to an embodiment of the present application;
fig. 2 is a schematic flowchart illustrating an implementation process of a phase locking method according to an embodiment of the present application;
fig. 3 is a schematic flowchart illustrating an implementation of a method for aligning a phase of an output signal with a phase of an input signal according to an embodiment of the present application;
fig. 4 is a schematic flowchart illustrating an implementation process of a phase locking method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a phase locking device according to an embodiment of the present disclosure;
fig. 6 is a hardware entity diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the embodiments of the present application will be described in further detail below with reference to the drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
In the following description, references to the terms "first \ second \ third" are only to distinguish similar objects and do not denote a particular order, but rather the terms "first \ second \ third" are used to interchange specific orders or sequences, where appropriate, so as to enable the embodiments of the application described herein to be practiced in other than the order shown or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
Fig. 1 is a schematic diagram of a DPLL architecture provided in an embodiment of the present application, and as shown in fig. 1, the DPLL includes: a Digital phase detector 11, a Loop Filter (DLF) 12, a digitally controlled Oscillator (NCO) 13, a first frequency Divider (Divider)14 and a second frequency Divider (Divider)15, wherein,
the phase detector 11, also called sampling phase detector, is used to compare the phase of the input signal with the output signal (feedback signal) of the voltage controlled oscillator, the output voltage being a function of the phase difference corresponding to the two signals. The phase detector is a key component in the phase-locked loop, and the form of the digital phase detector can be divided into: a zero-cross sampling phase discriminator, a flip-flop type digital phase discriminator, a lead-lag type digital phase discriminator and a Nyquist rate sampling phase discriminator.
The loop filter 12 suppresses input noise in the loop and adjusts the correction speed of the loop.
The numerically controlled oscillator 13 is also called a digital clock. The place in the digital loop is equivalent to a voltage controlled oscillator in the analog phase locked loop. The digitally controlled oscillator output is a pulse train and the period of the output pulse train is controlled by a correction signal from the digital loop filter. The control characteristics are as follows: the correction signal obtained at the previous sampling instant will change the pulse time position at the next sampling instant.
The first frequency divider 14 and the second frequency divider 15 are both used for dividing the frequency of the oscillation signal output by the digitally controlled oscillator 13.
In the implementation process, firstly, the phase difference between the input end signal (input signal) and the feedback end signal (feedback signal) of the phase discriminator 11 in the digital phase discriminator is obtained; then, the phase value of the feedback signal is adjusted in the numerical range based on the phase difference, so as to realize the fast locking of the phase of the digital phase discriminator, and simultaneously, the output port signal (output signal) of the corresponding first frequency divider 14 is processed in advance or in a delayed manner, so as to realize the phase synchronization of the input signal and the output signal.
The advantages of using the digital phase-locked loop to lock the signal phase are as follows: the phase is locked quickly, and no seconds are lost in the quick locking process.
An embodiment of the present application provides a data phase-locked loop, including:
the phase discriminator is used for acquiring the phase difference between the input signal and the feedback signal of the digital phase-locked loop;
here, the phase detector may first acquire the phase of the input signal and the phase of the feedback signal output by the voltage controlled oscillator and then determine the phase difference of the input signal and the feedback signal.
A processor to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold;
here, the processor may be a processor connected to the digital phase locked loop for processing various signals in the digital phase locked loop.
The phase difference threshold value can be set by a user according to actual needs, and under the condition that the phase difference is determined to be larger than the phase difference threshold value, the phase value of the feedback end can be adjusted in a numerical range based on the phase difference, so that the phase difference between the input signal and the feedback signal is reduced, and the digital phase-locked loop is quickly locked.
The processor is further configured to compensate an output signal of the digital phase locked loop based on the phase difference to achieve phase locking.
In practice, the phase value of the feedback signal is adjusted based on the phase difference, and simultaneously, the output signal of the digital phase-locked loop is compensated based on the phase difference, so that the phase synchronization of the input signal and the output signal is realized.
In the embodiment of the application, the phase discriminator is used for acquiring the phase difference between the input signal and the feedback signal of the digital phase-locked loop; a processor to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold; compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking. In this way, in the case that the phase difference is determined to be greater than the phase difference threshold, the direct compensation of the phase difference in the digital domain based on the phase difference of the input signal and the feedback signal can be achieved, and the phase can be locked quickly.
In some embodiments, the digital phase-locked loop further comprises:
a first register for providing phase registration service for the feedback signal;
here, the first register may be a register that provides a phase registration service for the feedback signal.
The processor is further configured to register the phase difference to the first register if it is determined that the phase difference is greater than a phase difference threshold;
in the implementation process, the first register is used for registering the phase difference between the input signal and the feedback signal so as to compensate the phase difference to the feedback signal in time, reduce the phase difference between the input signal and the feedback signal of the phase discriminator and realize the rapid locking of the phase of the digital phase-locked loop.
A second register for providing phase registration service for the output signal;
here, the second register may be a register that provides a phase registration service for the output signal.
In some embodiments, the second register and the first register may share one register, and the functions of the first register and the second register are implemented by setting different storage spaces in the register.
In some embodiments, the second register and the first register may be different registers.
The processor is further configured to register the phase difference to the second register if it is determined that the phase difference is greater than a phase difference threshold.
In an implementation, the phase difference may be registered to the second register at the same time as the phase difference is registered to the first register, so as to compensate the output signal of the digital phase-locked loop based on the phase difference.
In the embodiment of the application, a first register and a second register can be arranged in the digital phase-locked loop and are respectively used for providing phase registering services for the feedback signal and the output signal so as to realize timely compensation of the phase difference to the feedback signal, reduce the phase difference between the input signal and the feedback signal of the phase discriminator and realize rapid locking of the phase of the digital phase-locked loop; meanwhile, the phase synchronization of the input signal and the output signal is realized based on the output signal of the phase difference compensation digital phase-locked loop.
An embodiment of the present application provides a phase locking method, as shown in fig. 2, the method includes:
step S210, obtaining the phase difference between the input signal and the feedback signal of the digital phase-locked loop;
here, as in the digital phase-locked loop shown in fig. 1, the phase detector 11 in the digital phase-locked loop may be used to acquire the phase of the input signal and the phase of the feedback signal of the digital phase-locked loop, and then determine the phase difference based on the phase of the input signal and the phase of the feedback signal.
Step S220, in a case that it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal;
and step S230, compensating the output signal of the digital phase-locked loop based on the phase difference to realize phase locking.
In the implementation process, the steps S220 and S230 are not performed in a different order, and may be performed simultaneously. In this way, after the steps S220 and S230 are performed, the phase difference between the two input signals (the input signal and the feedback signal) of the phase detector can be reduced, and the fast locking of the phase of the digital phase-locked loop can be realized. Meanwhile, according to the phase difference value compensated at the feedback end, the corresponding output signal is processed in advance or in a delayed mode, and phase synchronization of the input signal and the output signal is achieved.
In the embodiment of the application, firstly, the phase difference between the input signal and the feedback signal of the digital phase-locked loop is obtained; then, in a case where it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal; compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking. In this way, in the case that the phase difference is determined to be greater than the phase difference threshold, the direct compensation of the phase difference in the digital domain based on the phase difference of the input signal and the feedback signal can be achieved, and the phase can be locked quickly.
In some embodiments, the above step S220 "in the case that it is determined that the phase difference is greater than the phase difference threshold, adjusting the phase value of the feedback signal of the digital phase-locked loop based on the phase difference to reduce the phase difference between the input signal and the feedback signal of the digital phase-locked loop" may be implemented by:
and under the condition that the phase difference is determined to be larger than a phase difference threshold value, storing the phase difference in a first register of the digital phase-locked loop so as to compensate the phase difference of the input signal and the feedback signal, wherein the first register provides phase registration service for the feedback signal.
Here, a first register for providing a phase registration service for the feedback signal; the phase difference of the input signal and the feedback signal is registered.
In implementation, the phase difference between the input signal and the feedback signal of the phase detector is reduced by obtaining the phase difference compensation feedback signal from the first register.
In the embodiment of the application, the phase difference is stored by using the first register, so that the phase compensation of the feedback signal is realized.
In some embodiments, the above step S230 "compensating the output signal of the digital phase locked loop based on the phase difference to achieve phase lock" may be achieved by:
and storing the phase difference in a second register of the digital phase-locked loop to compensate the output signal based on the phase difference, and aligning the phase of the output signal with the phase of the input signal to realize phase locking, wherein the second register provides phase registration service for the output signal.
Here, a second register for providing a phase registration service for the output signal; the phase difference of the input signal and the feedback signal is registered.
In some embodiments, the second register and the first register may share one register, and the functions of the first register and the second register are implemented by setting different storage spaces in the register.
In some embodiments, the second register and the first register may be different registers.
In practice, the phase of the output signal is aligned with the phase of the input signal by retrieving the phase difference compensated output signal from the second register.
In the embodiment of the application, the phase difference is stored by using the second register, so that the phase compensation of the output signal is realized, the phase of the output signal is aligned with the phase of the input signal, and the phase locking is realized.
In some embodiments, the above step S230 "compensating the output signal of the digital phase locked loop based on the phase difference to achieve phase lock" may be achieved by:
step 231, determining a delay relationship between the delay of the output signal and the delay of the input signal based on the phase difference;
step 232, aligning the phase of the output signal with the phase of the input signal based on the time delay relationship, so as to implement phase locking.
In the embodiment of the application, firstly, the time delay relation between the time delay of the output signal and the time delay of the input signal is determined based on the phase difference; phase alignment of the output signal with the input signal may then be achieved based on the time delay relationship.
In some embodiments, as shown in fig. 3, the above step 232 "aligning the phase of the output signal with the phase of the input signal based on the time delay relationship, and achieving phase lock" may be achieved by:
step S310, under the condition that the time delay of the output signal is determined to be larger than the time delay of the input signal based on the time delay relation, determining the advance period of the output signal based on the phase difference;
step S320, outputting the output signal based on the advance period, aligning the phase of the output signal with the phase of the input signal, and implementing phase locking;
in the implementation process, when it is determined that the time delay of the output signal is greater than the time delay of the input signal, it may be determined that the output signal needs to be output in advance based on the advance period, so that the phase of the output signal is aligned with the phase of the input signal, and phase locking is achieved.
Step S330, determining a delay period of the output signal based on the phase difference under the condition that the time delay of the output signal is determined to be smaller than the time delay of the input signal based on the time delay relation;
step S340, outputting the output signal based on the delay period, aligning the phase of the output signal with the phase of the input signal, and implementing phase locking.
In the implementation process, when it is determined that the delay of the output signal is smaller than the delay of the input signal, it may be determined that the output signal needs to be delayed based on the delay period, so that the phase of the output signal is aligned with the phase of the input signal, and phase locking is achieved.
In the embodiment of the application, the phase locking is realized by firstly determining the advance period or the delay period of the output signal based on the phase difference and then aligning the phase of the output signal with the phase of the input signal based on the advance period or the delay period.
Fig. 4 is a phase locking method according to an embodiment of the present application, and as shown in fig. 4, the phase locking method includes the following steps:
step S410, acquiring a phase difference between an input signal and a feedback signal of the digital phase-locked loop;
step S420, in a case that it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal;
step S430, compensating the output signal of the digital phase-locked loop based on the phase difference to realize phase locking;
step S440, determining a first adjusting voltage based on the phase difference under the condition that the phase difference is smaller than the phase difference threshold value;
in implementation, a user may adjust the phase difference threshold based on actual usage requirements, and in the case that the phase difference is determined to be less than the phase difference threshold, the first adjustment voltage may be determined based on the phase difference.
S450, filtering high-frequency components of the first adjusting voltage to obtain a second adjusting voltage;
in the implementation process, the loop filter 12 of the digital phase locked loop shown in fig. 1 may filter out a high frequency component of the first adjustment voltage to obtain a second adjustment voltage.
And step S460, adjusting the output signal based on the second adjusting voltage, and realizing phase locking.
In practice, the digitally controlled oscillator 13 of the digital phase locked loop shown in fig. 1 may obtain a second adjustment voltage based on the loop filter 12, and then adjust the output signal based on the second adjustment voltage to achieve phase locking.
The numerically controlled oscillator 13 may further adjust the feedback signal based on the second adjustment voltage, so as to achieve phase alignment between the feedback signal and the input signal.
In the embodiment of the present application, in the case where it is determined that the phase difference is smaller than the phase difference threshold value, the first adjustment voltage is determined based on the phase difference; filtering out high-frequency components of the first adjusting voltage to obtain a second adjusting voltage; and adjusting the output signal based on the second adjusting voltage to realize phase locking. Thus, when the phase difference is small, the phase alignment of the output signal and the input signal can be achieved by the second adjustment voltage for adjusting the phase of the output signal.
Based on the foregoing embodiments, the present application provides a phase locking device, which includes modules, each module includes sub-modules, each sub-module includes a unit, and the sub-modules can be implemented by a processor in an electronic device; of course, the implementation can also be realized through a specific logic circuit; in the implementation Process, the processor may be a Central Processing Unit (CPU), a Microprocessor Unit (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.
Fig. 5 is a schematic structural diagram of a phase lock device according to an embodiment of the present application, and as shown in fig. 5, the phase lock device 500 includes:
a first obtaining module 510, configured to obtain a phase difference between an input signal and a feedback signal of the digital phase-locked loop;
a first adjusting module 520, configured to adjust the phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold;
a compensation module 530 for compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase lock.
In some embodiments, the first adjusting module 520 is further configured to store the phase difference in a first register of the digital phase locked loop to compensate for the phase difference between the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold, wherein the first register provides a phase registration service for the feedback signal.
In some embodiments, the compensation module 530 is further configured to store the phase difference in a second register of the digital phase locked loop to compensate the output signal, align the phase of the output signal with the phase of the input signal, and achieve phase lock, wherein the second register provides a phase registration service for the output signal.
In some embodiments, the compensation module 530 includes a determination sub-module and an alignment sub-module, wherein the determination sub-module is configured to determine a delay relationship between the delay of the output signal and the delay of the input signal based on the phase difference; and the alignment submodule is used for aligning the phase of the output signal with the phase of the input signal based on the time delay relation, so as to realize phase locking.
In some embodiments, the alignment submodule comprises a first determining unit, a first alignment unit, a second determining unit and a second alignment unit, wherein the first determining unit is configured to determine the advance period of the output signal based on the phase difference if it is determined that the time delay of the output signal is greater than the time delay of the input signal based on the time delay relationship; the first alignment unit is used for outputting the output signal based on the advance period, aligning the phase of the output signal with the phase of the input signal and realizing phase locking; the second determining unit is configured to determine a delay period of the output signal based on the phase difference when it is determined that the time delay of the output signal is smaller than the time delay of the input signal based on the time delay relationship; and the second alignment unit is used for outputting the output signal based on the delay period, aligning the phase of the output signal with the phase of the input signal and realizing phase locking.
In some embodiments, the apparatus further comprises a determining module, a filtering module, and a second adjusting module, wherein the determining module is configured to determine a first adjusted voltage based on the phase difference if it is determined that the phase difference is less than the phase difference threshold; the filtering module is used for filtering out high-frequency components of the first adjusting voltage to obtain a second adjusting voltage; and the second adjusting module is used for adjusting the output signal based on the second adjusting voltage to realize phase locking.
The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be noted that, in the embodiment of the present application, if the method is implemented in the form of a software functional module and sold or used as a standalone product, the method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing an electronic device (which may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
Correspondingly, the present application provides a storage medium, on which a computer program is stored, which when executed by a processor implements the steps in the phase locking method provided in the above embodiments.
Correspondingly, an embodiment of the present application provides an electronic device, and fig. 6 is a schematic diagram of a hardware entity of the electronic device provided in the embodiment of the present application, as shown in fig. 6, the hardware entity of the device 600 includes: comprising a memory 601 and a processor 602, said memory 601 storing a computer program operable on the processor 602, said processor 602 implementing the steps in the phase locking method provided in the above embodiments when executing said program.
The Memory 601 is configured to store instructions and applications executable by the processor 602, and may also buffer data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or already processed by the processor 602 and modules in the electronic device 600, and may be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM).
Here, it should be noted that: the above description of the storage medium and device embodiments is similar to the description of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the storage medium and apparatus of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing an electronic device (which may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to arrive at new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of phase locking, the method comprising:
acquiring the phase difference of an input signal and a feedback signal of the digital phase-locked loop;
adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold;
compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase locking.
2. The method of claim 1, wherein adjusting the phase value of the feedback signal of the digital phase-locked loop based on the phase difference to reduce the phase difference of the input signal and the feedback signal of the digital phase-locked loop if it is determined that the phase difference is greater than a phase difference threshold, comprises:
and under the condition that the phase difference is determined to be larger than a phase difference threshold value, storing the phase difference in a first register of the digital phase-locked loop so as to adjust a phase value of a feedback signal of the digital phase-locked loop based on the phase difference, wherein the first register provides phase registration service for the feedback signal.
3. The method of claim 1, compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase lock, comprising:
and storing the phase difference in a second register of the digital phase-locked loop to compensate the output signal based on the phase difference, and aligning the phase of the output signal with the phase of the input signal to realize phase locking, wherein the second register provides phase registration service for the output signal.
4. The method of claim 1, the compensating an output signal of the digital phase locked loop based on the phase difference to achieve phase lock, comprising:
determining a delay relationship of a delay of the output signal to a delay of the input signal based on the phase difference;
and aligning the phase of the output signal with the phase of the input signal based on the time delay relation to realize phase locking.
5. The method of claim 4, said aligning the phase of the output signal with the phase of the input signal based on the time delay relationship, achieving phase lock, comprising:
determining an advance period of the output signal based on the phase difference if it is determined that the time delay of the output signal is greater than the time delay of the input signal based on the time delay relationship;
outputting the output signal based on the advance period, aligning the phase of the output signal with the phase of the input signal, and achieving phase locking;
determining a delay period of the output signal based on the phase difference if it is determined that the time delay of the output signal is less than the time delay of the input signal based on the time delay relationship;
and outputting the output signal based on the delay period, and aligning the phase of the output signal with the phase of the input signal to realize phase locking.
6. The method of any of claims 1 to 5, further comprising:
determining a first adjustment voltage based on the phase difference if it is determined that the phase difference is less than the phase difference threshold;
filtering out high-frequency components of the first adjusting voltage to obtain a second adjusting voltage;
and adjusting the output signal based on the second adjusting voltage to realize phase locking.
7. A digital phase locked loop, comprising:
the phase discriminator is used for acquiring the phase difference between the input signal and the feedback signal of the digital phase-locked loop;
a processor to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference of the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold;
the processor is further configured to compensate an output signal of the digital phase locked loop based on the phase difference to achieve phase locking.
8. The digital phase locked loop of claim 7, further comprising:
a first register for providing phase registration service for the feedback signal;
the processor is further configured to register the phase difference to the first register if it is determined that the phase difference is greater than a phase difference threshold;
a second register for providing phase registration service for the output signal;
the processor is further configured to register the phase difference to the second register if it is determined that the phase difference is greater than a phase difference threshold.
9. A phase-lock apparatus, the apparatus comprising:
the acquisition module is used for acquiring the phase difference between the input signal and the feedback signal of the digital phase-locked loop;
a first adjusting module, configured to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal if it is determined that the phase difference is greater than a phase difference threshold;
and the compensation module is used for compensating the output signal of the digital phase-locked loop based on the phase difference so as to realize phase locking.
10. An electronic device comprising a memory and a processor, the memory storing a computer program operable on the processor, the processor implementing the steps of the method of any one of claims 1 to 6 when executing the program.
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