CN115047243A - Current detection circuit applied to DNA sequencing - Google Patents

Current detection circuit applied to DNA sequencing Download PDF

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Publication number
CN115047243A
CN115047243A CN202210589068.2A CN202210589068A CN115047243A CN 115047243 A CN115047243 A CN 115047243A CN 202210589068 A CN202210589068 A CN 202210589068A CN 115047243 A CN115047243 A CN 115047243A
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switch
capacitor
nmos tube
voltage
feedback loop
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Inventor
李治
王镇
诸小胜
韩增产
王永利
施成丽
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Sinoway Technology Wuxi Co ltd
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Sinoway Technology Wuxi Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Abstract

The invention discloses a current detection circuit applied to DNA sequencing, which comprises a capacitance trans-impedance amplifier array, a difference value sampling circuit and an analog-to-digital converter for analog-to-digital conversion; the capacitor transimpedance amplifier array is used for performing capacitor integration on input current and outputting an integrated voltage, and consists of M rows of capacitor transimpedance amplifier units and N columns of capacitor transimpedance amplifier units; the difference value sampling circuit is used for simultaneously sampling a plurality of integral voltages of each row of the capacitor transimpedance amplifier array, amplifying the integral voltages and then outputting the amplified integral voltages; and the output ports of the N columns of the capacitor transimpedance amplifier array are respectively connected to N input ports of the difference value sampling circuit, and output signals of the difference value sampling circuit are sent to the input end of the analog-to-digital converter.

Description

Current detection circuit applied to DNA sequencing
Technical Field
The invention belongs to the technical field of electronic circuit design, and particularly relates to a current detection circuit applied to DNA sequencing.
Background
DNA (deoxyribonic Acid Deoxyribonucleic Acid) sequencing is the process of determining the identity and order of DNA bases (ACGT) in a DNA fragment. Sequencing methods currently used are diverse, such as Sequencing By Synthesis (SBS), nanopore sequencing, and the like.
Charge-sensing measurements are one type of sequencing-by-synthesis and are suitable for use in integrated circuits to perform DNA sequencing. Because the current to be detected in DNA sequencing is very weak, generally in the magnitude of dozens of fA to hundreds of fA, the traditional electric induction measurement mainly depends on ISFET (Ion-sensitive Field-Effect Transistor) for detection, and the defects are that the current is sensed by a passivation layer, an excitation mode cannot be compatible, and excitation and sequencing functions cannot be simultaneously supported.
In addition, in the conventional measurement scheme, a plurality of ADCs (analog To Digital converters) are often used in cooperation with the microelectrode array for data acquisition, which greatly increases the complexity of the chip and the area of the chip.
Disclosure of Invention
The invention aims to: in order to solve the problems that the conventional sequencing method cannot support the excitation and sequencing functions simultaneously and the problems of high chip complexity and large chip area in the conventional measurement method, the invention provides a current detection circuit applied to DNA sequencing.
The technical scheme is as follows: a current detection circuit applied to DNA sequencing comprises a capacitor trans-impedance amplifier array, a difference value sampling circuit and an analog-to-digital converter for analog-to-digital conversion;
the capacitor transimpedance amplifier array is used for performing capacitor integration on input current and outputting an integrated voltage, and consists of M rows of capacitor transimpedance amplifier units and N columns of capacitor transimpedance amplifier units;
the difference value sampling circuit is used for simultaneously sampling a plurality of integral voltages of each row of the capacitor transimpedance amplifier array, and outputting the plurality of integral voltages after amplifying the integral voltages in sequence;
and the output ports of the N columns of the capacitor transimpedance amplifier array are respectively connected to N input ports of the difference value sampling circuit, and output signals of the difference value sampling circuit are sent to the input end of the analog-to-digital converter.
Further, the structure of each column in the capacitor transimpedance amplifier array comprises one PCELL and M NCELLs; arranging the M NCELLs according to the positions of M rows in the array;
the PCELL comprises: a first PMOS transistor and a second PMOS transistor, wherein the gate of the first PMOS transistor is connected with a voltage V cp The drain electrode of the first PMOS tube is used as an output port of the column, the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the second PMOS tube is connected with a voltage V bp The source electrode of the second PMOS tube is connected with a voltage VDD;
each NCELL comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor and an electrode; the grid electrode of the first NMOS tube is connected with the electrode, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; grid access voltage V of second NMOS tube cn The drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube; a grid electrode of the third NMOS tube is connected with a Row Select signal, and a drain electrode of the third NMOS tube is connected with a source electrode of the fifth NMOS tube; a grid electrode of the fourth NMOS tube is connected with a Row Select signal, a source electrode of the fourth NMOS tube is connected with a drain electrode of the first PMOS tube, and the drain electrode of the fourth NMOS tube is connected with an electrode through a first capacitor; a grid electrode of the fifth NMOS tube is connected with a RST signal, a drain electrode of the fifth NMOS tube is connected with the electrode, and a source electrode of the fifth NMOS tube is connected with a drain electrode of the third NMOS tube;
when the Row Select signal is high and the RST signal is low, the NCELL enters the integrating operation, and when the Row Select signal is low, the NCELL stops operating, and when the Row Select signal and the RST signal are simultaneously high, the NCELL resets to the initial level.
Furthermore, at most one NCELL works normally for any column in the capacitor trans-impedance amplifier array.
Further, the electrode is a metal electrode.
Furthermore, the difference value sampling circuit comprises N paths of integrated voltage receiving circuits, an amplifier, a first feedback loop and a second feedback loop;
the N paths of integrated voltage receiving circuits sequentially correspond to N rows of output ports of the capacitor trans-impedance amplifier array, and each path of integrated voltage receiving circuit has the same structure and comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor and a third capacitor;
one end of the first switch and one end of the second switch are both connected with integral voltage, the other end of the first switch is connected with one end of a third switch through a second capacitor, and the other end of the third switch is connected with the positive input end of the amplifier; the other end of the second switch is connected with one end of a fourth switch through a third capacitor, and the other end of the fourth switch is connected with the negative input end of the amplifier; one end of a fifth switch is connected with the other end of the first switch, the other end of the fifth switch is connected with one end of a sixth switch, the other end of the sixth switch is connected with the other end of the second switch, and the other end of the fifth switch is connected with a voltage Vcm 1;
the first feedback loop and the second feedback loop have the same structure and both comprise: a seventh switch, an eighth switch, a ninth switch and a fourth capacitor; one end of the fourth capacitor is connected with one end of the ninth switch;
the other end of the fourth capacitor is connected with a voltage Vcm2 through an eighth switch, and the other end of the fourth capacitor is connected with one end of a seventh switch;
one end of a fourth capacitor in the first feedback loop is connected with the positive input end of the amplifier, the other end of a ninth switch is connected with the negative output end of the amplifier, and the other end of a seventh switch is connected with the negative output end of the amplifier;
one end of a fourth capacitor in the second feedback loop is connected with the negative input end of the amplifier, the other end of the ninth switch is connected with the positive output end of the amplifier, and the other end of the seventh switch is connected with the positive output end of the amplifier.
Further, when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at high level, the seventh switch is at low levelLevel, and when the first switch and the third switch in the N-path integral voltage receiving circuit are high and the second switch and the fourth switch are low, the difference value sampling circuit performs sampling at time t1, and t 1 Is the starting time of the integral measurement;
when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are in high level, the seventh switch is in low level, and when the second switch and the fourth switch in the N-path integral voltage receiving circuit are in high level and the first switch and the third switch are in low level, the difference value sampling circuit samples at the time t2, and the time t2 is 2 Indicating the end time of the integration measurement.
Furthermore, when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at low level, the seventh switch is at high level, and when the fifth switch and the sixth switch in a certain path of the integrated voltage receiving circuit are at high level, and the third switch and the fourth switch are at high level, the voltage sampled by the path of the integrated voltage receiving circuit is amplified to the output end.
Furthermore, each path of integral voltage receiving circuit amplifies the sampled voltage to an output end in sequence.
Has the advantages that: compared with the prior art, the invention has the following advantages:
(1) according to the invention, a capacitive transimpedance amplifier Array CTIA Array (capacitive transimpedance amplifier Array) is used for carrying out capacitance integral measurement on input weak current, so that the fA magnitude current measurement can be realized, a metal electrode can be used for measurement, and the excitation and sequencing functions can be simultaneously supported;
(2) the differential Sampling Circuit DDS Circuit (Delta Difference Sampling Circuit) is adopted, a plurality of same arrays in a microelectrode array are simultaneously sampled, namely a plurality of channels in each line are simultaneously sampled, a single ADC finishes Sampling of a full array in a line-column scanning mode, and Sampling voltage is serially sent to the ADC for quantification, so that the number of rear-stage ADCs is greatly reduced, and the system area is reduced;
(3) the DDS supports offset of OTA, and realizes higher signal-to-noise ratio;
(4) the detection circuit has the advantages of simple structure, small size, suitability for standard CMOS process processing, easiness in realizing large-scale microelectrode arrays and the like.
Drawings
FIG. 1 is a top level block diagram of the present invention;
FIG. 2 is a block diagram of a row of capacitive transimpedance amplifiers in the capacitive transimpedance amplifier Array CTIA Array;
fig. 3 is a block diagram of a differential sampling Circuit DDS Circuit;
fig. 4 is a block diagram of the operating state of the difference sampling Circuit DDS Circuit.
Detailed Description
The technical solution of the present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 1, the current detection Circuit applied To DNA sequencing of the present invention mainly includes a capacitive transimpedance amplifier Array (CTIA Array), a Delta Difference Sampling Circuit (DDS Circuit), and an analog-To-Digital Converter (ADC).
As shown in fig. 1, the capacitor transimpedance amplifier array according to the present invention is composed of M rows and N columns of CTIA units. Fig. 2 shows a block diagram of a column of capacitive transimpedance amplifiers in the capacitive transimpedance amplifier array, which mainly includes a pcell (pmos cell) and M NCELLs (nmos cell) arranged in the electrode array according to the positions of M rows.
As shown in fig. 2, PCELL is a unit composed of PMOS, which mainly includes: a first PMOS transistor P1 and a second PMOS transistor P2, the grid of the first PMOS transistor P1 is connected with a voltage V cp The drain of the first PMOS transistor P1 is used as the output port of the column capacitor transimpedance amplifier, the source of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to a voltage V bp And the source of the second PMOS pipe P2 is connected with the voltage VDD.
As shown in fig. 2, each NCELL is a unit constituted by an NMOS, which mainly includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a first capacitor C1 and a Metal Electrode;
the grid electrode of the first NMOS transistor M1 is connected with the metal electrode, the source electrode of the first NMOS transistor M1 is grounded, and the drain electrode of the first NMOS transistor M1 is connected with the source electrode of the second NMOS transistor M2;
the grid electrode of the second NMOS tube M2 is connected with a voltage Vcn, and the drain electrode of the second NMOS tube M2 is connected with the source electrode of the third NMOS tube M3;
the grid electrode of the third NMOS tube M3 is connected to a Row Select signal, and the drain electrode of the third NMOS tube M3 is connected with the source electrode of the fifth NMOS tube M5;
the grid Electrode of the fourth NMOS tube M4 is connected with a Row Select signal, the source Electrode of the fourth NMOS tube M4 is connected with the drain Electrode of the first PMOS tube P1, and the drain Electrode of the fourth NMOS tube M4 is connected with a Metal Electrode through a first capacitor C1;
the gate of the fifth NMOS transistor M5 is connected to the RST signal, the drain of the fifth NMOS transistor M5 is connected to the Metal Electrode, and the source of the fifth NMOS transistor M5 is connected to the drain of the third NMOS transistor M3.
The NCELL operates normally when the Row Select signal is high and stops when the Row Select signal is low. In a column of capacitive transimpedance amplifiers, at most one NCELL operates normally at the same time, and selection is performed by the Row Select signal. The fifth NMOS tube M5 is connected to the RST signal, and when the Row Select signal and the RST signal of the NCELL are simultaneously high level, the CTIA is reset to the initial level; when the Row Select signal is high and the RST signal is low, the CTIA reset is finished, and the integration working mode is entered.
And the output ports of the N columns of the capacitor transimpedance amplifier array are respectively connected to the N input ports of the difference value sampling circuit. The output signal of the difference sampling circuit is sent to the input port of the analog-to-digital converter.
The capacitive transimpedance amplifier Array CTIA Array can realize integral measurement of multipath input weak current, and measurable output voltage can be obtained by reducing integral capacitance and increasing integral time;
Figure BDA0003666868070000041
in the formula I in (t) represents a weak current signal of the input capacitance trans-impedance amplifier CTIA, C1 represents the capacitance value of the first capacitor C1, and t 1 Indicating the starting moment of the integral measurement, t 2 Indicating the end time of the integration measurement.
Capacitance integration measurement is performed on input weak current, metal electrodes can be used, and excitation and sequencing functions are supported.
Fig. 3 shows a block diagram of a difference sampling Circuit DDS Circuit, where the difference sampling Circuit samples multiple channels in each row of the capacitor transimpedance amplifier array at the same time, obtains a voltage difference between the integrated voltages at two moments, and sequentially amplifies and outputs the integrated voltages.
As shown in fig. 3, the difference sampling Circuit DDS Circuit includes N integrating voltage receiving circuits, an amplifier, a first feedback loop, and a second feedback loop; the amplifier adopted by the invention is a transconductance amplifier OTA.
The N paths of integrated voltage receiving circuits correspond to N columns of output ports of the capacitor transimpedance amplifier array in sequence, and each path of integrated voltage receiving circuit has the same structure and comprises a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a second capacitor C2 and a third capacitor C3;
one end of the first switch S1 and one end of the second switch S2 are both connected to an integrated voltage, the other end of the first switch S1 is connected to one end of the third switch S3 through the second capacitor C2, and the other end of the third switch S3 is connected to the positive input end of the amplifier;
the other end of the second switch S2 is connected to one end of a fourth switch S4 through a third capacitor C3, and the other end of the fourth switch S4 is connected to the negative input terminal of the amplifier;
one end of the fifth switch S5 is connected to the other end of the first switch S1, the other end of the fifth switch S5 is connected to one end of the sixth switch S6, the other end of the sixth switch S6 is connected to the other end of the second switch S2, that is, the fifth switch S5 is connected in series with the sixth switch S6, and the other end of the fifth switch S5 is connected to a voltage Vcm 1.
The first feedback loop and the second feedback loop have the same structure and both comprise: a seventh switch S7, an eighth switch S8, a ninth switch S9, and a fourth capacitor C4;
one end of the fourth capacitor C4 is connected to one end of the ninth switch S9;
the other terminal of the fourth capacitor C4 is connected to the voltage V cm2 through an eighth switch S8, and the other terminal of the fourth capacitor C4 is connected to one terminal of a seventh switch S7.
One end of the first feedback loop is connected to the positive input end of the amplifier, and the other end of the first feedback loop is connected to the negative output end of the amplifier, that is, one end of the fourth capacitor C4 in the first feedback loop is connected to the positive input end of the amplifier, the other end of the ninth switch S9 is connected to the negative output end of the amplifier, and the other end of the seventh switch S7 is connected to the negative output end of the amplifier.
One end of the second feedback loop is connected to the negative input end of the amplifier, and the other end of the second feedback loop is connected to the positive output end of the amplifier, that is, one end of the fourth capacitor C4 in the second feedback loop is connected to the negative input end of the amplifier, the other end of the ninth switch S9 is connected to the positive output end of the amplifier, and the other end of the seventh switch S7 is connected to the positive output end of the amplifier.
As shown in fig. 4, in a specific working process, the difference sampling Circuit DDS Circuit of the present invention includes two working states: sampling the working state and amplifying the working state.
Referring to sample phase in fig. 4, when the difference sampling Circuit DDS Circuit is in the sampling operation state, the ninth switch S9 and the eighth switch S8 are at high level and the seventh switch S7 is at low level for the first feedback loop and the second feedback loop. When the first switch S1 and the third switch S3 of the N-way integration voltage receiving circuit are high and the second switch S2 and the fourth switch S4 are low, i.e., the first switch S1 and the third switch S3 are closed and the second switch S2 and the fourth switch S4 are opened, the voltage of the N-way integration voltage receiving circuit charges the second capacitor C2 connected to the first switch S1/the third switch S3, the first switch S1/the third switch S3 are pulled low, and the time t is 1 And finishing sampling.
When the second switch S2 and the fourth switch S4 of the N-way integral voltage receiving circuit are high and the first switch S1 and the third switch S3 are low, N-way integral voltage receiving circuitThe voltage of the integrated voltage receiving circuit charges a third capacitor C3 connected with the second switch S2/the fourth switch S4, and the second switch S2/the fourth switch S4 are pulled down at a time t 2 And finishing sampling.
After the above process is completed, the sampling voltages of the N-path integrated voltage receiving circuit at two moments t1 and t2 are stored on the second capacitor C2 and the third capacitor C3.
Referring to Hold phase in fig. 4, when the difference sampling Circuit DDS Circuit is in the amplification operation state, the ninth switch S9 and the eighth switch S8 are at low level and the seventh switch S7 is at high level for the first feedback loop and the second feedback loop. When the fifth switch S5 and the sixth switch S6 of one integrated voltage receiving circuit are high and the third switch S3 and the fourth switch S4 are high, the voltage sampled by the integrated voltage receiving circuit is amplified to the output end, and the voltage V 'is output' out Expressed as:
Figure BDA0003666868070000061
in the formula, V in (t 2 ) Denotes t 2 Sampled voltage of time, V in (t 1 ) Represents t 1 The sampling voltage at the moment, the capacitance values of the second capacitor and the third capacitor are the same and are C 2 ；C 4 Is the capacitance value of the fourth capacitor.
The left side of the equal sign of the formula (3) represents a first sampling stage, and the right side thereof represents an amplification stage; the left side of the equal sign of the formula (4) represents a second sampling stage, and the right side thereof represents an amplification stage; by making a difference between the formula (3) and the formula (4), it can be seen that the difference sampling Circuit DDS Circuit of the present invention also has an offset cancellation function.
Figure BDA0003666868070000062
(3)-(4):
(V os -(V 1 -V 2 ))C 2 +V os ·C 4 ＝V os ·C 2 +(V os +V out )C 4
V os ·C 2 -(V 1 -V 2 )·C 2 +V os ·C 4 ＝V os ·C 2 +V os ·C 4 +V out ·C 4
Figure BDA0003666868070000063
In the formula, C 2 The capacitance value of a second capacitor C2 is shown, and the second capacitor C2 is used as an input sampling capacitor of the DDS module; c 4 The capacitance value of a fourth capacitor C4 is shown, and the fourth capacitor C4 is used as an output feedback capacitor of the DDS module; v ota+ Represents the input positive terminal voltage of the OTA; v ota- Represents the input negative terminal voltage of the OTA; v 1 Represents the input voltage of the DDS at the integration measurement start time t 1; v 2 Represents the input voltage of the DDS at the integration measurement end time t 2; v cm2 Representing the bias voltage of the output stage OTA of the DDS module; v cm1 Representing the bias voltage of an input stage sampling capacitor of the DDS module; v out- Represents the negative terminal voltage output of the DDS output stage OTA; v out+ Represents the positive terminal voltage output of the DDS output stage OTA; v os Representing input offset voltage of OTA, equal to V ota+ Minus V ota- ；V out Representing differential voltage output of DDS output stage OTA, equal to V out+ Minus V out- 。
After the three processes of first sampling, second sampling and amplifying, the offset voltage at the input end of the OTA can be cancelled.
In the specific use of DNA sequencing, a metal electrode in the NCELL is contacted with a DNA cell, the DNA cell can release weak current under certain bioelectricity experimental conditions, and a DNA sequencing circuit consisting of CTIA, DDS and ADC realizes the function of detecting the weak current.

Claims (8)

1. A current detection circuit applied to DNA sequencing is characterized in that: the circuit comprises a capacitor transimpedance amplifier array, a difference value sampling circuit and an analog-to-digital converter for analog-to-digital conversion;
the capacitance transimpedance amplifier array is used for performing capacitance integration on input current and outputting integration voltage, and consists of M rows of capacitance transimpedance amplifier units and N columns of capacitance transimpedance amplifier units;
the differential value sampling circuit is used for simultaneously sampling a plurality of integral voltages of each row of the capacitor transimpedance amplifier array, and amplifying and outputting the integral voltages in sequence;
and the output ports of the N columns of the capacitor transimpedance amplifier array are respectively connected to N input ports of the difference value sampling circuit, and output signals of the difference value sampling circuit are sent to the input end of the analog-to-digital converter.
2. The current detection circuit according to claim 1, wherein: the structure of each column in the capacitor trans-impedance amplifier array comprises a PCELL and M NCELLs; arranging the M NCELLs according to the positions of M rows in the array;
the PCELL comprises: a first PMOS transistor and a second PMOS transistor, wherein the gate of the first PMOS transistor is connected with a voltage V cp The drain electrode of the first PMOS tube is used as the output port of the column, the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the second PMOS tube is connected with a voltage V bp The source electrode of the second PMOS tube is connected with a voltage VDD;
each NCELL comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor and an electrode; the grid electrode of the first NMOS tube is connected with the electrode, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; grid access voltage V of second NMOS tube cn The drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube; a grid electrode of the third NMOS tube is connected with a Row Select signal, and a drain electrode of the third NMOS tube is connected with a source electrode of the fifth NMOS tube; a grid electrode of the fourth NMOS tube is connected with a Row Select signal, a source electrode of the fourth NMOS tube is connected with a drain electrode of the first PMOS tube, and the drain electrode of the fourth NMOS tube is connected with an electrode through a first capacitor; the grid electrode of the fifth NMOS tube is connected with a RST signal, the drain electrode of the fifth NMOS tube is connected with the electrode, and the source electrode of the fifth NMOS tube is connected with the third NMOS tubeThe drain electrodes of the two electrodes are connected;
when the Row Select signal is high and the RST signal is low, the NCELL enters the integrating operation, and when the Row Select signal is low, the NCELL stops operating, and when the Row Select signal and the RST signal are simultaneously high, the NCELL resets to the initial level.
3. The current detection circuit for DNA sequencing of claim 2, wherein: for any column in the capacitor trans-impedance amplifier array, at most one NCELL works normally.
4. The current detection circuit for DNA sequencing of claim 2, wherein: the electrodes are metal electrodes.
5. The current detection circuit according to claim 1, wherein: the difference value sampling circuit comprises N paths of integrated voltage receiving circuits, an amplifier, a first feedback loop and a second feedback loop;
the N paths of integrated voltage receiving circuits sequentially correspond to N rows of output ports of the capacitor trans-impedance amplifier array, and each path of integrated voltage receiving circuit has the same structure and comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor and a third capacitor;
one end of the first switch and one end of the second switch are both connected with integral voltage, the other end of the first switch is connected with one end of the third switch through the second capacitor, and the other end of the third switch is connected with the positive input end of the amplifier; the other end of the second switch is connected with one end of a fourth switch through a third capacitor, and the other end of the fourth switch is connected with the negative input end of the amplifier; one end of a fifth switch is connected with the other end of the first switch, the other end of the fifth switch is connected with one end of a sixth switch, the other end of the sixth switch is connected with the other end of the second switch, and the other end of the fifth switch is connected with a voltage Vcm 1;
the first feedback loop and the second feedback loop have the same structure and both comprise: a seventh switch, an eighth switch, a ninth switch and a fourth capacitor; one end of the fourth capacitor is connected with one end of the ninth switch;
the other end of the fourth capacitor is connected with a voltage Vcm2 through an eighth switch, and the other end of the fourth capacitor is connected with one end of a seventh switch;
one end of a fourth capacitor in the first feedback loop is connected with the positive input end of the amplifier, the other end of a ninth switch is connected with the negative output end of the amplifier, and the other end of a seventh switch is connected with the negative output end of the amplifier;
one end of a fourth capacitor in the second feedback loop is connected with the negative input end of the amplifier, the other end of the ninth switch is connected with the positive output end of the amplifier, and the other end of the seventh switch is connected with the positive output end of the amplifier.
6. The current detection circuit according to claim 5, wherein:
when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are in high level and the seventh switch is in low level, and when the first switch and the third switch in the N-path integral voltage receiving circuit are in high level and the second switch and the fourth switch are in low level, the difference value sampling circuit performs sampling at time t1, and the time t1 is 2 Represents the start time of the integration measurement;
when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are in high level, the seventh switch is in low level, and when the second switch and the fourth switch in the N-path integral voltage receiving circuit are in high level and the first switch and the third switch are in low level, the difference value sampling circuit samples at the time t2, and the time t2 is 2 Indicating the end time of the integration measurement.
7. The current detection circuit according to claim 5, wherein:
and when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at low level, the seventh switch is at high level, and when the fifth switch and the sixth switch in a certain path of integrated voltage receiving circuit are at high level, and the third switch and the fourth switch are at high level, amplifying the voltage sampled by the path of integrated voltage receiving circuit to the output end.
8. The current detection circuit according to claim 7, wherein: and each path of integral voltage receiving circuit amplifies the sampled voltage to an output end in sequence.
CN202210589068.2A 2022-05-27 2022-05-27 Current detection circuit applied to DNA sequencing Pending CN115047243A (en)

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