CN115037814B - TCP/UDP checksum determining method based on FPGA hardware acceleration - Google Patents

TCP/UDP checksum determining method based on FPGA hardware acceleration Download PDF

Info

Publication number
CN115037814B
CN115037814B CN202210970606.2A CN202210970606A CN115037814B CN 115037814 B CN115037814 B CN 115037814B CN 202210970606 A CN202210970606 A CN 202210970606A CN 115037814 B CN115037814 B CN 115037814B
Authority
CN
China
Prior art keywords
data packet
tcp
checksum
header
new data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210970606.2A
Other languages
Chinese (zh)
Other versions
CN115037814A (en
Inventor
刘锋
曾祥刚
李志康
李梦君
沈永超
李书胜
薛楠楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hubei Weiyuan Zhuoyue Technology Co ltd
Original Assignee
Hubei Weiyuan Zhuoyue Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hubei Weiyuan Zhuoyue Technology Co ltd filed Critical Hubei Weiyuan Zhuoyue Technology Co ltd
Priority to CN202210970606.2A priority Critical patent/CN115037814B/en
Publication of CN115037814A publication Critical patent/CN115037814A/en
Application granted granted Critical
Publication of CN115037814B publication Critical patent/CN115037814B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The invention relates to a method for determining TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) checksum based on FPGA (programmable logic device) hardware acceleration, which comprises the following steps: the FPGA receives the data packet, performs checksum calculation on a TCP/UDP data load part of the data packet to obtain a calculation result R1, and adds the calculation result R1 to one end of the data packet to obtain a new data packet containing a private header; the software layer acquires a new data packet from the FPGA, analyzes the new data packet layer by layer and extracts the new data packet to obtain IP header information and TCP/UDP header information, and updates field information of the new data packet according to the requirement of a service layer custom strategy; the software layer calculates to obtain a pseudo header checksum R2 and a TCP header checksum R3; calculating R4= R1+ R2+ R3, performing shift negation operation on R4 to obtain R5, and backfilling the value of R5 serving as a final checksum calculation result into a checksum field of the new data packet; the problem of check sum computational efficiency among the prior art is too low is solved.

Description

TCP/UDP checksum determining method based on FPGA hardware acceleration
Technical Field
The invention relates to the field of network communication protocol data processing and data communication, in particular to a TCP/UDP checksum determining method based on FPGA hardware acceleration.
Background
In recent years, with the further development of network information technology, the 5G era comes, and the data flow transmitted in the network link grows exponentially. In order to ensure the accuracy and correctness of network data transmission and avoid negative influence on the communication quality and data integrity caused by the inconsistency of data streams during receiving and transmitting, a data verification means is required to ensure the completeness and accuracy of data in network communication. There are two general methods for calculating the TCP/UDP checksum: one is realized by means of a traditional software layer algorithm, and CPU resources are called by software to carry out calculation; the other method is based on a novel hardware-only method, and an FPGA is used for calculating the whole checksum.
For the traditional software method, the problems of low check sum calculation efficiency, high system overhead, high packet receiving and transmitting delay and the like are caused by overlong TCP/UDP load part in an actual scene, and the problems are particularly obvious in low-end embedded equipment. The new pure hardware method is characterized by insufficient flexibility, IP header information or TCP/UDP header information needs to be changed in certain service scenes, the calling times between software and hardware are increased, and a new time cost problem is brought.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a TCP/UDP checksum determining method based on FPGA hardware acceleration, and solves the problem of low checksum calculation efficiency in the prior art.
According to a first aspect of the present invention, there is provided a method for determining a TCP/UDP checksum based on FPGA hardware acceleration, including: step 1, an FPGA receives a data packet, calculates the checksum of a TCP/UDP data load part of the data packet to obtain a calculation result R1, and adds the calculation result R1 to one end of the data packet to obtain a new data packet containing a private header;
step 2, the software layer acquires the new data packet from the FPGA, analyzes the new data packet layer by layer and extracts the new data packet to obtain IP header information and TCP/UDP header information, and updates the field information of the new data packet according to the requirement of a service layer custom strategy;
step 3, the software layer extracts the calculation result R1 in the private header of the new data packet; analyzing the new data packet to acquire IP header and TCP/UDP header information, and calculating to acquire a pseudo header checksum R2 and a TCP header checksum R3; and calculating R4= R1+ R2+ R3, performing shift negation operation on R4 to obtain R5, and filling the value of R5 serving as a final checksum calculation result into a checksum field of the new data packet.
On the basis of the technical scheme, the invention can be improved as follows.
Optionally, the process of calculating and obtaining the calculation result R1 in step 1 includes:
step 101, dividing the data load of the TCP or UDP in the received data packet into a plurality of groups of 16-bit data by the FPGA, supplementing 0 to the data with less than 16 bits at the low order, and storing a plurality of sections of 16-bit data in the array;
and 102, traversing the array, carrying out binary inverse sum on the 16-bit number, if a carry bit higher than the 16-bit number is generated, adding the carry bit to the low-bit data, finishing the calculation of the checksum of the TCP/UDP data load part and obtaining a calculation result R1.
Optionally, the process of adding the calculation result R1 to one end of the data packet in step 1 to obtain a new data packet including a private header includes:
and 103, adding the calculation result R1 to the front end or the tail part of the data packet in a private head form according to the requirement of an actual application scene to obtain the new data packet.
Optionally, after obtaining the new data packet in step 1, the method further includes:
and sending the new data packet to a software layer through DMA after the new data packet is packaged, and meanwhile, placing the R1 value in a private header of the new data packet.
Optionally, the field information of the data packet updated in step 2 includes: source IP, destination IP, source port, destination port, and TCP/UDP header other field information.
Optionally, the method for calculating the pseudo header checksum R2 in step 3 includes:
and accumulating the information of the source IP, the target IP, the protocol number, the length and the like every 2 bytes to obtain the pseudo-header checksum R2.
Optionally, the method for calculating the TCP header checksum R3 in step 3 includes:
and setting the TCP header checksum field to be 0, and then adding every 2 bytes of TCP header information to obtain the TCP header checksum R3.
Optionally, after the step 3, the method further includes:
and 4, sending the new data packet after backfilling and packaging through a network port or other interfaces according to a set strategy.
Optionally, the step 4 includes:
step 401, the software layer consults a predetermined data packet transceiving strategy and determines an interface or a network port for transmitting a network data packet to be transmitted;
and 402, after the interface or the network port for transmission is successfully judged, sending the new data packet.
The invention provides a TCP/UDP checksum determining method based on FPGA hardware acceleration, which improves the traditional software layer checksum calculating process and divides the traditional software layer checksum calculating process into two parts, namely, the checksum calculation of a head pseudo-header information part and the checksum calculation of a data load part. The network data packet analysis, the network data packet splitting, the network data packet check sum calculation, the network data packet check sum result data backfilling, the processes are all completed in a flow line algorithm mode in a data packet scanning process, and compared with a traditional software layer check sum calculation method which needs two times of whole packet scanning, the performance is doubled in a data packet packaging stage.
The FPGA with excellent computing capability is utilized to realize a data load check sum computing part which has a large influence on performance in a check sum computing process, and by means of computing resources on a hardware level, compared with a traditional pure software layer check sum computing method, the method realizes the remarkable increase of the check sum computing rate and remarkably improves the processing efficiency and the check accuracy.
The check sum calculation of the pseudo head and the head information is realized on a software level, and as the head of the data packet is mostly repeated or fixed and has small length, the calculation effect is very little accelerated by calling hardware resources. In some services, TCP/UDP header information of a data packet needs to be modified, the number of calling between software and hardware is increased, time cost brought by the process of transferring instruction information by a plurality of hardware devices is considered, and the step of packaging the data packet is carried out on a software level, so that compared with a novel pure hardware layer check sum calculation method, the method simplifies a plurality of data transfer steps, and the check sum calculation processing rate is increased slightly.
The software and hardware level are communicated with each other in an auxiliary mode, the software level is focused on calculating the pseudo-head and head check sum, the hardware level is focused on calculating the data load check sum, and the software and the hardware are combined to make up the respective defects of the two methods. Compared with a pure software layer checksum algorithm, the method has the advantages that the rate is remarkably advanced, and the performance advantage of hardware equipment is fully utilized; compared with a pure hardware layer checksum algorithm, the method solves the problem of multiple times of calling of hardware equipment resources (only 1 time of FPGA is called) by using system design, and reduces time cost in the process of calling information transmission.
Drawings
FIG. 1 is a flowchart of a TCP/UDP checksum determining method based on FPGA hardware acceleration according to the present invention;
fig. 2 is a software hardware interaction diagram of a method for determining a TCP/UDP checksum based on FPGA hardware acceleration according to an embodiment of the present invention;
fig. 3 (a) is a schematic structural diagram of a standard ethernet packet according to an embodiment of the present invention;
fig. 3 (b) is a schematic structural diagram of an ethernet packet with a private header added according to an embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a flowchart of a method for determining a TCP/UDP checksum based on FPGA hardware acceleration, and fig. 2 is a schematic diagram of software hardware interaction of the method for determining a TCP/UDP checksum based on FPGA hardware acceleration, according to a technical solution disclosed in the present invention, checksum calculation is performed on a TCP or UDP message, and fig. 2 shows an example of a TCP message, and in a specific implementation, a message in an interaction process may be a TCP or UDP message. As can be seen from fig. 1 and fig. 2, given a network communication system, a network communication protocol and an algorithm requirement are determined, and related configuration of an FPGA hardware layer and function implementation of a software layer are completed. And dividing the functions completed by each module. Specifically, the method for determining the TCP/UDP checksum includes:
step 1, the FPGA receives a data packet, checksum calculation is carried out on a TCP/UDP data load part of the data packet to obtain a calculation result R1, and the calculation result R1 is added to one end of the data packet to obtain a new data packet containing a private header.
And 2, the software layer acquires a new data packet from the FPGA, analyzes the new data packet layer by layer and extracts the IP header and TCP/UDP header information, and updates the field information of the new data packet according to the requirement of the service layer custom strategy.
Step 3, extracting a calculation result R1 stored in a private header of the new data packet by the software layer; analyzing the new data packet to obtain IP header and TCP/UDP header information, and calculating to obtain a pseudo header checksum R2 and a TCP header checksum R3; and calculating R4= R1+ R2+ R3, performing shift negation operation on R4 to obtain R5, and backfilling the value of R5 serving as a final checksum calculation result into a checksum field of the new data packet.
The invention provides a TCP/UDP checksum determining method based on FPGA hardware acceleration, which improves the traditional software layer checksum calculating process, and divides the traditional software layer checksum calculating process into two parts, namely, the checksum calculation of a head pseudo-head information part and the checksum calculation of a data load part; the network data packet analysis, the splitting, the check sum calculation respectively, the check sum result data backfilling, the processes are all completed in a one-time data packet scanning process in a pipeline algorithm mode, and compared with a traditional software layer check sum calculation method which needs two times of whole packet scanning, the performance is doubled in a data packet packaging stage.
Example 1
Embodiment 1 provided by the present invention is an embodiment of a TCP/UDP checksum determination method based on FPGA hardware acceleration, and as can be seen from fig. 1 and fig. 2, the embodiment of the TCP/UDP checksum determination method includes:
step 1, the FPGA receives a data packet, performs checksum calculation on a TCP/UDP data load part of the data packet to obtain a calculation result R1, and adds the calculation result R1 to one end of the data packet to obtain a new data packet containing a private header.
In a possible embodiment, the process of calculating and obtaining the calculation result R1 in step 1 includes:
in step 101, the FPGA divides the data load of TCP or UDP in the received data packet into a plurality of groups of 16-bit data, the data with less 16 bits is supplemented with 0 at the lower position, and a plurality of sections of 16-bit data are stored in the array.
And 102, traversing the array, carrying out binary code reversal summation on the 16-bit data, if the carry bit higher than 16 bits is generated, adding the carry bit to the low-bit data, completing the calculation of the checksum on the TCP/UDP data load part and obtaining a calculation result R1.
In a possible embodiment, the process of adding the calculation result R1 to one end of the data packet in step 1 to obtain a new data packet containing a private header includes:
and 103, adding the calculation result R1 (32 bits) to the front end or the tail end of the data packet in a private header mode according to the requirement of an actual application scene to obtain a new data packet.
In a possible embodiment, after obtaining the new packet in step 1, the method further includes:
the new data packet is sent to the software layer through DMA (direct memory access) after being packaged, and meanwhile, the R1 value is placed in a special header of the new data packet.
As shown in fig. 3 (a) and fig. 3 (b) are schematic structural diagrams of a standard ethernet packet and an ethernet packet with a private header added, and as can be seen from fig. 3 (a) and fig. 3 (b), after acquiring a complete network packet, an FPGA processing unit performs checksum calculation on a TCP/UDP data payload portion, and adds a calculation result R1 in the form of a private header to the front or the tail of an ethernet packet according to requirements of an actual application scenario.
And 2, the software layer acquires a new data packet from the FPGA, analyzes the new data packet layer by layer and extracts the IP header and TCP/UDP header information, and updates the field information of the new data packet according to the requirement of the service layer custom strategy.
In a possible embodiment, the field information of the data packet updated in step 2 includes: source IP, destination IP, source port, destination port, and TCP/UDP header other field information (e.g., FLAG, WINDOW, etc. for TCP).
Step 3, extracting a calculation result R1 hidden in a private header of the new data packet by the software layer; analyzing the new data packet to obtain IP header and TCP/UDP header information, and calculating to obtain a pseudo header checksum R2 and a TCP header checksum R3; and calculating R4= R1+ R2+ R3, performing shift negation operation on R4 to obtain R5, and backfilling the value of R5 serving as a final checksum calculation result into a checksum field of the new data packet.
In a possible embodiment, the method for calculating the TCP header checksum R3 in step 3 includes:
and setting the TCP header checksum field to be 0, and then adding every 2 bytes of TCP header information to obtain a TCP header checksum R3.
In step 301, the R1 checksum information stored in the private header, that is, the checksum calculation result of the data payload part, is extracted.
Step 302, analyzing the data packet, calculating the checksum of the dummy header, and accumulating the information such as the source IP, the target IP, the protocol number, the length, and the like every 2 bytes to obtain an intermediate result R2.
Step 303, parsing the data packet, performing checksum calculation on the TCP header, setting the TCP header checksum field to 0, and then adding every 2 bytes of TCP header information to obtain R3.
And step 304, adding the R1, the R2 and the R3 to obtain a result R4, and then shifting and negating the result R4 to obtain a final checksum calculation result R5.
And 305, backfilling the value of the R5 into a checksum field (originally set to be 0) of the TCP/UDP, and finally obtaining a data packet to be sent after checksum calculation is completed.
In a possible embodiment, step 3 is further followed by:
and 4, sending out the new data packet subjected to backfill packaging through the internet access or other interfaces according to a set strategy. The data packet to be sent obtained in step 3 provides data support for step 4,
in one possible embodiment, step 4 includes:
step 401, the software layer refers to a predetermined data packet transceiving policy and determines an interface or a network port for transmitting a network data packet to be transmitted.
Step 402, after successfully judging the interface or network port for transmission, sending a new data packet
The method for determining the TCP/UDP checksum based on FPGA hardware acceleration improves the traditional software layer checksum calculation process, and divides the traditional software layer checksum calculation process into two parts, namely, the checksum calculation of the head pseudo-header information part and the checksum calculation of the data load part. The network data packet analysis, the network data packet splitting, the network data packet check sum calculation, the network data packet check sum result data backfilling, the processes are all completed in a flow line algorithm mode in a data packet scanning process, and compared with a traditional software layer check sum calculation method which needs two times of whole packet scanning, the performance is doubled in a data packet packaging stage.
The FPGA (programmable logic device) with excellent computing capability is utilized to realize a data load check sum computing part which has great influence on performance in the check sum computing process, and by means of computing resources on a hardware level, compared with the traditional pure software layer check sum computing method, the method realizes the remarkable increase of the check sum computing rate and remarkably improves the processing efficiency and the check accuracy.
The check sum calculation of the false head and the head information is realized on a software level, and because the head of the data packet is mostly repeated or fixed and has smaller length, the effect of calling hardware resources to accelerate the calculation is very little. In some services, TCP/UDP header information of a data packet needs to be modified, the number of calling between software and hardware is increased, time cost brought by the process of transferring instruction information by a plurality of hardware devices is considered, and the packaging step of the data packet is carried out on the software level, so that compared with a novel pure hardware layer check sum calculation method, the method simplifies a plurality of data transfer steps, and the check sum calculation processing speed is increased slightly.
The software and hardware level are communicated with each other in an auxiliary mode, the software level is focused on calculating the pseudo-head and head check sum, the hardware level is focused on calculating the data load check sum, and the software and the hardware are combined to make up the respective defects of the two methods. On one hand, compared with a pure software level checksum algorithm, the method has the advantages that the rate is remarkably advanced, and the performance advantage of hardware equipment is fully utilized; compared with a pure hardware layer checksum algorithm, the method solves the problem of multiple times of calling of hardware equipment resources (only 1 time of FPGA is called) by using system design, and reduces time cost in the process of calling information transmission.
It should be noted that, in the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. A TCP/UDP checksum determination method based on FPGA hardware acceleration is characterized by comprising the following steps:
step 1, an FPGA receives a data packet, calculates the checksum of a TCP/UDP data load part of the data packet to obtain a calculation result R1, and adds the calculation result R1 to one end of the data packet to obtain a new data packet containing a private header;
step 2, the software layer acquires the new data packet from the FPGA, analyzes the new data packet layer by layer and extracts the new data packet to obtain IP header information and TCP/UDP header information, and updates the field information of the new data packet according to the requirement of a service layer custom strategy;
step 3, the software layer extracts the calculation result R1 in the private header of the new data packet; analyzing the new data packet to acquire IP header and TCP/UDP header information, and calculating to acquire a pseudo header checksum R2 and a TCP header checksum R3; and calculating R4= R1+ R2+ R3, performing shift negation operation on the R4 to obtain R5, and using the value of the R5 as a final checksum calculation result to be back filled in a checksum field of the new data packet.
2. The method for determining the TCP/UDP checksum according to claim 1, wherein the step of calculating and obtaining the calculation result R1 in step 1 comprises:
step 101, dividing the data load of the TCP or UDP in the received data packet into a plurality of groups of 16-bit data by the FPGA, supplementing 0 to the data with less than 16 bits at a low position, and storing a plurality of sections of 16-bit data in the array;
and 102, traversing the array, carrying out binary inverse sum on the 16-bit number, if a carry bit higher than the 16-bit number is generated, adding the carry bit to the low-bit data, finishing the calculation of the checksum of the TCP/UDP data load part and obtaining a calculation result R1.
3. The TCP/UDP checksum determination method according to claim 1 or 2, wherein the step of adding the calculation result R1 to one end of the data packet in step 1 to obtain a new data packet including a private header includes:
and 103, adding the calculation result R1 to the front end or the tail end of the data packet in a private header mode according to the requirement of an actual application scene to obtain the new data packet.
4. The method for determining the TCP/UDP checksum according to claim 1, wherein after obtaining the new packet in step 1, further comprising:
and sending the new data packet to a software layer through DMA after the new data packet is packaged, and meanwhile, placing the R1 value in a private header of the new data packet.
5. The method according to claim 1, wherein the field information of the data packet updated in step 2 includes: source IP, destination IP, source port, destination port, and TCP/UDP header other field information.
6. The method according to claim 1, wherein the method for calculating the dummy header checksum R2 in step 3 comprises:
and accumulating the information of the source IP, the target IP, the protocol number and the length by every 2 bytes to obtain the pseudo header checksum R2.
7. The method for determining a TCP/UDP checksum according to claim 1, wherein the step 3 of calculating the TCP header checksum R3 comprises:
and setting the TCP header checksum field to be 0, and then adding every 2 bytes of TCP header information to obtain the TCP header checksum R3.
8. The method according to claim 1, wherein said step 3 is further followed by:
and 4, sending the new data packet after backfilling and packaging through a network port or other interfaces according to a set strategy.
9. The method according to claim 8, wherein said step 4 comprises:
step 401, the software layer consults a predetermined data packet transceiving strategy and determines an interface or a network port for transmitting a network data packet to be transmitted;
and 402, after the interface or the network port for transmission is successfully judged, sending the new data packet.
CN202210970606.2A 2022-08-13 2022-08-13 TCP/UDP checksum determining method based on FPGA hardware acceleration Active CN115037814B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210970606.2A CN115037814B (en) 2022-08-13 2022-08-13 TCP/UDP checksum determining method based on FPGA hardware acceleration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210970606.2A CN115037814B (en) 2022-08-13 2022-08-13 TCP/UDP checksum determining method based on FPGA hardware acceleration

Publications (2)

Publication Number Publication Date
CN115037814A CN115037814A (en) 2022-09-09
CN115037814B true CN115037814B (en) 2022-11-01

Family

ID=83131237

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210970606.2A Active CN115037814B (en) 2022-08-13 2022-08-13 TCP/UDP checksum determining method based on FPGA hardware acceleration

Country Status (1)

Country Link
CN (1) CN115037814B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116193000B (en) * 2023-04-25 2023-06-23 湖北微源卓越科技有限公司 FPGA-based intelligent packet rapid forwarding system and forwarding method
CN116455991B (en) * 2023-06-13 2023-08-22 珠海星云智联科技有限公司 Tunnel encapsulation message checksum calculation method and related device
CN117834756A (en) * 2023-12-12 2024-04-05 中科驭数（北京）科技有限公司 Checksum calculation method and device, electronic equipment and storage medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202220417A (en) * 2020-11-05 2022-05-16 財團法人資訊工業策進會 Relay node and packet encapsulation method based on tunnelling protocol

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8726132B2 (en) * 2010-12-14 2014-05-13 International Business Machines Corporation Checksum verification accelerator
US8683307B2 (en) * 2011-05-27 2014-03-25 International Business Machines Corporation Checksum calculation, prediction and validation
CN102404210B (en) * 2011-11-15 2014-04-16 北京天融信科技有限公司 Method and device for incrementally calculating network message check sum
CN103001827B (en) * 2012-11-30 2015-09-23 无锡众志和达数据计算股份有限公司 Based on the inspection of Ethernet bag and the FPGA hardware check method of ten thousand Broadcoms
CN109951253B (en) * 2019-03-14 2021-07-13 北京信而泰科技股份有限公司 Method and device for generating checksum of header of data message
CN114499757B (en) * 2022-01-07 2024-06-18 锐捷网络股份有限公司 Method and device for generating checksum and electronic equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202220417A (en) * 2020-11-05 2022-05-16 財團法人資訊工業策進會 Relay node and packet encapsulation method based on tunnelling protocol

Also Published As

Publication number Publication date
CN115037814A (en) 2022-09-09

Similar Documents

Publication Publication Date Title
CN115037814B (en) TCP/UDP checksum determining method based on FPGA hardware acceleration
EP2189903A2 (en) Barrier synchronization apparatus, barrier synchronization system, and barrier synchronization method
JP6981329B2 (en) Distributed deep learning system
CN112637080B (en) Load balancing processing system based on FPGA
CN111209240B (en) Data transmission method, electronic equipment and storage medium
JP2019144642A (en) Distributed deep learning system
CN114390004A (en) Message processing method, system, device and medium
WO2015105781A1 (en) Methods and systems for flexible packet classification
CN115038125A (en) Data transmission method and device, electronic equipment and storage medium
CN105763375A (en) Data packet transmission method, receiving method and microwave station
US10339091B2 (en) Packet data processing method, apparatus, and system
CN111277449B (en) Safety testing method and device for voice service equipment
EP4328748A1 (en) Data processing method and apparatus, computer device, computer-readable storage medium, and computer program product
US9948756B1 (en) Automated pipeline generation
US20060155771A1 (en) Method and apparatus for processing data
CN113364790B (en) Data transmission method and device
US12002043B2 (en) Method for enabling efficient evaluation of transactions in a distributed ledger network
CN111064673B (en) User plane data integrity protection method and device, electronic equipment and medium
CN111147374A (en) Distributed communication algorithm and device
CN112398735A (en) Method and device for batch processing of messages
CN108134646B (en) A kind of transmission method and device of optical transmission unit frame
KR20160123562A (en) Receiver for processing data packet and data packet processing method of receiver
KR100666997B1 (en) Apparatus and method for processing checksum
CN111865884A (en) Message processing method, device and equipment
CN116996516B (en) Cluster communication method and device, electronic equipment and readable storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant