CN115037574A

CN115037574A - Tunnel management method, FPGA chip and network equipment

Info

Publication number: CN115037574A
Application number: CN202210595789.4A
Authority: CN
Inventors: 左彦峰; 郭建华
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2022-09-09

Abstract

The present specification provides a method for managing tunnels, an FPGA chip, and a network device, the method including: the method comprises the steps of receiving first data sent by a forwarding chip through an Ethernet tunnel, analyzing the first data according to a first preset rule, and selecting a target PCIE tunnel from a plurality of PCIE tunnels to send the first data according to a first analysis result. The method can be used for carrying out tunnel management on the network equipment model of the CPU + FPGA + SWITCH chip.

Description

Tunnel management method, FPGA chip and network equipment

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a method for managing a tunnel, an FPGA chip, and a network device.

Background

With the continuous improvement of the ethernet technology on the bandwidth requirement, the CPU directly provides the ethernet port, and the interface density and the bandwidth requirement cannot be met, and a typical network device model is gradually formed by using the CPU + FPGA (Field Programmable Gate Array) + SWITCH chip.

Disclosure of Invention

The embodiment of the disclosure provides a method for managing a tunnel, an FPGA chip and network equipment.

The embodiment of the disclosure provides a method for managing a tunnel, which is applied to an FPGA chip and comprises the following steps:

receiving first data sent by a forwarding chip through an Ethernet tunnel;

analyzing the first data according to a first preset rule, and selecting a target PCIE tunnel from a plurality of PCIE tunnels according to a first analysis result to send the first data;

wherein the first parsing result comprises: a size and/or priority of the first data.

Optionally, the method further includes:

acquiring attribute information of the PCIE tunnels;

the attribute information includes: resource information of each PCIE tunnel and/or priority of each PCIE tunnel.

Wherein, the selecting a target PCIE tunnel from the PCIE tunnels according to the first parsing result to send the first data includes:

and selecting the PCIE tunnel corresponding to the attribute information matched with the first analysis result as a target PCIE tunnel according to the first analysis result and the attribute information of the plurality of PCIE tunnels.

The method further comprises the following steps: receiving second data sent by the processing chip through the PCIE tunnel;

and analyzing the second data through a second preset rule, and selecting a target Ethernet tunnel from the plurality of Ethernet tunnels according to a second analysis result to send the second data.

After receiving the second data sent by the processing chip through the PCIE tunnel, the method further includes:

and sending the second data to a queue of the corresponding PCIE tunnel according to the resource information of each PCIE tunnel and/or the priority of each PCIE tunnel.

The method can realize the management of the Ethernet tunnel and the PCIE tunnel in the network equipment.

This disclosed embodiment still provides an FPGA chip, and this FPGA chip includes: a first chip having a first chip area and a second chip area,

the first chip is used for receiving first data sent by the forwarding chip through the Ethernet tunnel;

the first chip is further configured to analyze the first data according to a first preset rule, and select a target PCIE tunnel from the PCIE tunnels according to a first analysis result to send the first data;

The FPGA chip is also connected with the register;

the FPGA chip acquires attribute information of the PCIE tunnels from the register;

And the FPGA chip selects a PCIE tunnel corresponding to the attribute information matched with the first analysis result as a target PCIE tunnel according to the first analysis result and the attribute information of the PCIE tunnels.

The FPGA chip further comprises: a second chip having a second chip-shaped surface,

the second chip is used for receiving second data sent by the processing chip through the PCIE tunnel;

the second chip is further configured to parse the second data according to a second preset rule, and select a target ethernet tunnel from the multiple ethernet tunnels according to a second parsing result to send the second data.

In this embodiment, an FPGA chip is provided, where management of an ethernet tunnel and a PCIE tunnel in a network device is implemented by the FPGA chip.

Based on the foregoing embodiments, an embodiment of the present disclosure further provides a network device, where the FPGA chip in any of the foregoing embodiments is installed in the network device, so as to implement management of an ethernet tunnel and a PCIE tunnel in the network device.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a logic diagram of a network device model according to an embodiment of the present disclosure.

Fig. 2 is a logic diagram of an ethernet port receiving model of a network device according to an embodiment of the present disclosure.

Fig. 3 is a logic diagram of a method for managing a tunnel according to an embodiment of the present disclosure.

Fig. 4 is a logic diagram of an ethernet port receiving model of a network device according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the claims that follow.

The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present description. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

In a network device model constructed based on a CPU + FPGA + SWITCH chip, the CPU and the FPGA are connected through multiple channels, and the CPU software forwarding bandwidth can be increased, as shown in fig. 1, a typical network device model has a CPU chip connected to an FPGA chip and a SWITCH chip, an ethernet tunnel is formed between the SWITCH chip and the FPGA chip, and a PCIE tunnel is formed between the FPGA chip and the CPU chip.

As shown in fig. 2, one side of the SWITCH chip is connected to the lines 1 to Z, where each line is connected to a corresponding terminal, and the other side of the SWITCH chip is connected to the FPGA chip through an ethernet tunnel (ethernet channel).

In this embodiment, the bandwidth between the CPU and the FPGA (PCIE tunnel) and the bandwidth between the FPGA and the SWITCH (ethernet tunnel) may be increased, so as to improve the forwarding performance of the whole device, but the PCIE channels and the ethernet channels are bound one to one, and the traffic cannot share the effective load.

In one case, in case the PCIE tunnel bandwidth is greater than the ethernet tunnel bandwidth: traffic in the sending direction PCIE1 cannot be load-shared to a channel (e.g. ethernet channel N) other than ethernet channel 1 (ethernet channel 1), so that the phenomenon that ethernet channel 1 is congested and other ethernet channels are idle occurs

In another case, in case that the bandwidth of the ethernet tunnel is greater than the bandwidth of the PCIE tunnel: after the traffic in the receiving direction reaches the ethernet channel 1, the traffic cannot be load-shared to a channel (for example, the PCIE channel N) other than the PCIE1, so that the phenomenon occurs that the PCIE1 channel is congested, and other PCIE channels are idle.

In order to solve the above technical problem, an embodiment of the present disclosure provides a method for managing a tunnel, where the method is applied to an FPGA chip, and as shown in fig. 3, the method includes:

s301, receiving first data sent by a forwarding chip through an Ethernet tunnel;

s302, analyzing the first data according to a first preset rule, and selecting a target PCIE tunnel from a plurality of PCIE tunnels according to a first analysis result to send the first data;

wherein the first parsing result comprises: a size and/or a priority of the first data.

In this embodiment, the forwarding chip may be a SWITCH chip, and in step S301, the SWITCH chip receives the first data from the terminal through the line and sends the first data to the FPGA chip through the ethernet.

In this embodiment, a first chip may be disposed in the FPGA chip, and the first chip is configured to parse data and control the capability of scheduling the PCIE tunnel.

In step S302, the first preset rule includes: a designated field of data, a size of data, a priority of data, and the like. After the FPGA chip receives the first data, the first chip analyzes the data according to the first preset rule and obtains a corresponding first analysis result.

In order to implement management of PCIE tunnels, the first chip is connected to a register in the FPGA chip, and acquires attribute information of each PCIE tunnel from the register of the FPGA chip (the register is not limited to be set by the FPGA chip, and this is only illustrated by an example), where the attribute information may include resource information of the PCIE tunnel (which may include a bandwidth size of the PCIE tunnel, a size of a current bearer service, and the like) and/or a priority of the PCIE tunnel.

In this embodiment, after the first chip obtains the first analysis result, the first chip may find the target attribute information that can best satisfy the first analysis result from the attribute information of each PCIE tunnel, for example, if the first analysis result determines that the first data needs 10M of bandwidth, it may determine whether bandwidth satisfying 10M data transmission exists in the attribute information of each PCIE tunnel, and determine that bandwidth satisfying 10M data transmission as the target attribute information.

After the target attribute information is determined, a target PCIE tunnel corresponding to the target attribute information is found, and the first data is sent to the CPU through the target PCIE tunnel.

It can be seen from the above embodiments that, in this embodiment, the FPGA chip may dynamically select a PCIE tunnel suitable for data transmission from among PCIE tunnels according to data received from the ethernet tunnel, and does not need to forcibly configure a corresponding relationship between the ethernet tunnel and the PCIE tunnel, so that on one hand, the configuration cost is saved, and on the other hand, the situation of tunnel resource waste or transmission congestion caused by unequal ethernet tunnel and PCIE tunnel resources is avoided.

In the above embodiment, a data transmission method from a terminal to a CPU is described, and in practical application, there is also a case where the CPU sends data like a data terminal, which specifically includes:

the FPGA chip receives second data sent by the processing chip through the PCIE tunnel;

In this embodiment, the second preset rule may include: a designated field of data, a size of data, a priority of data, and the like. As shown in fig. 4, a second chip may also be provided in the FPGA chip.

In an example, the second chip receives second data sent by the CPU side, may analyze the second data, obtain a second analysis result (the same general concept as the first solution result, which is not described here again), and send the second data to the PCIE tunnel (in the PCIE tunnel queue) according to the second analysis result. In another example, the second chip sends the second data to the designated lane queues according to the destination lanes (each PCIE tunnel may send the second data to all queues).

Then, the first chip obtains the analysis result of the second data and the attribute information of each ethernet tunnel, determines a target ethernet tunnel (the concept is the same as that of the target PCIE tunnel and is not repeated), and sends the second data to the terminal through the target ethernet tunnel.

It can be seen from the above embodiments that, in the process of data from the CPU to the terminal, according to the present scheme, a corresponding tunnel can be dynamically selected to transmit data according to the data and the attribute information of each ethernet tunnel and PCIE tunnel, so that, on one hand, the configuration cost is saved, and on the other hand, the situation of tunnel resource waste or transmission congestion caused by unequal ethernet tunnel and PCIE tunnel resources is avoided.

The embodiment of the present disclosure further provides an FPGA chip, where the FPGA chip includes: first chip

The FPGA chip is also connected with the register; the FPGA chip acquires attribute information of the PCIE tunnels from the register;

This FPGA chip still includes: the second chip is used for receiving second data sent by the processing chip through the PCIE tunnel;

The embodiment of the disclosure also provides a network device, which includes the FPGA chip described above, where the FPGA chip includes a first chip and/or a second chip.

It should be noted that the first chip and the second chip may be the same chip or different chips in practical applications.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following the general principles of the specification and including such departures from the present disclosure as come within known or customary practice in the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.

It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the description is limited only by the appended claims.

The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A method for managing tunnels is applied to an FPGA chip, and comprises the following steps:

receiving first data sent by a forwarding chip through an Ethernet tunnel;

2. The method of claim 1, further comprising:

acquiring attribute information of the PCIE tunnels;

3. The method of claim 2, wherein the selecting a target PCIE tunnel from a plurality of PCIE tunnels according to the first parsing result to send the first data includes:

4. The method of claim 1, further comprising:

receiving second data sent by the processing chip through the PCIE tunnel;

5. The method according to claim 4, wherein after receiving the second data sent by the processing chip through the PCIE tunnel, the method further comprises:

6. An FPGA chip, comprising: a first chip having a first chip area and a second chip area,

7. The FPGA chip of claim 6, wherein the FPGA chip is further connected to a register;

8. The FPGA chip of claim 7, wherein the FPGA chip selects, according to the first analysis result and attribute information of the plurality of PCIE tunnels, a PCIE tunnel corresponding to the attribute information matched with the first analysis result as a target PCIE tunnel.

9. The FPGA chip of claim 6, further comprising: a second chip (a second chip) having a first chip,

the second chip is further configured to analyze the second data according to a second preset rule, and select a target ethernet tunnel from the multiple ethernet tunnels according to a second analysis result to send the second data.

10. A network device, characterized in that the network device comprises: the FPGA chip of any one of claims 6 to 9.