CN115037382B - Shift operation method and device of self-adaptive channel equalization algorithm - Google Patents
Shift operation method and device of self-adaptive channel equalization algorithm Download PDFInfo
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Abstract
The invention relates to a shift operation method and a device of a shift operation method of a self-adaptive channel equalization algorithm, wherein the method comprises the following steps: taking the product of the real part of the polarized input signal and the first displacement as the value of the shifter; taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement; acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state; and acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch. The problem of the large number of multipliers used in the related art can be solved.
Description
Technical Field
The present invention relates to the field of digital signal processing technologies, and in particular, to a shift operation method and apparatus for a self-adaptive channel equalization algorithm.
Background
With the rapid development of network services and the continuous update of communication demands, the demands for improving the communication rate in other scenarios outside the backbone network are also increasing, such as short-distance communication scenarios like data centers, access networks, etc. The coherent optical communication technology can fully exert the advantage of high speed, and plays a role in a short-distance communication scene. However, due to the higher demands of short-range scenes for low cost and low power consumption, the conventional complex coherent optical communication technology is difficult to directly apply. The traditional coherent optical communication technology is high in complexity of a system and an algorithm, and needs to rely on a complex digital signal processing (Digital Signal Processing, DSP) chip, so that the large-scale application of the coherent optical communication technology in a short-distance scene is restricted.
The adaptive channel equalization algorithm in the related art adopts a butterfly algorithm structure of 2×2 multiple input multiple output (Multiple Input Multiple Output, MIMO) based on a complex multiplier, and consists of 4N-order complex calculation modules. For an N-order 2×2 butterfly adaptive equalization module, each calculation requires N complex multipliers, and four paths consume a total of 4N complex multipliers. Because the multiplier is a scarce hardware resource, compared with other algorithm resources such as adders or comparators, the realization difficulty is higher, and therefore the cost of chips with more multipliers is higher. Meanwhile, a large number of multipliers can cause the increase of chip power consumption, which is unfavorable for the development of application of the high-speed coherent optical communication technology in a short-distance scene.
Disclosure of Invention
The embodiment of the invention provides a shift operation method and a shift operation device of a self-adaptive channel equalization algorithm, which are used for solving the problem that multipliers in the related art are used in a large number.
The embodiment of the invention provides a shift operation method of a self-adaptive channel equalization algorithm, which is characterized by comprising the following steps:
taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0;
taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state;
and acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch.
In some embodiments, the step of taking the product of the real part of the polarized input signal and the first displacement as the value of the shifter includes:
setting a set stepping number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M;
the first displacement is a m Wherein a is a number greater than 0 and less than 1;
and multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter.
In some embodiments, the setting the enable switch according to the bit distribution of the binary number includes the steps of:
setting enabling switches on bit positions of the binary numbers correspondingly, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
the corresponding enable switch state is on when the bit is 1.
In some embodiments, the obtaining the substitution result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the enabling switch output value includes the steps of:
performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient;
and taking the result after sign bit compensation as a substitute result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient.
In some embodiments, the sign bit compensation for the accumulated value of the enable switch output value according to the sign bit of the real part of the equalization coefficient includes the steps of:
if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
On the other hand, an embodiment of the present invention provides a shift operation device of an adaptive channel equalization algorithm, which is characterized in that the shift operation device includes:
a displacement module for:
taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0;
taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
a gating module for:
acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state;
and acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch.
In some embodiments, the displacement module is further configured to:
setting a set stepping number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M;
the first displacement is a m Wherein a is a number greater than 0 and less than 1;
and multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter.
In some embodiments, the gating module is further configured to:
setting enabling switches on bit positions of the binary numbers correspondingly, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
the corresponding enable switch state is on when the bit is 1.
In some embodiments, the gating module is further configured to:
performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient;
and taking the result after sign bit compensation as a substitute result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient.
In some embodiments, the gating module is further configured to:
if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
The embodiment of the invention replaces the multiplication operation of the original polarization input signal real part and the original polarization input signal real part by utilizing the mode of shifting and accumulating the polarization input signal real part by utilizing the equalization coefficient real part, thereby realizing the self-adaptive channel equalization algorithm by replacing a multiplier in the self-adaptive channel equalization algorithm by using simple logic units such as an adder, a shifter, an enabling switch and the like, and achieving the purpose of reducing the cost and the power consumption of a receiving end DSP without the participation of the multiplier in the algorithm.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a shift operation method of an adaptive channel equalization algorithm according to an embodiment of the present invention;
fig. 2 is a block diagram of a conventional 2×2 butterfly adaptive channel equalization algorithm according to an embodiment of the present invention;
FIG. 3 is a block diagram of an N-order complex computing module in a conventional 2×2 butterfly adaptive channel equalization algorithm according to an embodiment of the present invention;
FIG. 4 is a block diagram illustrating a complex multiplier in an N-level complex calculation module according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating a structure of each logic unit in a shift operation method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a shift operation device of an adaptive channel equalization algorithm according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a shift operation method of an adaptive channel equalization algorithm, which includes the steps of:
s100, taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0;
s200, taking a modulus value according to a real part of an equilibrium coefficient from the polarized input signal to the polarized output signal, and calculating a product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
s300, obtaining binary numbers of products of the modulus value and the second displacement, and setting enabling switches according to bit distribution of the binary numbers, wherein the enabling switches are used for allowing the numerical value of the shifter to pass when in an on state;
s400, acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch.
Needs to be as followsIt is described that, as shown in fig. 2 and 3, for the conventional 2×2 butterfly adaptive channel equalization algorithm, the algorithm is composed of 4N-order complex computing modules. Einx and Einy are X, Y two-path polarized input complex signals, F xx ，F yx ，F xy ，F yy Four paths of complex coefficients are respectively updated in real time by a coefficient updating algorithm. The input complex signal is multiplied by the complex coefficient and summed to obtain an output signal. The adaptive channel equalization module can compensate intersymbol interference caused by chromatic dispersion, polarization-related loss, polarization-related dispersion and damage of various devices, complete polarization demultiplexing and recover X, Y two paths of polarized signals Eoutx and eoutty. The calculation of the 2×2 butterfly adaptive channel equalization algorithm is shown in formulas (1) and (2):
wherein Einx and Einy are respectively the input of X, Y polarized signals, eoutx and Eouty are respectively the output of the equalization algorithm module, F is the update coefficient of the equalization algorithm module, and the upper right small mark indicates the input and output directions of the polarized states, wherein F xx Is the coefficient of the X-polarized input signal to the X-polarized output signal, F xy Is the coefficient of the X-polarized input signal to the Y-polarized output signal, F yx Is the coefficient of the Y polarized input signal to the X polarized output signal, F yy Is the coefficient of the Y polarized input signal to the Y polarized output signal. i is the number of the equalization module series, and the value range is 1 to N. For an N-order 2×2 butterfly adaptive equalization module, each calculation requires N complex multipliers, and four paths consume a total of 4N complex multipliers. The multiplier is a scarce hardware resource, so that the implementation difficulty is higher compared with other algorithm resources such as adders or comparators, and therefore, the cost of chips with more multipliers is higher. At the same time, the use of a large number of multipliers can cause the increase of the power consumption of the chip, which is disadvantageousThe method is applied to a short-distance scene in a high-speed coherent optical communication technology.
The embodiment of the invention replaces the multiplication operation of the original polarization input signal real part and the original polarization input signal real part by utilizing the mode of shifting and accumulating the polarization input signal real part by utilizing the equalization coefficient real part, thereby realizing the self-adaptive channel equalization algorithm by replacing a multiplier in the self-adaptive channel equalization algorithm by using simple logic units such as an adder, a shifter, an enabling switch and the like, and achieving the purpose of reducing the cost and the power consumption of a receiving end DSP without the participation of the multiplier in the algorithm.
In some embodiments, S100 comprises the steps of:
s110, setting a step number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M;
s120, the first displacement is a m Wherein a is a number greater than 0 and less than 1;
s130, multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter.
Preferably, a=2 is taken, and therefore, the first displacement amount is a set of values consisting of 1, 1/2, 1/4, 1/8.
In some embodiments, setting the enable switch according to the bit distribution of the binary number in S300 includes the steps of:
s310, correspondingly setting enabling switches on bit positions of the binary numbers, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
s320, the corresponding enabling switch state is on when the bit is 1.
In some embodiments, S400 comprises the steps of:
s410, performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient;
s420, taking the result after sign bit compensation as a substitute result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient.
Further, S410 includes the steps of:
s411, if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and S412, if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
In a specific embodiment, for the case of providing a complex multiplier with 1 number of 4 real multipliers (including another case of forming a complex multiplier with 1 number of 3 real multipliers) as shown in fig. 4, the shift operation method provided by the embodiment of the present invention may be used to perform substitution processing. As shown in fig. 5, the real part Einx1_re of the input signal is polarized with the first order X and the corresponding real part coefficient F xx The multiplication of 1_re is used as a replacement object, and the shift operation method comprises the following steps:
s1: the einx1_re is sequentially shifted to the right by 0 to M bits to obtain einx1_re, einx1_re/2, einx1_re/4 M The value of the shifter is correspondingly input to the enabling switch set in the step S3.
The magnitude of the M value determines the accuracy of the shift operation module, and the greater M, the higher the accuracy. From the practical test result, the value of the QPSK modulation format M may be selected to be more than 6.
S2: acquisition of F xx The modulus Mod of 1_re is shifted left by M bits to obtain Mod×2 M Is a numerical value of (2).
S3: mod×2 M After the numerical value of (a) is converted into a binary number, enable switches En0, en1 to EnM are respectively arranged on Bit bits of the binary number by making the binary number Mod multiplied by 2 M The highest control En0, mod×2m, and the next highest control En1 M Is the lowest order control EnM of (c). The enabling switches En0, en1 to EnM are sequentially used for controlling the values of the displacers obtained when the right shift is 0 bit, the right shift is 1 bit to the right shift is M bit in the S1.
It should be noted that the enable switch may be set to be turned on when the corresponding Bit is 1, and the enable switch may be set to be turned on when the Bit is 0The switch can be turned off. In this way, by F xx 1_re controls the state of the m+1 enable switches, and the value of the shifter can pass only when the enable switch is turned on.
S4: the m+1 number values einx1_re, einx1_re/2, einx1_re/4 obtained in step S1 are combined M M+1 enable switch outputs determined in step S3 and according to F xx 1_re, compensating the sign bit of the output data of step S3, if F xx 1_re is negative, the output data is inverted, if F xx 1_re is regular output data.
Based on the shift operation of the embodiment, the original Einx1_re and F are compared xx Multiplication by 1_re, approximated for a method according to F xx 1_re performs shift and accumulate completed operations on Einx1_re. The method and the device realize the reduction of the use quantity of multipliers in the DSP and achieve the purpose of reducing the power consumption and the cost of a receiving end.
As shown in fig. 6, an embodiment of the present invention further provides a shift operation device of an adaptive channel equalization algorithm, which includes:
a displacement module for:
taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0;
taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
a gating module for:
acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state;
and acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch.
In some embodiments, the displacement module is further to:
setting a set stepping number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M;
the first displacement is a m Wherein a is a number greater than 0 and less than 1;
and multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter.
In some embodiments, the gating module is further configured to:
setting enabling switches on bit positions of the binary numbers correspondingly, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
the corresponding enable switch state is on when the bit is 1.
In some embodiments, the gating module is further configured to:
performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient;
and taking the result after sign bit compensation as a substitute result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient.
In some embodiments, the gating module is further configured to:
if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer-readable storage media (or non-transitory media) and communication media (or transitory media).
It should be noted that in the present invention, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. The shift operation method of the adaptive channel equalization algorithm is characterized by comprising the following steps:
taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0; the step of taking the product of the real part of the polarized input signal and the first displacement as the value of the shifter comprises the following steps: setting a set stepping number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M; the first displacement is a m Wherein a is a number greater than 0 and less than 1; multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter;
taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state;
acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch; the step of obtaining a substitution result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch comprises the following steps: performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient; and taking the result after sign bit compensation as a substitute result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient.
2. The method for shift operation of an adaptive channel equalization algorithm of claim 1,
setting enabling switches on bit positions of the binary numbers correspondingly, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
the corresponding enable switch state is on when the bit is 1.
3. The shift operation method of an adaptive channel equalization algorithm according to claim 1, wherein said sign bit compensation of said accumulated value of enabling switch output values according to sign bits of real parts of said equalization coefficients comprises the steps of:
if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
4. A shift operation device of an adaptive channel equalization algorithm, comprising:
a displacement module for:
taking the product of the real part of the polarized input signal and a first displacement as a value of a shifter, wherein the first displacement is M+1 values which are larger than 0 and smaller than 1, and M is an integer which is larger than or equal to 0;
taking a modulus value according to the real part of the equalizing coefficient from the polarized input signal to the polarized output signal, and calculating the product of the modulus value and a second displacement, wherein the second displacement is the reciprocal of the minimum value in the first displacement;
the displacement module is also used for:
setting a set stepping number M, and acquiring a corresponding first displacement under the condition that M sequentially takes 0 to M;
the first displacement is a m Wherein a is a number greater than 0 and less than 1;
multiplying the real part of the polarized input signal by a first displacement when m takes different values in sequence, and taking the product as the value of a shifter;
a gating module for:
acquiring binary numbers of the product of the modulus value and the second displacement, and setting an enabling switch according to bit distribution of the binary numbers, wherein the enabling switch is used for allowing the numerical value of the shifter to pass when in an on state;
acquiring a substitution result of multiplication operation of the real part of the polarized input signal and the real part of the equalizing coefficient based on the accumulated value of the output value of the enabling switch;
the gating module is further configured to:
performing sign bit compensation on the accumulated value of the output value of the enabling switch according to the sign bit of the real part of the equalizing coefficient;
and taking the result after sign bit compensation as a substitute result of multiplying the real part of the polarized input signal and the real part of the equalizing coefficient.
5. The shift operation device of an adaptive channel equalization algorithm of claim 4, wherein said gating module is further configured to:
setting enabling switches on bit positions of the binary numbers correspondingly, so that enabling switches on the highest bit position to the lowest bit position correspondingly control on-off of the numerical value of the shifter when M is 0 to M in sequence;
the corresponding enable switch state is on when the bit is 1.
6. The shift operation method of an adaptive channel equalization algorithm of claim 4, wherein said gating module is further configured to:
if the sign bit is negative, inverting the accumulated value of the output value of the enabling switch, and taking the inverted result as the result after sign bit compensation;
and if the sign bit is positive, directly taking the accumulated value of the output value of the enabling switch as the result after sign bit compensation.
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| CN109314583A (en) * | 2016-07-15 | 2019-02-05 | 华为技术有限公司 | The high capacity light data transmission that use intensity is modulated and directly detected |
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