CN115037365A - High-speed expandable encoder of high-power free space optical communication system - Google Patents
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Abstract
The invention discloses a high-speed expandable encoder of a high-power free space optical communication system. The encoder is composed of an Ethernet input interface unit, a decoding unit, an encoding mode configurable unit, a TTL high-speed signal driving output unit, a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit. The high-speed TTL high-speed data coding and high-power constant current control circuit is characterized in that a data stream is accessed from an Ethernet network interface, is subjected to module unpacking, selects coding modes such as polarization code coding and Manchester coding by using a dial switch, performs high-speed data coding to output high-speed TTL driving signals, drives a high-power constant current unit through a high-speed photoelectric conversion isolation unit, outputs multiple groups of constant large currents, and controls an external light source circuit to stably work for a long time. The invention has the characteristics of high-speed transmission, stable work, large driving power, free expansion and the like, can provide high-speed and stable light source driving, and can drive external light source circuits of different scales by connecting a plurality of encoders with a switch for expansion and assembly.
Description
Technical Field
The application relates to the aspect of free space optical communication, in particular to a high-speed expandable encoder of a high-power free space optical communication system, which is used for driving a light source circuit at a transmitting end.
Background
Free space optical communication is a novel communication technology which takes light waves as a transmission carrier of signals and takes free space (including vacuum and atmosphere) as an information propagation medium, and can realize interconnection communication among single point-to-single point, single point-to-multipoint and multipoint in space. This technology combines the features of optical communication and wireless communication, and is also called wireless optical communication. Compared with the traditional microwave communication technology, the free space optical communication technology has the advantages of high modulation rate, wide frequency band, no occupation of frequency spectrum resources and the like, and the used light source has better directivity and is favorable for information confidentiality. Compared with the optical fiber communication technology, the free space optical communication does not need to lay special optical fibers, so that the free space optical communication technology has the advantages of lower cost, convenience in construction, easiness in popularization and the like, and the problem of 'last kilometer' left by the optical fiber communication technology is solved. The light source used for free light communication has better directivity, so that the free light communication also has good confidentiality and directivity, and information is not easy to leak and intercept; and it has certain dilatation, the equipment upgrade of being convenient for. However, in practical applications, the free space optical communication system is sensitive to the atmosphere and is susceptible to interference in a complex environment, so that solving the interference is a key issue that needs to be paid attention to in practical applications.
Compared with the foreign countries, the development is late in the research of free space optical communication technology. Since the 90 s, domestic research on this technology has been gradually expanding. In the course of decades of development, free space optical communication technology has continuously made breakthroughs in several aspects such as transmission rate, transmission distance, transmission reliability and the like. At present, the free space optical communication technology has great value not only in the civil field, but also in the military field, and has wide application in the aspects of local area network interconnection, metropolitan area network expansion, zero-kilometer access of a broadband network, wireless base station data return and the like. When the electromagnetism is silent, the free space optical communication technology can be used as an important guarantee for battlefield communication. Therefore, the free space optical communication technology has wide application prospect and huge market potential.
The free space optical communication system mainly comprises a transmitting end and a receiving end. The basic flow of the transmitting end is as follows: an operator inputs a signal to be transmitted at the transmitting end, and the light source sends a corresponding optical signal to be received by the receiving end through the processes of coding, signal conversion and the like. In this process, the light source at the emitting end is required to have the characteristics of high speed, stability, high power and the like during operation, and a proper driving scheme and a proper coding scheme of the emitting end need to be selected and designed.
The laser has the advantages of good monochromaticity, strong directivity, high brightness, good color, low energy consumption, small volume and the like, and is a commonly used light source selection in laser communication. When the light source is large in scale, a Light Emitting Diode (LED) with equivalent performance and lower cost can be selected as the light source in consideration of the higher cost of the light source. Light Emitting Diodes (LEDs) have a lower cost, longer lifetime and better safety than lasers and are therefore a good choice for free space optical communication system transmitter side light sources. However, the main problem of the Light Emitting Diode (LED) is that the LED is susceptible to temperature during light emitting, and the temperature of the LED gradually increases with the increase of the light emitting time, which causes the resistance of the LED to gradually decrease, the operation stability to become weak, and the operation life to be shortened. Therefore, in the driving scheme, a Light Emitting Diode (LED) is selected as a light source, and a driving circuit which is stable in operation and has a high power characteristic needs to be designed in consideration of the operating life of the light source.
Manchester coding is a common coding method in ethernet, and "0" and "1" are represented by high-low transition of level. In the data transmission process, a level jump must be carried out in the middle of each bit, and the level jump can be used as a clock signal and a data signal, so that a self-synchronizing coding mode can be realized, and a separate synchronizing signal does not need to be sent out. But the frequency of the coded signal sequence is doubled, and the data transmission rate is only half of the original rate.
The polar code is a linear channel coding method proposed by Arikan in 2008, and is a coding method which is theoretically proved to reach shannon limit at present. Compared with the conventional channel coding, the coding complexity of the polar code is lower, and as the code length increases, the decoding accuracy rate will also be higher, so in the future communication field, the development of the polar code will become a research hotspot in the coding field and play an important role. For hardware coding, the increase of the code length increases the implementation complexity of the hardware coding, and the problem of hardware complexity is solved at first.
The invention discloses a high-speed expandable encoder of a high-power free space optical communication system, which consists of an Ethernet input interface unit, a decoding unit, an encoding mode configurable unit, a TTL high-speed signal driving output unit, a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit. The method comprises the steps of reading a TCP/IP input data stream of an Ethernet network interface, entering a decoding unit to unpack the TCP/IP data stream, entering an encoding mode configurable unit to carry out high-speed encoding according to the received network data stream, outputting a high-speed TTL driving signal, driving a high-power constant current unit through a high-speed photoelectric conversion isolation unit, and outputting a plurality of groups of constant large currents, so that an external light source circuit is controlled to emit light.
The code mode selection in the code mode configurable unit is controlled through the dial switch, and the light source signal modulation is realized through Manchester coding, polar code coding and the like. By providing stable constant large current for the LED lamp bank in the external light source circuit, the light source at the transmitting end can stably work for a long time, and the safety of the system is improved. And the external light source circuit driving of different scales can be realized by the expanded combination of a plurality of encoders connected with the switch.
In the aspect of light source driving, for example, a patent publication with an application number of "CN 202110390423.9" discloses a MIMO high-speed array type blue-green LED light source for optical communication, which includes a signal input adjusting module, a phase adjusting module, a power module, an LED driving circuit, an LED lamp bead, and a condenser lens. The LED driving circuit receives the signals after the phase is adjusted, and outputs large-current driving signals to the LED lamp beads based on the power supply module. The LED driving circuits are in parallel connection, only one LED lamp bead is controlled and driven independently, namely each LED lamp bead is provided with one corresponding LED driving circuit, the efficiency of the emitting light source is low, more driving circuit units are needed when the emitting of a high-power light source is realized, and the cost is higher.
In terms of driving the light source, a driver of a visible light communication system is disclosed in patent publication No. CN202010531717.4, for example. The driver adopts a mode of alternately providing 0V and light source working voltage at two ends of the LED, all energy of the driver is used for communication, the lighting function can be realized without a power amplifier, the size is reduced, and the loss is reduced. However, in the process of alternately using different working voltages, large current fluctuation is easily generated, which causes instability of the light source and shortens the service life of the system.
In terms of driving the light source, a patent publication with the application number "CN 201911172752.5" discloses a light source for a multi-channel visible light communication system. The 4 LED driving modules respectively convert the 4 paths of modulation signals into current signals, send the current signals to the 4 monochromatic LED modules, convert the current signals into 4 paths of optical signals, and obtain the illumination light with uniform color by mixing the colors of the monochromatic light. The alternating current driving circuit adopts MOS driving and converts a modulation signal into an alternating current signal which can be superposed on direct current; the direct current driving circuit adopts a DC/DC voltage reduction circuit and outputs constant direct current to drive the LED to emit light; the superposition of direct current driving and alternating current driving signals is completed through a Bias-tee signal coupling circuit, so that the light emitting and the communication of the LED are driven. The signal superposition mode is adopted to modulate the signal, and the complexity of the circuit is increased.
In terms of driving of the light source, patent publication No. CN202110339751.6, for example, discloses a control device for a light source driver in an optical communication transmitter and a control method thereof. The light source driver is used for providing bias current and modulation current for driving the light emitting component to emit light, and is connected to the light emitting component to generate an optical signal. And the signal is modulated in a signal superposition mode, so that the complexity of the circuit is increased.
In terms of an encoder, a general encoder circuit for LED light fixtures for visible light communication is disclosed in patent publication No. CN 201710609319.8. The MCU is used for periodically sending out a control signal, and the LED lamp is controlled to be on or off through the two MOS tubes through amplification and driving of the driving chip, so that stable power supply current is provided for the LED lamp. The invention generates and modulates the control signal, which can effectively improve the system efficiency, and is different from the method adopted by the application.
In the aspect of polar code encoding, for example, a patent publication with an application number of "CN 201810107445.8" discloses a hardware implementation method of a polar code encoder based on an FPGA. The method only needs to perform the operation of generating the first column of the matrix, then obtains the whole coding result according to the rule, solves the problem of parallel operation, introduces a ROM table look-up method as an initial computing unit, and improves the overall operation speed of the encoder. The invention introduces the optimization of the coding algorithm, but when the ROM table look-up method is used, the bit number of the table needs to be specified in advance according to the coding bit number, the calculation and the storage are good, the flexibility is poor, and the use is inconvenient.
In the aspect of polarization code encoding, for example, patent publication No. CN202010684940.2 discloses a high-performance polarization encoding method and encoder for satellite discontinuous communication. The method mainly comprises the following steps: CRC encoding module, FIFO, first-stage polarization code encoding module, second-stage polarization code encoding module. The method comprises the steps of firstly carrying out sub-polarization code encoding, then carrying out XOR operation on code blocks of the first part of codes according to a butterfly diagram, and realizing high-performance operation through parallel operation of the two parts, thereby meeting the requirement on transmission reliability in satellite communication. The method combining the generation matrix calculation and the butterfly diagram calculation is adopted, so that the resource occupation in the generation matrix calculation is reduced, but the problem of time delay in the butterfly diagram calculation is reserved.
Disclosure of Invention
The invention designs a high-speed expandable encoder of a high-power free space optical communication system, which is characterized in that a data stream is accessed from a gigabit network interface, and a constant large-current control signal is output for an external light source circuit after high-speed data encoding; the high-speed expandable encoder comprises an Ethernet input interface unit, a decoding unit, an encoding mode configurable unit, a TTL high-speed signal driving output unit, a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit;
the work of the high-speed expandable encoder of the high-power free space optical communication system comprises the following processes:
firstly, reading TCP input data stream of an Ethernet network interface, and entering a decoding unit to unpack the TCP/IP data stream; selecting coding modes such as polarization code coding or Manchester coding and the like through a dial switch, and entering a next coding unit for coding according to the received network data stream; then outputting a high-speed TTL driving signal according to the coding sequence; finally, the high-power constant current unit is driven by the isolation unit; the high-power constant current driving unit outputs a plurality of groups of constant heavy currents according to the data signals output by the isolation unit, so that the external light source circuit is controlled to emit light; a single encoder can support the encoding of 8 channels at most, and a plurality of encoders can be connected through a switch to expand the channel number of the channels.
The Ethernet input interface unit unpacks the input signal through the network port. And the decoding unit is used for specially analyzing the Ethernet network data by using a single module, and unpacking the network data by using a soft core in the module, so that the hardware circuit design of the system is simplified.
The coding mode configurable unit uses a special module to code data, and can select coding modes such as Manchester coding and polar code coding through a dial switch, so that the selectivity of various coding mode sets is realized. When the encoding mode configurable unit adopts a Manchester encoding mode, the frequency of a signal sequence is doubled, and an encoded signal is obtained through high-low level conversion. When the coding mode configurable unit adopts a polar code coding mode, the signal sequence is decomposed, multiplication calculation is carried out by multiplexing a Kronecker product matrix in a generated matrix, and then accumulation and sorting operation is carried out to obtain a coded signal, so that the complexity of hardware design is reduced. The decoding unit and the encoding mode configurable unit can be implemented by using a logic control circuit or a sequential control circuit, such as an FPGA, a DSP, and the like.
The TTL high-speed signal drives the output unit to output the coded high-speed signal to enter the high-speed photoelectric conversion isolation unit. The core of the high-speed photoelectric conversion isolation unit is that photoelectric isolation is completed by using a photoelectric coupling device 6N137, low-voltage VCC _ L is used for supplying power, a collector output mode is adopted, and a plurality of groups of output TTL driving signals are input into the high-power constant current driving unit after high-speed photoelectric conversion, so that complete electric isolation is realized.
The high-power constant current driving unit adopts a TLC5927 high-power constant current driving chip, 16 output ends of the chip are connected, constant large current output can be obtained, and the external light source circuit can stably work for a long time. The plurality of high-power constant current driving chips are connected in parallel, and can output larger constant large current to meet the power requirement of an external light source circuit; the plurality of groups of high-power constant current driving units are connected in parallel, and can output a plurality of groups of constant large currents to the external light source circuit so as to meet the scale requirement of the external light source circuit.
The beneficial effect of this application is:
the high-speed expandable encoder of the high-power free space optical communication system has the characteristics of high-speed transmission, stable work, large driving power, free expansion and the like. The high-speed transmission performance of the encoder is ensured by using a high-speed coding scheme; the constant current driving chip is used for carrying out constant current driving on the LED, so that the temperature influence of the LED under the long-time working condition is reduced, and the light source stably works for a long time; different external light source circuits can be matched through the parallel combination of a plurality of groups of high-power constant current driving units; can expand the equipment through multi-disc encoder connection switch to expand the channel quantity of channel, drive the external light source circuit of different scales.
Drawings
Fig. 1 is a system structure block diagram of the high-speed expandable encoder of the high-power free space optical communication system;
fig. 2 is a schematic diagram of an ethernet input interface unit of the high-speed expandable encoder of the high-power free space optical communication system;
FIG. 3 is a schematic diagram of TCP/IP decoding of the high-speed expandable encoder of the high-power free space optical communication system;
FIG. 4 is a Manchester encoding schematic diagram of the high-speed expandable encoder of the high-power free space optical communication system;
fig. 5 is a polarization encoding flow chart of the high-speed expandable encoder of the high-power free space optical communication system;
FIG. 6 is a schematic diagram of a polar code encoding mode of the high-speed expandable encoder of the high-power free space optical communication system;
fig. 7 is a schematic block diagram of a high-power constant current driving unit of the high-power free space optical communication system high-speed expandable encoder;
fig. 8 is a schematic diagram of a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit of the high-speed expandable encoder of the high-power free space optical communication system;
fig. 9 is a schematic diagram of an encoder expansion scheme of the high-speed expandable encoder of the high-power free space optical communication system.
Detailed Description
The present application will be described in further detail below with reference to the accompanying drawings by way of specific embodiments.
Fig. 1 is a block diagram of a high-speed scalable encoder of a high-power free-space optical communication system. The high-speed expandable encoder comprises a low-voltage power supply unit 1, an Ethernet input interface unit 2, a decoding unit 3, an encoding mode configurable unit 4, a dial switch 5, a TTL high-speed signal driving output unit 6, a high-speed photoelectric conversion isolation unit 7, a high-power constant current driving unit 8, an external light source circuit 9 and a high-voltage power supply unit 10.
The low-voltage power supply unit 1 provides a low-voltage power supply for the Ethernet input interface unit 2, the decoding unit 3, the coding mode configurable unit 4 and the TTL high-speed signal driving output unit 6; the high-voltage power supply unit 10 provides a high-voltage power supply for the high-power constant-current driving unit 8.
Firstly, an Ethernet input interface unit 2 reads a TCP input data stream of a network interface, and enters a decoding unit 3 to unpack the TCP/IP data stream; then, the received network data stream enters an encoding mode configurable unit 4 for encoding, and an encoding mode such as polarization code or Manchester encoding can be selected through a dial switch 5; then, the TTL high-speed signal driving output unit 6 outputs a high-speed TTL driving signal according to the coding sequence; finally, the high-speed photoelectric conversion isolation unit 7 enters a high-power constant current driving unit 8; the high-power constant current driving unit 8 outputs a plurality of groups of constant large currents according to the data signals output by the isolation unit, so that the external light source circuit 9 is controlled to emit light.
In an embodiment, as shown in fig. 2, the schematic diagram of the ethernet input interface unit is that an RJ45 ethernet port socket 200 is connected to an isolation transformer 210, so as to implement ethernet data transmission under an electrical isolation condition, ensure high speed of input data stream reading, and eliminate common mode interference.
Data signals are input into RJ45 ethernet port jack 200 through a network cable connection. Here, the RJ45 ethernet port socket has 8 ports, wherein data signals enter corresponding input terminals of the port isolation transformer 210 through the TX +, TX-, RX +, and RX-four ports, and the rest of the four ports NC1, NC2, NC3, and NC4 are temporarily not used, and are connected to the communications ground CGND201 through resistors R10, R11, R12, and R13, and a connection capacitor C6, respectively. Appropriate resistors R6, R7, R8, R9, R10, R11, R12 and R13 are selected to form the Bob Smith circuit 202, so that impedance matching is realized, and a circuit protection effect is achieved.
The center tap CT3 and CT4 ports in the grid port isolation transformer 210 are connected to the capacitor C6 and the communication ground CGND201 through resistors R6 and R7 respectively; the center tap CT2 port is connected to signal ground GND211 through capacitor C4; the center tap CT1 is coupled to signal ground GND211 through capacitor C1 and to low voltage supply VCC 216 through resistor R1 to generate a bias voltage. The communication ground CGND201 is connected with the signal ground GND211 through a capacitor C5 to play a role of blocking direct current and avoid generating voltage deviation to cause direct current coupling.
The network port isolation transformer 210 outputs the input data signals after isolation conversion, and four paths of TXP212, TXN213, RXP214 and RXN215 are output from four terminals of TD +, TD-, RD + RD and RD-. The TD + and TD-ports of the network port isolation transformer 210 are connected to a low-voltage power supply VCC 216 through resistors R2 and R3; RD + RD-are respectively connected with capacitors C2 and C3, and are respectively connected with a port CT2 through resistors R4 and R5, so that common mode noise is filtered out.
The input data signals after the isolation conversion enter a decoding unit 3 for TCP/IP data stream unpacking. And the decoding unit 3 is used for specially analyzing the Ethernet network data by using an independent module, and unpacks the network data through an internal soft core, so that the hardware circuit design of the system is simplified. Referring to fig. 3, the decoding process includes three steps, namely link layer decoding 31, IP decoding 32, and TCP decoding 33, to finally obtain decoded data. In the step of decoding 31 of the link layer, the MAC layer firstly judges a data signal, confirms that the data signal is in communication, then carries out head and tail removing decoding work to obtain Framedata data, and sends the Framedata data to the IP layer. Framedata sent to the IP layer consists of an IPheader and IPdata, and header removing work is carried out in the step of IP decoding 32 to obtain IP data. The IPdata consists of TCPheeader and TCPdata, and is transmitted into a TCP module to carry out the first-removing work in the step of TCP decoding 33, so that Data, namely decoded Data, is obtained.
In the encoder, the encoding mode configurable unit 4 uses a special module to encode data, and can select encoding modes such as manchester encoding and polar code encoding through the dial switch 5, so as to realize the selectivity of a plurality of encoding mode sets. The dial switch 5 provides level signals of different port inputs for the encoding mode configurable unit 4 to control the encoding mode configurable unit 4 to enable different encoding modes. The encoding mode configurable unit 4 includes multiple encoding modes to implement encoding under different application situations. In this example, a single encoder can support up to 8 channels of encoding, considering the amount of computation and complexity. The decoding unit 3 and the encoding mode configurable unit 4 in the present encoder may be implemented by using a logic control circuit or a sequential control circuit, such as an FPGA, a DSP, or the like.
In one embodiment, the encoding mode configurable unit 4 employs manchester encoding, the principle of which is shown in fig. 4. In this example, the encoded header 411 is set to a low level signal, and when there is information to be transmitted, a low level signal is first sent to acknowledge the transmission. In the manchester encoding process 412, a high level "1" transmitted in the data signal is converted into a "1-0" signal having a duty cycle of 50%, and a low level "0" transmitted in the data signal is converted into a "0-1" signal having a duty cycle of 50%. Taking "11010010" as an example of the input sequence, the signal after Manchester encoding is "1010011001011001". At the same time, a code tail 413 is provided which nulls for high levels when no signal is being sent.
The coding mode configurable unit 4 sets two input clock signals, respectively a baseband clock and a band clock. The input data sequence is a baseband clock domain signal, and the output data sequence after encoding is a frequency band clock domain signal, wherein the baseband clock plays a role of fundamental frequency synchronization. It should be noted that the frequency of the band clock should be twice the baseband clock due to the level jump during manchester encoding. A counter is started at the beginning of encoding to generate a low level signal of an encoding head, a data bit and a parity bit. The manchester encoding module can be realized by adopting a state machine, starts to execute encoding work when a valid enabling signal is detected, enters a starting state, latches data to be encoded and generates a synchronous head signal 411; then, whether the value of the input data is a high level or a low level is judged, the input data respectively enters two states, the two states are assigned as '1-0' and '0-1' and are output, and the Manchester encoding process 412 is completed; and when the counter is in a full state, performing serial-parallel conversion on the data, verifying to indicate that the coding is finished, and transmitting the coded complete data and a zero setting busy signal.
In an embodiment, the encoding mode configurable unit 4 employs a polar code encoding method. The polar encoding flowchart includes four steps of reliability estimation 421, bit mixing 422, constructing generator matrix 423, and matrix multiplication 424, as shown in fig. 5. The input data is first subjected to reliability estimation 421, and a polarization code sequence structure is performed to calculate a subchannel with a high channel capacity for data transmission and a subchannel with a low signal capacity for transmission of frozen bits, so as to obtain a polarization sequence { i } [ (i) 1 ，i 2 ，...，i p ，j 1 ，j 2 ，...，j q And f, wherein the front p channels are information bit positions, and the rear q channels are used as frozen bit positions for fixed transmission. Then will beThe constructed polarization code is bit-mixed 422, the information bits and the frozen bits are code-mixed, and the information bits are set to { i } 1 ，i 2 ，...，i p The data of which is set to 1 and the frozen bit is j 1 ，j 2 ，...，j q The data of } is set to 0, resulting in a sequence
Then, a generator matrix 423 is constructed, and a parity separation ordering matrix B is first obtained N The separation of odd and even elements is done on the input sequence, which results in the sequence { u } 1 ，u 3 ，u 5 ，...，u N-1 ，u 2 ，u 4 ，u 6 ，...，u N }; then the matrix after n times of Kronecker product operation is solved
Wherein
And is
Obtaining a generator matrix
Finally, matrix multiplication 424 is performed to mix the data into bits
And generating matrix G N And multiplying to obtain the encoded polarization code, and finishing the polarization code encoding operation.
In a specific embodiment, as shown in fig. 6, when the coding mode configurable unit 4 adopts a polar code coding method, the signal sequence is decomposed, the Kronecker product matrix in the generated matrix is multiplexed to perform multiplication, and then the encoded signal is obtained by performing accumulation and sorting operation, so that the complexity of hardware design can be effectively reduced.
The DATA bit length of the input IN each clock signal is set to 64, i.e., the input signal is DATA _ IN [ 63: 0]. Considering the amount of matrix multiplication, the input signal sequence is first subjected to bit decomposition 431, and the input 64-bit signal is decomposed into 8 parts on average, each of which has a bit length of 8. The calculation module 432 uses gaussian approximation to complete the reliability estimation 421, and when the transmission error probability of each bit is judged to be less than a certain threshold, the bit is selected as an information bit with high channel capacity for data transmission, otherwise, the bit is selected as a frozen bit with low channel capacity for fixed transmission, so as to construct a polarization code sequence. The length of the polarization code sequence constructed here is set to 512, where the first 64 bits are information bits and the last 448 bits are frozen bits. The bit mixing 433 performs bit mixing on the input signal sequence according to the polarization code sequence given by the calculating module 432 to obtain a signal sequence after the input signal and the frozen bits are mixed, the total sequence length is 512, the signal sequence is composed of eight parts of P1, P2, … and P8 on average, and the sequence length of each part is 64.
In order to reduce the system computation amount and improve the utilization rate of hardware resources in the coding generation matrix, a 64 × 64Kronecker product 434 matrix is generated and multiplexed, namely, F1 to F8, and is multiplied by P1 to P8 respectively to obtain 8 groups of data sequences with the length of 64. The 8 groups of data sequences then enter buffer accumulation 435 for data buffering, and the buffered 8 groups of 64-bit signal sequences are accumulated to obtain 8 groups of 64-bit data after encoding. The 8 groups of data sequences are then arranged 436 in reverse order to obtain 8 groups of 64-bit signal sequences in sequence. Finally, the DATA sequence enters the output buffer module 437, and the 8 groups of DATA sequences are buffered and combined to output a signal sequence with a length of 512, that is, DATA _ OUT [ 511: 0].
The control module 430 may be implemented by a state machine. When the input high-level enable signal EN is recognized, the control module starts to perform a polar code encoding operation. The control module 430 outputs five enable signals EN1, EN2, EN3, EN4, EN 5. The enable signal EN1 controls the calculation module 432 to perform the reliability estimation 421 step, enter the first calculation state and perform the bit mixing 433; enabling a signal EN2 to control the operation of generating a Kronecker product matrix, generating 64 x 64Kronecker product 434 matrixes F1-F8, executing matrix multiplication operation, and entering a matrix calling state; enabling signals EN3 control a buffer accumulation 435 unit to buffer the data sequence, perform bit accumulation of each bit and enter an accumulation state; the enable signal EN4 controls the unit 436 to reverse order, and 8 groups of data sequences are reverse order arranged to enter a reverse order state; the enable signal EN5 controls the output buffer module to buffer 8 groups of data sequences, combine them into 512-bit data sequence and output them, and enter the output coding state. When the data is being coded, the control module continuously outputs a high-level busy signal, after the coding is finished, the initial state is recovered, and the control module outputs a zero setting busy signal.
Fig. 7 is a schematic block diagram of a high-power constant current driving unit. In the high-speed photoelectric conversion isolation unit 7, the core is a photoelectric coupling unit 71, and an initialization configuration signal 72 and a control signal 73 are output; in the high-power constant current driving unit 8, the core is a plurality of constant current sources, and the high-power constant current driving unit is composed of a high-power constant current driving chip. The function of the initialization configuration signal 72 is to output CLK, SDI, LE signals to enable and initialize the constant current sources 80, 81, … … 87; the control signal 73 is used for sending signals of OE0, OE1, and … … OE7 with matched numbers to the constant current sources 80, 81, … … and the like to control the constant current sources to output constant current to the external light source circuit 9.
It should be noted that, in this embodiment, a single high-power constant current driving unit 8 is taken as an example to implement light source driving. When the scale requirement of the external light source circuit is larger, a plurality of groups of high-power constant current driving units 8 can be connected in parallel to output more groups of constant large currents to the external light source circuit so as to adapt to the scale requirement of the external light source circuit.
The external light source circuit 9 may be composed of a plurality of LED lamp sets, as shown in fig. 7, to form an LED array. Each lamp group comprises a plurality of LEDs connected in series, and all the LED lamp groups are connected in a common anode mode, namely are connected in parallel. The external light source circuit 9 controls the input current signals of 0 and 1 to turn off and turn on the LED lamp panel, so that the text information or voice information of a user can be directionally transmitted out in the form of optical signals through the optical system of the communication lamp.
In one embodiment, please refer to fig. 8, a schematic diagram of a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit. The TTL high-speed signal driving output unit 6 outputs a high-speed TTL signal, and here, taking one OE signal as an example, the output unit 601 outputs four signals including SDI, CLK, LE, and OE1, where SDI, CLK, and LE are three initialization configuration signals, and OE1 is one control signal.
The core of the high-speed photoelectric conversion isolation unit 7 is that photoelectric isolation is completed by using a photoelectric coupling device 6N137, low-voltage VCC _ L is used for supplying power, a collector output mode is adopted, and a plurality of groups of output TTL driving signals are input into the high-power constant-current driving unit 8 after high-speed photoelectric conversion, so that complete electrical isolation is realized.
In this example, the output unit 601 outputs four signals, which are connected to four input terminals of the photocoupler 711 through current limiting resistors R10, R11, R12, and R13, respectively, and when a high level signal is input, the photodiode inside the chip 6N137 emits light. The photocoupler 711 inputs the signal after the isolation conversion into the base stage of the output stage triode, outputs the signal through the collector, and pulls the signal up to VCC _ H through the resistors R1, R2, R3 and R4, that is, the high-voltage power supply unit 10, so as to ensure that the chip 6N137 outputs a high-level signal when a high-level signal is input. The four outputs of the photocoupler 711 enter the base stage of the next stage triode 732 and are output by the collector, the four collector outputs are pulled up to VCC _ H through resistors R5, R6, R7, and R8, and when a high level signal is input, the triode 732 outputs a high level signal.
The high-power constant current driving unit 8 adopts a TLC5927 high-power constant current driving chip 801, and 16 output ends of the chip are connected, so that constant large current output can be obtained, and the external light source circuit 9 can stably work for a long time. The constant current source TLC5927 chip 801 is supplied with power by VCC _ H high voltage, and normal work is guaranteed. The chip firstly receives three signals of CLK, LE and SDI output by Q1, Q2 and Q3 in the triode 732 to complete internal initialization configuration, and then controls the chip according to an OE1 signal output by Q4 in the triode 732. The constant current source TLC5927 chip 801 is provided with OUT0-OUT15 pins, each pin can input sink current of 5 mA-120 mA, 16 pins are connected, a large constant driving current LED-0802 can be obtained, the single-channel driving current can reach 80 mA-1.92A at most, and the single-channel driving current is output to an external light source circuit 9.
The initialization configuration signal is composed of three signals, CLK, SDI, and LE. The CLK signal is first configured with a square wave signal having a frequency of 10kHz and a duty cycle of 50%, i.e. it is inverted every 50 us. And simultaneously controlling the SDI signal to sample all rising edges of the CLK signal, wherein in order to enable the output driving current to be large enough, all 16 paths of outputs are selected to be connected to supply power to one path of LED, so that the SDI signal is a signal which is constantly at a high level. After 16 cycles of the CLK signal, the LE port sends a high pulse with a pulse width of 2ms, which informs the system driver circuit that the initialization configuration has been completed. After the initialization configuration is completed, signals of CLK, SDI and LE do not need to be provided to the constant current source TLC5927 chip 801 any more, and only an OE1 signal needs to be sent to the constant current source TLC5927 chip 801 to control the constant current to light the corresponding LED lamp group. The initial value of an OE1 signal is high level, and when the OE1 signal is low level, the constant current source TLC5927 chip outputs constant current; when the OE1 signal is high, the constant current source TLC5927 chip 801 does not output current.
It should be noted that, in this embodiment, a single high-power constant-current driving unit 8 exemplifies a TLC5927 high-power constant-current driving chip 801 to implement constant-current driving. When the power requirement is larger, multiple TLC5927 high-power constant-current driving chips 801 can be connected in parallel in a single high-power constant-current driving unit 8, three signals of CLK, LE and SDI are shared to complete internal initialization configuration, and a signal of OE1 is shared to control the multiple chips, so that a larger constant driving current after multi-channel combination can be obtained, and larger power can be realized. If the power of a single high-power constant current driving unit 8 is adjustable and adaptable, different OE signals can be selected to be used for controlling a plurality of chips respectively.
In an embodiment, please refer to fig. 9, which is a schematic diagram of an expansion scheme of the encoder. The expansion scheme is composed of an upper computer 90, a switch 91, an encoder 92 and an external light source 93. The upper computer 90 is connected with the switch 91 to perform control and data transmission, the switch 91 is connected with the multiple encoders 92 to perform encoding and data transmission, and each encoder 92 is connected with the external light source 93 to control the light emission. The number of encoders 92 may be determined according to the restriction conditions of the switch 91 and the scale of the external light source 93. Each piece of encoder 92 can support encoding of 8 channels at most, and a plurality of encoders are connected in parallel through a switch to expand the channel number of the channels.
In summary, the present application implements a high-speed expandable encoder for a high-power free-space optical communication system.
The foregoing is a more detailed description of the present application in connection with specific embodiments thereof, and it is not intended that the present application be limited to the specific embodiments thereof. All the substitutions made on the basis of the technical scheme belong to the protection scope of the patent claims of the invention.
Claims (8)
1. A high-speed expandable encoder of a high-power free space optical communication system is characterized in that a data stream is accessed from a gigabit network interface, and a constant large-current control signal is output for an external light source circuit after high-speed data encoding; the high-speed expandable encoder comprises an Ethernet input interface unit, a decoding unit, an encoding mode configurable unit, a TTL high-speed signal driving output unit, a high-speed photoelectric conversion isolation unit and a high-power constant current driving unit;
the work of the high-speed expandable encoder of the high-power free space optical communication system comprises the following processes:
firstly, reading a TCP input data stream of an Ethernet network interface, and entering a decoding unit to unpack a TCP/IP data stream; selecting coding modes such as polarization code coding or Manchester coding and the like through a dial switch, and entering a next coding unit for coding according to the received network data stream; then outputting a high-speed TTL driving signal according to the coding sequence; finally, the high-power constant current unit is driven by the isolation unit; the high-power constant current driving unit outputs a plurality of groups of constant heavy currents according to the data signals output by the isolation unit, so that the external light source circuit is controlled to emit light; a single encoder can support the encoding of 8 channels at most, and a plurality of encoders can be connected through a switch to expand the channel number of the channels.
2. The high-speed scalable encoder of the high-power free-space optical communication system according to claim 1, wherein the decoding unit uses a single module to perform ethernet network data analysis exclusively, and unpacks the network data through a soft core inside the module, thereby simplifying the hardware circuit design of the system.
3. The high-speed scalable encoder of the high-power free-space optical communication system according to claim 1, wherein the encoding mode configurable unit uses a special module to encode data, and the selection of the encoding mode, such as manchester encoding and polar code encoding, can be performed through a dial switch, so as to achieve the selectivity of a plurality of encoding mode sets.
4. The high-speed expandable encoder of the high-power free-space optical communication system as claimed in claim 1, wherein when the encoding mode configurable unit adopts a polar code encoding mode, the signal sequence is decomposed, the Kronecker product matrix in the generated matrix is multiplexed to perform multiplication calculation, and then the encoded signal is obtained by performing accumulation sorting operation, thereby reducing the complexity of hardware design.
5. The high-power free-space optical communication system high-speed scalable encoder according to claim 1, wherein the decoding unit and the encoding mode configurable unit can be implemented by using a logic control circuit or a sequential control circuit, such as FPGA, DSP, or the like.
6. The high-speed expandable encoder of the high-power free-space optical communication system as claimed in claim 1, wherein the core of the high-speed photoelectric conversion isolation unit is to use a photoelectric coupler 6N137 to complete photoelectric isolation, and it uses a low-voltage VCC _ L to supply power, and adopts a collector output mode to input multiple output TTL driving signals into the high-power constant current driving unit after high-speed photoelectric conversion, so as to achieve complete electric isolation.
7. The high-speed expandable encoder of the high-power free-space optical communication system as claimed in claim 1, wherein the high-power constant-current driving unit adopts a TLC5927 high-power constant-current driving chip, and 16 output terminals of the chip are connected to obtain constant large-current output, thereby ensuring that an external light source circuit can stably work for a long time.
8. The high-speed expandable encoder of the high-power free-space optical communication system as claimed in claim 7, wherein a plurality of high-power constant current driving chips are connected in parallel and can output larger constant large current to meet the power requirement of an external light source circuit; the multiple groups of high-power constant current driving units are connected in parallel, can output multiple groups of constant large currents and output the multiple groups of constant large currents to the external light source circuit so as to meet the scale requirement of the external light source circuit.
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Cited By (2)
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| CN115955374A (en) * | 2022-12-15 | 2023-04-11 | 上海创景信息科技有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
| CN115955374B (en) * | 2022-12-15 | 2024-06-04 | 上海创景信息科技股份有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115955374A (en) * | 2022-12-15 | 2023-04-11 | 上海创景信息科技有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
| CN115955374B (en) * | 2022-12-15 | 2024-06-04 | 上海创景信息科技股份有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
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