CN115033506A

CN115033506A - Interrupt processing method and device

Info

Publication number: CN115033506A
Application number: CN202210581298.4A
Authority: CN
Inventors: 郭建华; 张飞
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2022-05-26
Filing date: 2022-05-26
Publication date: 2022-09-09

Abstract

The application provides an interrupt processing method and device. The method is applied to a control core in a multi-core CPU in forwarding equipment, and comprises the following steps: when a DMA interrupt request sent by any forwarding chip in the forwarding equipment is received, sending a DMA interrupt response used for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel; inquiring an interruption flag bit with a value as a set value stored in a designated storage space in the multi-core CPU, awakening a service core in the multi-core CPU, which needs to forward a service message in a DMA forwarding queue corresponding to the inquired interruption flag bit, to forward the service message in the corresponding DMA forwarding queue, and sending a forwarding completion message to the forwarding chip through a PCIE channel after the service core forwards the service message in the corresponding DMA forwarding queue. The method and the device can improve the forwarding efficiency of the service message associated with the DMA interrupt request.

Description

Interrupt processing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to an interrupt processing method and apparatus.

Background

In a communication network, any forwarding device (e.g., routing device, etc.) in the communication network may include multiple forwarding chips and a Central Processing Unit (CPU). A Peripheral Component Interconnect Express (PCIE) channel is established between each forwarding chip and the multi-core CPU, and the multi-core CPU may include one control core and a plurality of service cores.

For any forwarding chip (as shown in fig. 1) in the forwarding device, when a service packet is received through a network port (e.g., network port 1) on the forwarding device to which the forwarding chip belongs, the service packet is written into a DMA forwarding queue, determined by the forwarding chip, in the multi-core CPU and storing the service packet through a Direct Memory Access (DMA) mode through a PCIE channel, and a DMA interrupt corresponding to the DMA forwarding queue is also generated at the same time, and a value of an interrupt flag bit corresponding to the DMA forwarding queue in an interrupt flag register on the forwarding chip is set to a set value (e.g., 1) from an initial value (e.g., 0); and then, the forwarding chip reports the DMA interrupt to a control core in the multi-core CPU through the PCIE channel.

After receiving the DMA interrupt, the control core queries the interrupt flag register on the forwarding chip through the PCIE channel, wakes up the service core that needs to forward the service packet in the DMA forwarding queue corresponding to the interrupt flag bit whose queried value is the set value to process the service packet in the corresponding DMA forwarding queue, and after the subsequent corresponding service core has forwarded the corresponding service packet, sets the values of the interrupt flag bits corresponding to all the DMA forwarding queues on the interrupt flag register as initial values through the PCIE channel.

In the process of processing the DMA interrupt request, the control core needs to query the interrupt flag register through the PCIE channel to obtain the interrupt flag bit with the set value, which may be affected by network delay and other factors, so that the control core cannot query the interrupt flag bit with the set value in time, and further affects the forwarding efficiency of the related service core for forwarding the related service packet. Moreover, under the condition that the forwarding chip frequently reports the DMA interrupt request, the speed of the control core for processing the DMA interrupt request is affected, the forwarding efficiency of the related service core for forwarding the related service packet is also affected, and the problem that part of the DMA interrupt request is reported more or is not reported easily occurs.

Disclosure of Invention

In order to overcome the problems in the related art, the application provides an interrupt processing method and device.

According to a first aspect of embodiments of the present application, there is provided an interrupt processing method, which is applied to any forwarding chip in a forwarding device, and includes:

after a plurality of determined service messages which meet preset conditions and are received by the forwarding equipment are written into a DMA (direct memory access) forwarding queue for storing the service messages in a multi-core CPU (central processing unit) in the forwarding equipment in a DMA mode through a PCIE (peripheral component interface express) channel for the first time, a DMA interrupt request corresponding to the DMA forwarding queue is generated;

setting the value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

reporting the DMA interrupt request to a control core in the multi-core CPU through the PCIE channel, refreshing interrupt flag bits corresponding to all local DMA forwarding queues and corresponding values thereof to a designated storage space in the multi-core CPU, and restoring the values of all the interrupt flag bits to the initial values, so that when the control core receives the DMA interrupt request, sending a DMA interrupt response for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel, inquiring the interrupt flag bits with the values stored in the designated storage space as set values, and waking up a service core in the multi-core CPU, which needs to forward service messages in the DMA forwarding queues corresponding to the inquired interrupt flag bits, to forward the service messages in the corresponding DMA forwarding queues, so that after the service core finishes forwarding the service messages in the corresponding DMA forwarding queues, sending a forwarding completion message to the forwarding chip through the PCIE channel;

when receiving the DMA interruption response sent by the control core and the forwarding completion message sent by the service core, judging whether a generated and unreported DMA interruption request exists locally;

if so, taking the generated and unreported DMA interrupt request with the generation time closest to the generation time of the DMA interrupt request as the DMA interrupt request, and executing the step of setting the value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

and if the judgment result is negative, executing a waiting operation, taking a new DMA interrupt request as the DMA interrupt request when waiting for the generation of the new DMA interrupt request, and executing a step of setting the value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value.

According to a second aspect of the embodiments of the present application, there is provided an interrupt processing method, which is applied to a control core in a multi-core CPU in a forwarding device, the method including:

when a DMA interrupt request sent by any forwarding chip in the forwarding device is received, sending a DMA interrupt response used for representing that the control core has received the DMA interrupt request to the forwarding chip through a PCIE channel, wherein the DMA interrupt request is generated after the forwarding chip writes a plurality of determined service messages which are received by the forwarding chip and meet preset conditions into a DMA forwarding queue used for storing the service messages in the multi-core CPU through the PCIE channel in a DMA mode at any time;

inquiring an interrupt flag bit with a value as a set value stored in a designated storage space in the multi-core CPU, awakening a service core, which needs to forward a service message in a DMA forwarding queue corresponding to the inquired interrupt flag bit, in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, and sending a forwarding completion message to the forwarding chip through the PCIE channel after the service core finishes forwarding the service message in the corresponding DMA forwarding queue; the specified storage space stores the interrupt flag bits corresponding to all DMA forwarding queues on the forwarding chip refreshed by the forwarding chip and the corresponding values thereof, and in the interrupt flag bits corresponding to all DMA forwarding queues, the value of the interrupt flag bit corresponding to the DMA forwarding queue is set as a set value by the forwarding chip after the DMA interrupt request is reported by the forwarding chip, and the values of the rest interrupt flag bits are initial values.

According to a third aspect of the embodiments of the present application, there is provided an interrupt processing apparatus, which is applied to any forwarding chip in a forwarding device, and includes:

the generating module is used for generating a DMA interrupt request corresponding to a DMA forwarding queue after writing a plurality of determined self-received service messages meeting preset conditions into the DMA forwarding queue for storing the service messages in a multi-core CPU in the forwarding equipment through a PCIE channel in a DMA mode for the first time;

the setting module is used for setting the value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

a processing module, configured to report the DMA interrupt request to a control core in the multicore CPU through the PCIE channel, refresh interrupt flag bits corresponding to all local DMA forwarding queues and values corresponding to the interrupt flag bits into an assigned storage space in the multicore CPU, and restore the values of all interrupt flag bits to the initial values, so that when the control core receives the DMA interrupt request, send a DMA interrupt response used for representing that the DMA interrupt request has been received by the control core to the forwarding chip through the PCIE channel, query the interrupt flag bits whose values are set values stored in the assigned storage space, and wake up a service core in the multicore CPU, which needs to forward a service packet in a DMA forwarding queue corresponding to the queried interrupt flag bits to forward a service packet in the corresponding DMA forwarding queue, so that after the service core finishes forwarding the service packet in the corresponding DMA forwarding queue, sending a forwarding completion message to the forwarding chip through the PCIE channel;

a judging module, configured to, when receiving the DMA interrupt response sent by the control core and the forwarding completion message sent by the service core, judge whether a generated and unreported DMA interrupt request exists locally, and when a judgment result is yes, take the generated and unreported DMA interrupt request whose generation time is closest to the generation time of the DMA interrupt request as the DMA interrupt request, and trigger the setting module to perform a step of setting a value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

and the waiting module is used for executing a waiting operation when the judgment result of the judging module is negative, and taking a new DMA interrupt request as the DMA interrupt request when waiting for the generation of the new DMA interrupt request, and triggering the setting module to execute the step of setting the value of the interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value.

According to a fourth aspect of the embodiments of the present application, there is provided an interrupt processing apparatus, which is applied to a control core in a multi-core CPU in a forwarding device, the apparatus including:

the receiving and sending module is configured to send, to a forwarding chip in the forwarding device through a PCIE channel, a DMA interrupt response used to indicate that the control core has received the DMA interrupt request when receiving a DMA interrupt request sent by any forwarding chip in the forwarding device, where the DMA interrupt request is generated after the forwarding chip writes, in a DMA manner, multiple determined service messages that are received by the forwarding chip and meet a preset condition into a DMA forwarding queue used for storing the service messages in the multi-core CPU through the PCIE channel at any time;

the inquiry and wake-up module is used for inquiring an interrupt flag bit which is stored in a designated storage space in the multi-core CPU and takes a value as a set value, and waking up a service core which needs to forward a service message in a DMA forwarding queue corresponding to the inquired interrupt flag bit in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, so that the service core sends a forwarding completion message to the forwarding chip through the PCIE channel after forwarding the service message in the corresponding DMA forwarding queue; the specified storage space stores the interrupt flag bits corresponding to all DMA forwarding queues on the forwarding chip refreshed by the forwarding chip and the corresponding values thereof, and in the interrupt flag bits corresponding to all DMA forwarding queues, the value of the interrupt flag bit corresponding to the DMA forwarding queue is set as a set value by the forwarding chip after the DMA interrupt request is reported by the forwarding chip, and the values of the rest interrupt flag bits are initial values.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

in the embodiment of the present application, after writing the determined service packet, which is received by any forwarding chip in the forwarding device and satisfies the preset condition, into the DMA forwarding queue, which is used for storing the service packet, in the multi-core CPU in the forwarding device through the PCIE channel in a DMA manner, each time, a DMA interrupt request corresponding to the DMA forwarding queue is generated, so that the number of reported DMA interrupt requests can be reduced, the speed of the control core in the multi-core CPU for processing the DMA interrupt request is increased, and the forwarding efficiency of the related service core in the multi-core CPU for forwarding the related service packet is increased.

And after the forwarding chip reports a DMA interrupt request to the control core through the PCIE channel, the interrupt flag bits and the values corresponding to the interrupt flag bits corresponding to all local DMA forwarding queues are refreshed into the designated storage space in the multicore CPU, and the values of all the interrupt flag bits are restored to the initial values. Therefore, when receiving the current DMA interrupt request, the control core actively sends a DMA interrupt response for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel, and then queries the interrupt flag bit, in which the value stored in the specified storage space is the set value, without querying the interrupt flag bit, in which the value is the set value, through the PCIE channel, as in the prior art, thereby further improving the speed of the control core in the multi-core CPU for processing the DMA interrupt request, and improving the forwarding efficiency of the related service core in the multi-core CPU for forwarding the related service packet.

The subsequent control core also wakes up a service core in the multi-core CPU, which needs to forward the service message in the DMA forwarding queue corresponding to the inquired interrupt flag bit, to forward the service message in the corresponding DMA forwarding queue, so that the service core sends a forwarding completion message to the forwarding chip through the PCIE channel after forwarding the service message in the corresponding DMA forwarding queue, so that the forwarding chip can continue to report the next generated interrupt request only under the condition that a DMA interrupt response aiming at the DMA interrupt request generated this time and a forwarding completion message aiming at the service message in the DMA forwarding queue corresponding to the DMA interrupt request generated this time, which are sent by the control core, are received, thereby avoiding the problem that the DMA interrupt request is reported more or is not reported.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Fig. 1 is an interaction diagram of a forwarding chip and a multi-core CPU in a conventional forwarding device for processing a DMA interrupt request;

fig. 2 is a flowchart illustrating an interrupt processing method according to an embodiment of the present disclosure;

fig. 3 is a second flowchart illustrating an interrupt processing method according to an embodiment of the present application;

fig. 4 is an interaction diagram of processing a DMA interrupt request between a forwarding chip in a forwarding device and a multi-core CPU according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" or "if" as used herein may be interpreted as "at … …" or "when … …" depending on the context.

Next, examples of the present application will be described in detail.

An embodiment of the present application provides an interrupt processing method, which is applied to any forwarding chip in a forwarding device, and as shown in fig. 2, the method may include the following steps:

s21, after writing the determined multiple self-received service messages meeting the preset conditions into a DMA forwarding queue for storing the multiple service messages in a multi-core CPU in the forwarding device through a PCIE channel in a DMA mode for the first time, generating a DMA interrupt request corresponding to the DMA forwarding queue.

And S22, setting the value of the interrupt flag bit corresponding to the local DMA transfer queue to a set value from an initial value.

S23, reporting the DMA interrupt request to the control core in the multi-core CPU through the PCIE channel, refreshing the interrupt flag bits corresponding to all local DMA forwarding queues and the corresponding values to the appointed storage space in the multi-core CPU, and all the interrupt flag bits are restored to the initial value, so that when the control core receives the DMA interrupt request, sending a DMA interrupt response for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel, inquiring an interrupt flag bit which is stored in a specified storage space and takes a value as a set value, and awakens the service core of the service message in the DMA forwarding queue corresponding to the interrupt flag bit required to be forwarded and inquired in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, after the service core finishes transmitting the service message in the corresponding DMA transmitting queue, the transmitting completion message is sent to the transmitting chip through the PCIE channel.

In this step, of the interrupt flag bits and their corresponding values corresponding to all DMA transfer queues stored in the designated storage space, only the value of the interrupt flag bit corresponding to the DMA transfer queue corresponding to the DMA interrupt request is a set value, and the values of the interrupt flag bits corresponding to the remaining DMA transfer queues are all initial values.

S24, when receiving the DMA interruption response sent by the control core and the forwarding completion message sent by the service core, judging whether a generated and unreported DMA interruption request exists locally; if so, taking the generated and unreported DMA interrupt request with the generation time closest to the generation time of the DMA interrupt request as the DMA interrupt request, and executing step S22; when the determination result is no, step S25 is executed.

S25, a wait operation is executed, and when it is waited for that a new DMA interrupt request is generated, the new DMA interrupt request is made a DMA interrupt request, and step S22 is executed.

Specifically, in step S11, the forwarding chip may determine the service packet that meets the preset condition and is received by itself in the following manner:

if the timer arranged on the self is monitored to be overtime but the total number of the received service messages in the overtime duration of the timer does not reach the set number, determining all the service messages received in the overtime duration as the self-received service messages meeting the preset conditions;

if the timer is monitored not to be overtime but a set number of service messages are received, determining the received set number of service messages as the service messages meeting the preset conditions.

That is, in the embodiment of the present application, a timer is set on the forwarding chip, and the timeout duration of the timer can be set according to the actual requirements of the network to which the forwarding device belongs. After the forwarding chip starts the timer, if the timer is monitored to be overtime first, and the total number of the service messages received within the overtime duration of the timer is not more than the set number, under the condition, all the service messages received within the overtime duration are considered to be the service messages which are determined by the forwarding chip and meet the preset condition, and the timer is restarted. Here, the set number may also be set according to actual requirements of the network to which the forwarding device belongs.

If it is monitored that the set number of service messages are received, but the timer is not overtime, in this case, the received set number of service messages are also considered to be the service messages which are determined by the forwarding chip and meet the preset conditions, and the timer is restarted.

By executing the determined flow, the reporting number of the DMA interrupt requests can be reduced, so that the speed of the control core in the multi-core CPU for processing the DMA interrupt requests is increased, and the forwarding efficiency of related service cores in the multi-core CPU for forwarding related service messages is increased.

In addition, it should be noted that, in step S21, the DMA forwarding queue for storing a plurality of service messages is determined by the forwarding chip through an existing determining method, and a detailed determining process is not described in detail.

For example, service messages with the same source IP address and destination IP address are in the same DMA forwarding queue; for another example, service packets from the same port are in the same DMA forwarding queue.

Specifically, in step S22, the forwarding chip may set the value of the interrupt flag bit corresponding to the DMA forwarding queue set on the interrupt flag in the forwarding device from the initial value to the set value.

Here, the initial value and the set value may be set by a network administrator. The initial value is used for representing that the service message in the DMA forwarding queue corresponding to the corresponding interrupt zone bit does not need to be forwarded; the set value is used for representing that the service message in the DMA forwarding queue corresponding to the corresponding interrupt zone bit needs to be forwarded. For example, the initial value may be 0, the set value may be 1, and the like.

It should be noted that, in step S23, after the interrupt flag bits and their corresponding values corresponding to all local DMA forwarding queues are refreshed into the designated storage space in the multi-core CPU, the forwarding chip needs to perform a step of restoring the values of all interrupt flag bits to the initial values, which is mainly to ensure that when the forwarding chip reports a DMA interrupt request next time, the value of the interrupt flag bit corresponding to the relevant DMA forwarding queue can be accurately set, so that the relevant service core can accurately process the service packet in the relevant DMA forwarding queue.

After the forwarding chip executes the step S23, for the control core, when receiving the DMA interrupt request, the forwarding chip sends a DMA interrupt response for indicating that the control core has received the DMA interrupt request through the PCIE channel, so that the forwarding chip can know the report condition of the DMA interrupt request in time.

And the control core also queries an interrupt flag bit which is stored in the designated storage space and takes the value as a set value, then wakes up a service core which needs to forward the service message in the DMA forwarding queue corresponding to the queried interrupt flag bit in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, so that after the service core finishes forwarding the service message in the corresponding DMA forwarding queue, the service core sends a forwarding completion message (used for representing that the message forwarding is completed) to the forwarding chip through the PCIE channel. Here, the wakeup process of the service core that the control core wakes up the service packet in the DMA forwarding queue corresponding to the interrupt flag bit that needs to be forwarded and inquired in the multi-core CPU to forward the service packet in the DMA forwarding queue corresponding to the interrupt flag bit is the prior art, and is not described in detail here.

Therefore, the control core does not need to interact with the forwarding chip through a PCIE channel to obtain a corresponding interrupt flag bit, the speed of the control core in the multi-core CPU for processing the DMA interrupt request is greatly increased, and the forwarding efficiency of the service core for forwarding the service messages in the corresponding DMA forwarding queue is greatly increased.

Here, for the service core, once the service core is awakened by the control core, all the service messages in the DMA forwarding queue indicated by the control core are forwarded, and then a corresponding forwarding completion message is sent to the forwarding chip through the PCIE channel, so that a situation that the subsequent control core awakens again to forward the service messages in the DMA forwarding queue but the DMA forwarding queue is empty may occur, and in this situation, the service core still sends the corresponding forwarding completion message to the forwarding chip through the PCIE channel.

In addition, the service core needs to send the relevant forwarding completion message to the forwarding chip through the PCIE channel, mainly to ensure that the forwarding chip does not report more or report less DMA interrupt requests. That is, for the forwarding chip, only in the case of receiving the related DMA interrupt response sent by the control core and the related forwarding completion message sent by the related service core, the forwarding chip will continue to report the next generated DMA interrupt request.

It should be further noted that, in the embodiment of the present application, in order to improve the reliability of the report of the DMA interrupt request, the forwarding chip may further perform the following operations:

after the DMA interrupt request is reported to the control core through the PCIE channel, if the DMA interrupt response sent by the control core through the PCIE channel is not received within the set duration, the DMA interrupt request is reported to the control core through the PCIE channel again.

Here, the set time period may also be set according to the actual requirements of the network to which the forwarding device belongs.

In this embodiment of the application, after the step S24 is completed, if the determination result is yes, it means that the forwarding chip generates a new DMA interrupt request (which may also be referred to as a generated and unreported DMA interrupt request) within a time period from when the forwarding completion message is received after the DMA interrupt request is reported, and the number of the new DMA interrupt requests generated within the time period may be one or multiple.

If the result of the determination is negative, it means that the forwarding chip does not generate a new DMA interrupt request within the time period from the reporting of the DMA interrupt request to the receiving of the forwarding completion message, and needs to perform a wait operation until it waits until it generates a new DMA interrupt request, and starts to perform step S22 with the new DMA interrupt request as the DMA interrupt request.

The above is the flow of the interrupt processing method described on any forwarding chip side standing in the forwarding device. The flow of the interrupt processing method described below on the control core side in the multicore CPU standing in the forwarding device. As shown in fig. 3, for another interrupt processing method provided in this embodiment of the present application, the method is applied to a control core in a multi-core CPU in a forwarding device, and the method may include the following steps:

s31, when receiving a DMA interrupt request sent by any forwarding chip in the forwarding device, sending a DMA interrupt response used for indicating that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel.

In this step, the DMA interrupt request is generated after the forwarding chip writes the determined service packet that satisfies the preset condition and is received by the forwarding chip into a DMA forwarding queue for storing the service packet in the multi-core CPU through the PCIE channel in a DMA manner each time.

It should be noted that the generation manner of the interrupt request in this step is the same as the generation manner in the flow of describing the interrupt processing method on any forwarding chip side standing in the forwarding device, and details are not described here.

S32, inquiring an interrupt flag bit with a value as a set value stored in a designated storage space in the multi-core CPU, waking up a service core in the multi-core CPU, which needs to forward the service message in the DMA forwarding queue corresponding to the inquired interrupt flag bit, to forward the service message in the corresponding DMA forwarding queue, and sending a forwarding completion message to the forwarding chip through the PCIE channel after the service core finishes forwarding the service message in the corresponding DMA forwarding queue.

In this step, the designated storage space stores the interrupt flag bits and their corresponding values corresponding to all DMA forwarding queues on the forwarding chip refreshed by the forwarding chip, and in the interrupt flag bits corresponding to all DMA forwarding queues, the value of the interrupt flag bit corresponding to the DMA forwarding queue is set as a set value by the forwarding chip after the forwarding chip reports the DMA interrupt request, and the values of the remaining interrupt flag bits are set as initial values.

The interrupt processing method described above will be described in detail with reference to specific embodiments.

It is assumed that a forwarding chip (as shown in fig. 4) in a forwarding device in a communication network starts a timer after the forwarding device is powered on (assuming that the timeout duration of the timer is 1s), and it is assumed that the forwarding chip receives 3 service packets through a gateway 1 when the timer is out of time, and assuming that the set number is 5, then, the forwarding chip will monitor that the timer has expired but the total number of the service messages received within the timeout duration of the timer (i.e., 3) is not greater than the set number (i.e., 5), and at this time, the forwarding chip writes the 3 service messages into a DMA forwarding queue (e.g., DMA forwarding queue 1) for storing the 3 service messages in a multi-core CPU in the forwarding device through the PCIE channel in a DMA manner, and after the writing is completed, a DMA interrupt request (denoted as DMA interrupt request 1) corresponding to the DMA forwarding queue 1 is generated.

After that, the forwarding chip sets the value of the interrupt flag bit (denoted as interrupt flag bit 1) corresponding to the DMA forwarding queue 1 set on its own interrupt flag register from the initial value (e.g., 0) to the set value (e.g., 1).

And then reporting the DMA interrupt request 1 to a control core (not shown in fig. 4) in the multi-core CPU through the PCIE channel, refreshing the interrupt flag bits and their corresponding values corresponding to all DMA forwarding queues on the interrupt flag register to a designated storage space in the multi-core CPU, and restoring the values of all the interrupt flag bits to initial values. Here, among the interrupt flag bits corresponding to all the DMA transfer queues stored in the designated storage space and the values corresponding thereto, only the interrupt flag bit corresponding to the DMA transfer queue 1 has a value of 1, and the interrupt flag bits corresponding to the remaining DMA transfer queues have values of 0.

When receiving the DMA interrupt request 1, the control core sends a DMA interrupt response (denoted as DMA interrupt response 1) for representing that the control core has received the DMA interrupt request 1 to the forwarding chip through the PCIE channel, queries an interrupt flag bit with a value of 1 stored in the specified storage space, and wakes up a service core (e.g., service core 1) in the multi-core CPU that needs to forward a service packet in the DMA forwarding queue (i.e., DMA forwarding queue 1) corresponding to the queried interrupt flag bit to forward the service packet in the DMA forwarding queue 1, so that after the service core 1 finishes forwarding the service packet in the DMA forwarding queue 1, the service core 1 sends a forwarding completion message (denoted as forwarding completion message 1) to the forwarding chip through the PCIE channel.

If the DMA interrupt response 1 sent by the control core and the forwarding completion message 1 sent by the service core 1 are subsequently received, at this time, the forwarding chip determines whether the generated and unreported DMA interrupt request exists locally.

If the forwarding chip generates 1 DMA interrupt request (denoted as DMA interrupt request 2, and if the corresponding DMA forwarding queue is the DMA forwarding queue 2) within a time period from the time when the forwarding chip reports the DMA interrupt request 1 to the time when the forwarding completion message 1 is received, the result of the determination is yes, and at this time, the forwarding chip sets the value of the interrupt flag bit (denoted as interrupt flag bit 2) corresponding to the DMA forwarding queue 2 in the interrupt flag register from 0 to 1.

And reporting the DMA interrupt request 2 to a control core in the multi-core CPU through a PCIE channel, refreshing interrupt flag bits corresponding to all DMA forwarding queues on an interrupt flag register and corresponding values thereof to a designated storage space in the multi-core CPU, and restoring the values of all the interrupt flag bits to initial values. Here, of the interrupt flag bits corresponding to all the DMA transfer queues stored in the designated storage space and the values corresponding thereto, only the interrupt flag bit corresponding to the DMA transfer queue 2 has a value of 1, and the interrupt flag bits corresponding to the remaining DMA transfer queues have values of 0.

When receiving the DMA interrupt request 2, the control core sends a DMA interrupt response (denoted as DMA interrupt response 2) for indicating that the control core has received the DMA interrupt request 2 to the forwarding chip through the PCIE channel, queries an interrupt flag bit with a value of 1 stored in the specified storage space, and wakes up a service core (for example, the service core 2) in the multi-core CPU, which needs to forward a service packet in the DMA forwarding queue (that is, the DMA forwarding queue 2) corresponding to the queried interrupt flag bit, to forward the service packet in the DMA forwarding queue 2, so that the service core 2 sends a forwarding completion message (denoted as forwarding completion message 2) to the forwarding chip through the PCIE channel after forwarding the service packet in the DMA forwarding queue 2.

If the DMA interrupt response 2 sent by the control core and the forwarding completion message 2 sent by the service core 2 are subsequently received, at this time, the forwarding chip still determines whether the generated and unreported DMA interrupt request exists locally.

If there is no generated and unreported DMA interrupt request locally, the determination result is no, at this time, the forwarding chip executes a wait operation, and when it waits until it generates a new DMA interrupt request, executes a process similar to the process after the DMA interrupt request 1 is generated, and the process is continuously cycled, and details are not described here.

According to the technical scheme, in the embodiment of the application, after each determined service message which is received by any forwarding chip in the forwarding device and meets the preset condition is written into the DMA forwarding queue for storing the service messages in the multi-core CPU in the forwarding device in a DMA mode through the PCIE channel, a DMA interrupt request corresponding to the DMA forwarding queue is generated, so that the number of reported DMA interrupt requests can be reduced, the speed of processing the DMA interrupt request by the control core in the multi-core CPU is increased, and the forwarding efficiency of forwarding the relevant service message by the relevant service core in the multi-core CPU is increased.

And after the forwarding chip reports a DMA interrupt request to the control core through the PCIE channel, the interrupt flag bits and the values corresponding to the interrupt flag bits corresponding to all local DMA forwarding queues are refreshed into the designated storage space in the multicore CPU, and the values of all the interrupt flag bits are restored to the initial values. Therefore, when receiving the current DMA interrupt request, the control core actively sends a DMA interrupt response for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel, and then queries the interrupt flag bit whose value is a set value and stored in the specified storage space, which does not need to query the interrupt flag bit whose value is a set value through the PCIE channel as in the prior art, so that the speed of the control core in the multi-core CPU processing the DMA interrupt request is further increased, and the forwarding efficiency of the related service core in the multi-core CPU forwarding the related service packet is increased.

Based on the same inventive concept, the present application further provides an interrupt processing apparatus, which is applied to any forwarding chip in a forwarding device, and a schematic structural diagram of the apparatus is shown in fig. 5, and specifically includes:

the generating module 51 is configured to generate a DMA interrupt request corresponding to a DMA forwarding queue after writing, for the first time, a plurality of determined service messages that are received by the generating module and meet a preset condition into the DMA forwarding queue used for storing the service messages in a multi-core CPU in the forwarding device through a PCIE channel in a DMA manner;

a setting module 52, configured to set a value of an interrupt flag corresponding to the local DMA forwarding queue from an initial value to a set value;

a processing module 53, configured to report the DMA interrupt request to a control core in the multicore CPU through the PCIE channel, refresh interrupt flag bits corresponding to all local DMA forwarding queues and values corresponding to the interrupt flag bits into an assigned storage space in the multicore CPU, and restore the values of all interrupt flag bits to the initial values, so that when the control core receives the DMA interrupt request, send a DMA interrupt response used for representing that the DMA interrupt request has been received by the control core to the forwarding chip through the PCIE channel, query the interrupt flag bits whose values are set values stored in the assigned storage space, and wake up a service core in the multicore CPU, which needs to forward a service packet in a DMA forwarding queue corresponding to the queried interrupt flag bits, to forward the service packet in the corresponding DMA forwarding queue, so that after the service core has forwarded the service packet in the corresponding DMA forwarding queue, sending a forwarding completion message to the forwarding chip through the PCIE channel;

a judging module 54, configured to, when receiving the DMA interrupt response sent by the control core and the forwarding completion message sent by the service core, judge whether there is a generated and unreported DMA interrupt request locally, and if yes, take the generated and unreported DMA interrupt request whose generation time is closest to the generation time of the DMA interrupt request as the DMA interrupt request, and trigger the setting module 52 to perform a step of setting a value of an interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

a waiting module 55, configured to execute a waiting operation when the determination result of the determining module 54 is negative, and when it is waited that a new DMA interrupt request is generated, take the new DMA interrupt request as the DMA interrupt request, and trigger the setting module 52 to execute a step of setting the value of the interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value.

Preferably, the apparatus further comprises:

a determining module (not shown in fig. 5) configured to determine a service packet that meets a preset condition and is received by itself in the following manner:

if the timer arranged on the self is monitored to be overtime but the total number of the service messages received in the overtime duration of the timer is not more than the set number, determining all the service messages received in the overtime duration as the self-received service messages meeting the preset conditions;

if the timer is monitored not to be overtime but the set number of service messages are received, determining the received set number of service messages as the service messages meeting the preset conditions received by the self.

Preferably, the processing module 53 is further configured to:

after the DMA interruption request is reported to the control core through the PCIE channel, if the DMA interruption response sent by the control core through the PCIE channel is not received within a set time length, the DMA interruption request is reported to the control core through the PCIE channel again.

The present application further provides an interrupt processing apparatus, which is applied to a control core in a multi-core CPU in a forwarding device, and a schematic structural diagram of the apparatus is shown in fig. 6, and specifically includes:

a transceiver module 61, configured to send, to a forwarding chip in the forwarding device through a PCIE channel, a DMA interrupt response used to represent that the control core has received the DMA interrupt request when receiving a DMA interrupt request sent by any forwarding chip in the forwarding device, where the DMA interrupt request is generated after the forwarding chip writes, in a DMA manner through the PCIE channel, a plurality of determined service messages that are received by itself and meet a preset condition into a DMA forwarding queue for storing the service messages in the multi-core CPU at any time;

the query and wake-up module 62 is configured to query an interrupt flag stored in an assigned storage space of the multi-core CPU, where the value is a set value, and wake up a service core in the multi-core CPU, which needs to forward a service packet in a DMA forwarding queue corresponding to the queried interrupt flag, to forward the service packet in the corresponding DMA forwarding queue, so that the service core sends a forwarding completion message to the forwarding chip through the PCIE channel after forwarding the service packet in the corresponding DMA forwarding queue; the specified storage space stores the interrupt flag bits corresponding to all DMA forwarding queues on the forwarding chip refreshed by the forwarding chip and the corresponding values thereof, and in the interrupt flag bits corresponding to all DMA forwarding queues, the value of the interrupt flag bit corresponding to the DMA forwarding queue is set as a set value by the forwarding chip after the DMA interrupt request is reported by the forwarding chip, and the values of the rest interrupt flag bits are initial values.

The subsequent control core also wakes up a service core in the multi-core CPU, which needs to forward the service message in the DMA forwarding queue corresponding to the queried interrupt flag bit, to forward the service message in the corresponding DMA forwarding queue, so that the forwarding chip sends a forwarding completion message to the forwarding chip through the PCIE channel after the service core finishes forwarding the service message in the corresponding DMA forwarding queue, so that the forwarding chip can continue to report the next generated interrupt request only under the condition of receiving a DMA interrupt response sent by the control core for the current generated DMA interrupt request and a forwarding completion message sent by the relevant service core for the service message in the DMA forwarding queue corresponding to the current generated DMA interrupt request, thereby avoiding the problem that the DMA interrupt request is reported more or is not reported.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. An interrupt processing method is applied to any forwarding chip in a forwarding device, and comprises the following steps:

after writing a plurality of determined self-received service messages meeting preset conditions into a DMA (direct memory access) forwarding queue for storing the service messages in a multi-core CPU (central processing unit) in the forwarding equipment in a DMA mode through a PCIE (peripheral component interface express) channel for the first time, generating a DMA interrupt request corresponding to the DMA forwarding queue;

reporting the DMA interrupt request to a control core in the multi-core CPU through the PCIE channel, refreshing interrupt flag bits corresponding to all local DMA forwarding queues and corresponding values thereof to a designated storage space in the multi-core CPU, restoring the values of all the interrupt flag bits to the initial values so that when the control core receives the DMA interrupt request, sending a DMA interrupt response for representing that the control core has received the DMA interrupt request to the forwarding chip through the PCIE channel, inquiring the interrupt flag bits of which the values are set values and which are stored in the designated storage space, waking up a service core in the multi-core CPU, which needs to forward the service messages in the DMA forwarding queues corresponding to the inquired interrupt flag bits, to forward the service messages in the corresponding DMA forwarding queues so that the service core forwards the service messages in the corresponding DMA forwarding queues, sending a forwarding completion message to the forwarding chip through the PCIE channel;

if so, taking the generated and unreported DMA interrupt request with the generation time closest to the generation time of the DMA interrupt request as the DMA interrupt request, and executing the step of setting the value of the interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value;

and if the judgment result is negative, executing a waiting operation, taking a new DMA interrupt request as the DMA interrupt request when waiting for the generation of the new DMA interrupt request, and executing the step of setting the value of the interrupt flag bit corresponding to the local DMA forwarding queue from an initial value to a set value.

2. The method according to claim 1, wherein the service packet received by the method and meeting the preset condition is determined by:

if the timer is monitored not to be overtime but the set number of service messages are received, determining the received set number of service messages as the service messages which meet the preset conditions and are received by the self.

3. The method of claim 1, further comprising:

4. An interrupt processing method, applied to a control core in a multi-core CPU in a forwarding device, the method comprising:

when a DMA interrupt request sent by any forwarding chip in the forwarding equipment is received, sending a DMA interrupt response used for representing that the control core has received the DMA interrupt request to the forwarding chip through a PCIE channel, wherein the DMA interrupt request is generated after the forwarding chip writes a plurality of determined service messages which are received by the forwarding chip and meet preset conditions into a DMA forwarding queue used for storing the service messages in the multi-core CPU through the PCIE channel in a DMA mode at any time;

inquiring an interrupt flag bit with a value as a set value stored in a designated storage space in the multi-core CPU, awakening a service core, which needs to forward a service message in a DMA forwarding queue corresponding to the inquired interrupt flag bit, in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, and sending a forwarding completion message to the forwarding chip through the PCIE channel after the service core finishes forwarding the service message in the corresponding DMA forwarding queue; the interrupt flag bits corresponding to all the DMA forwarding queues refreshed by the forwarding chip and the corresponding values of the interrupt flag bits are stored in the designated storage space, the interrupt flag bits corresponding to the DMA forwarding queues are set to be a set value from an initial value after the DMA interrupt request is reported by the forwarding chip in the interrupt flag bits corresponding to all the DMA forwarding queues, and the values of the rest interrupt flag bits are the initial value.

5. An interrupt processing apparatus, wherein the apparatus is applied to any forwarding chip in a forwarding device, the apparatus comprising:

6. The apparatus of claim 5, further comprising:

the determining module is used for determining the service message which meets the preset conditions and is received by the determining module in the following modes:

7. The apparatus of claim 5, wherein the processing module is further configured to:

8. An interrupt processing apparatus applied to a control core in a multi-core CPU in a forwarding device, the apparatus comprising:

a transceiver module, configured to send, to a forwarding chip through a PCIE channel, a DMA interrupt response used to characterize that the control core has received the DMA interrupt request when receiving a DMA interrupt request sent by any forwarding chip in the forwarding device, where the DMA interrupt request is generated after the forwarding chip writes, in a DMA manner through the PCIE channel, a plurality of determined service messages that are received by itself and meet a preset condition, into a DMA forwarding queue in the multi-core CPU for storing the service messages at any time;

the inquiry and wake-up module is used for inquiring an interrupt flag bit which is stored in a designated storage space in the multi-core CPU and takes a value as a set value, and waking up a service core which needs to forward a service message in a DMA forwarding queue corresponding to the inquired interrupt flag bit in the multi-core CPU to forward the service message in the corresponding DMA forwarding queue, so that the service core sends a forwarding completion message to the forwarding chip through the PCIE channel after forwarding the service message in the corresponding DMA forwarding queue; the interrupt flag bits corresponding to all the DMA forwarding queues refreshed by the forwarding chip and the corresponding values of the interrupt flag bits are stored in the designated storage space, the interrupt flag bits corresponding to the DMA forwarding queues are set to be a set value from an initial value after the DMA interrupt request is reported by the forwarding chip in the interrupt flag bits corresponding to all the DMA forwarding queues, and the values of the rest interrupt flag bits are the initial value.