CN115033433A - Anomaly detection device based on brain new cortex mechanism - Google Patents
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Abstract
The invention relates to the technical field of data anomaly detection, in particular to an anomaly detection device based on a new cortical layer mechanism of a brain. The invention relates to a computer accessory, which is a universal anomaly detection device and can be used in application scenes such as equipment operation and maintenance, alarming and the like.
Description
Technical Field
The invention relates to the technical field of data anomaly detection, in particular to an anomaly detection device based on a new cortex mechanism of a brain.
Background
The detection of various data anomalies is one of the important tasks of various service maintenance. However, the existing anomaly detection technology is usually performed by using a machine learning (ES, MA, ARIMA, SVM, etc.) algorithm or a deep learning (LSTM-AD, LSTM-ED, etc.) algorithm, and the disadvantages of the methods are obvious, for example, the precision of the machine learning scheme is low, the robustness is poor, and the method is only suitable for a specific scene; the deep learning scheme is that the training is complex, a large amount of data is required to be trained, the model is large, the required machine calculation force is large, the cost is high, and the implementation by using cheap embedded hardware is difficult.
Disclosure of Invention
The present invention provides an abnormality detection device based on the mechanism of the new cortex of the brain to solve the above problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
the abnormality detection device comprises a multi-core controller, a cortical column assembly and a neuron assembly, and is connected with a PC mainboard through a PCIe interface.
Further, the multi-core controller comprises an instruction register, a counter register and a decode register,
the output terminals of the counter register and the register are both linked to the second input terminal of the first data selector,
the output terminal of the instruction register is linked to the first input terminal of the first data selector,
the output terminal of the decoding register is linked to the input terminal of the second data selector,
two output terminals of the second data selector are respectively linked with a data input terminal of the bit overlap array and a bit data input terminal of the winning neuron storage component,
the data output terminal of the bit-overlapped array links the input terminal of the sorting element,
the output terminal of the ordering component is linked to the bit data input terminal of the cortical pillar storage component,
the data output terminal of the winning cortical pillar storage component is connected to the fourth input terminal of the first data selector,
the data output terminal of the winning neuron storage component is linked to the third input terminal of the first data selector,
the bit data input terminals of the winning neuron storage component and the bit overlap array are respectively linked with two output terminals of the second data selector,
the output terminal of the second data selector is linked to the input terminal of cortical pillar data.
Further, the cortical pillar assembly includes a primary bus,
the main bus output terminal is connected with the second path input terminal and the third path input terminal of the first data selector,
a fourth way input terminal of the first data selector is linked to an input terminal of a first synapse persistence value register,
the output terminal of the first data selector is linked to the bit data input terminal of the partition1 portion of the 64-byte memory, the output terminal of the first data selector is also output to a neuron,
the data output terminal of partition2 portion of the 64byte memory is linked to the input terminal of a third data selector,
a first output terminal of the third data selector is linked to an input terminal of a second synapse persistence value register,
a second output terminal of the third data selector is linked to an input terminal of a synaptic address register,
the third path output terminal and the fourth path output terminal of the third data selector are linked with the input terminal of an activated address 8-bit register together,
the output terminal of the synaptic address register is linked through a first data distributor to the input terminal of an active address 8-bit register,
the active address 8-bit register is linked to an overlap count register by a logical operation,
the second synaptic permanent value register is linked to a second data distributor,
a first output terminal of the second data distributor is linked to an input terminal of an overlap count register by a sort operation,
the second way output terminal of the second data distributor outputs data through an inversion operation, the inversion operation output data is linked to the first way input terminal of the first data selector linked with the partition1 part of the 64-byte memory,
the information carried by the overlapping counting register and the neuron is linked with a pipeline register through a first data selector, and an output end chain of the pipeline register is linked to the multi-core controller.
Further, the 64-byte memory further comprises a partition3 part, wherein the partition3 part is linked with a count register, and the count register is respectively linked with four input terminals of an address count register, a synapse permanent value count register, a bit register and a synapse address register through a first data selector.
Further, the neuron component includes multi-phase information of a plurality of cortical pillars,
the multi-phase information of the plurality of cortical pillars is linked to a neuron time series store by a logical operation,
the neuron time series stores an interlink controller,
each unit of the controller is linked to a time series store of neurons at the last time from the input of the decoding register.
Further, the neuron component further comprises an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition respectively, and the multiphase information of the plurality of cortical pillars is further linked to the controller through a cortical pillar state register.
Further, the amplification processing module comprises a synapse persistence value register and a neuron register, the synapse persistence value register being linked to a count register by a threshold-defining ordering operation,
the output end of the counting register is linked to the learning channel, the output end of the neuron register is linked to the learning channel,
the output end of the learning channel is linked to a cortical post.
Further, the learning processing module comprises a segment register, a segment update register and a synapse persistence value register,
and the segment register and the segment updating register are output to the controller and the synapse comparison vector register through sequencing operation.
Further, the prediction processing module includes a current value register and a segment register,
the previous value register and the segment register are linked with the counter register through the logical operation output,
the counter register is linked to the individual cells of the neuron state register by a sorting operation that defines a threshold value,
the identification of each cell of the neuron state register comprises a learning state flag and a neuron state.
Further, the segment storage partition is divided into a segment update storage partition, a previous content storage partition, and a permanent value storage partition,
the previous content memory partition is respectively linked with a segment permanent value address register, a segment update address register and a previous segment address register through a first data selector;
the output terminal of the first data selector links bit data input terminals of segment storage partitions,
a first input terminal of the first data selector is linked to an initial synapse persistence value register,
the second input terminal of the first data selector is linked with the multiphase information of a plurality of cortical columns and the multiphase information of the plurality of cortical columns is also linked with the controller through a logical operation output,
a third input terminal of the first data selector is linked to a synapse comparison vector register and a synapse persistence value register in a learning processing module,
a fourth input terminal of the first data selector is linked with a memory buffer register;
and the permanent value storage partition is respectively output through a fourth data selector and a data output and linked memory buffer register, a synapse permanent value register in the amplification processing module, a segment register in the prediction processing module, a neuron register in the amplification processing module, a synapse permanent value register in the learning processing module, a segment register in the learning processing module, a current value register in the prediction processing module and a segment update register in the learning processing module.
Compared with the prior art, the invention has the beneficial effects that: the invention is an intelligent hardware card of PCIe interface, it is a device of software and hardware, similar to FPGA, some functions are finished by hardware, some functions can be realized by programming, the whole device is presented as hardware equipment, realize plug and play, but carry on data input and result return through SDK, can realize the general algorithm of various data abnormal detection, can do abnormal detection of various services according to the difference of the input data, for example: sensors, human behavior, and vehicle trajectory.
The invention is based on the anomaly detection algorithm design device based on space-time which simulates part of the human brain new cortex cognition system mechanism to realize the hardware of the algorithm; the design has high prediction precision, has good inhibition effect on noise in real-time data, can continuously learn, continuously enhances the adaptation to scenes, requires small training data volume, has high hardware realization operation speed and general scenes, and compared with the realization mode of a common GPU card, realizes similar functions with low cost and does not need to carry out anomaly detection software development.
Drawings
FIG. 1 is a representation design diagram of a multi-core master controller RTL in the invention;
FIG. 2 is a schematic representation of the RTL design of cortical pillars in the present invention;
fig. 3 is a diagram showing the RTL expression of neurons in the present invention.
In the figure: PRG: instruction Register, Register: register, Counter: counter register, Decoder: a decode register; DMUX: a data distributor (1-to-2 DMUX is the second data distributor); overlay Array: a bit overlap array; din: inputting bit data; dout: outputting data; en: inputting data; winning cells RAM: a winning neuron storage component; sorting Unit: a sorting component; winning col, RAM: a winning cortical post storage assembly; MainBus: main bus pipe register: a pipeline register; overlapCNT: an overlap count register; ActiAddr (8-bit): activating an address 8-bit register; SynpAddr: a synaptic address register; PermV: a second synaptic permanent value register (for cortical pillar permanent value information storage); PermTh: a synapse permanence value threshold input; RAM (64 bytes): a 64byte memory; CNT: a count register; AddrCNT: an address count register; PermCNT: a synapse permanent value counting register; InBITCNT: a bit register; SynpAddr [ 7: 3 ] A step of: a synaptic address register; and MUX: a data selector; initial.perm.: an initial synapse persistence value register; cellsiteline: storing a neuron time series; cell Status Register; burst _ Block: an amplification processing module; learning _ Block; prediction _ Block, Prediction processing module; segment: a segment register; counter: a counter register; current: a current value register; ch _ spare: a learning channel; SynpMatchVec: a synaptic comparison vector register; SynpPerm: a synapse permanent value register; cell/segm.: a neuron register; up.: a segment update register; m, buffer is memory buffer register; ColStatus: a cortical column status register; SegPermAddr: a segment permanent value address register; SegAddr: a segment address register; SegUpAddr: segment update address registers; PriorAddr: a front segment address register; CNT: a counter register; segment Partition: a segment storage partition; segment up. Segment update storage partitions; PriorMemPratition: a previous content storage partition; the Permance Partition: permanent value storage partition, CCU: a communication controller; cell: a neuron; MCU: a multi-core controller; CU: a controller; learning Flag: a learning status flag; cell Status: a neuron state flag; column: a cortical column; a first data selector: a data selector with 4 input terminals and 1 output terminal; a second data selector: a data selector with 1 input terminal and 2 output terminals; a third data selector: a data selector with 1 input terminal and 4 output terminals; a fourth data selector: a data selector with 1 input terminal and 8 output terminals; the first data distributor: a data distributor having 1-channel input terminal and 8-channel output terminal; the second data distributor: a data distributor having 1-way input terminal and 2-way output terminal.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1-3, an abnormality detection device based on a new cortical layer mechanism of a brain includes a multi-core controller, a cortical pillar component and a neuron component, and the abnormality detection device is connected to a PC motherboard through a PCIe interface.
Specifically, the multi-core master controller is used for controlling and coordinating the cortical pillar component and the neuron component to carry out operation; the abnormality detection device is composed of a multi-core controller, a cortical post assembly and a neuron assembly, realizes abnormality detection by using hardware, and can communicate with other computer software and hardware by inserting a PCIe interface of a PC mainboard.
Furthermore, the multi-core master controller is used for carrying out logic control on the whole system and scheduling data.
Referring to fig. 1, a multi-core controller RTL expression obtained by an abnormality detection device based on a new cortex mechanism of a brain includes an instruction register, a counter register, and a decode register, where the register stores original input data from an acquisition encoder; the counter register is used for calculating the processing times, namely the number of network layers; a decoding register for receiving the result data from the processing of the previous cortical pillar region; the counter register and the register are combined into a same input terminal and are linked to a second input terminal of the first data selector, the output of the instruction register is linked to a first input terminal of the first data selector, the decoding register is linked to an input terminal of the second data selector, two output terminals of the second data selector are respectively linked with a data input terminal of a bit overlap array and a bit data input terminal of a winning neuron storage component, the bit overlap array is a storage component with corresponding same numerical values in the two arrays, the winning neuron storage component is used for storing neuron information which is winning in competition, the data output of the bit overlap array is linked with a sorting component, the sorting component is composed of a comparator and a register, the overlapped arrays are compared and sorted, Top 20% of the overlapped arrays are selected and transmitted to the winning cortical pillar storage component, and the winning cortical pillar storage component is used for storing the winning cortical pillar information, in the learning stage, data are transmitted to the cortical pillar component through the MUX, the output of the sorting component is linked with a terminal of a bit data input of the cortical pillar storage component, neuron information of competition success is stored, the data output of the winning cortical pillar storage component is linked with a fourth input terminal of the first data selector, the data output of the winning neuron storage component is linked with a third input terminal of the first data selector, the data input of the winning neuron storage component and the data input of the bit overlap array are respectively linked with two output terminals of the second data selector, and the input terminal of the second data selector is linked with cortical pillar data.
Furthermore, the cortical pillar component mainly processes the competitive winning state of the cortical pillar and coordinates and controls the neurons in the cortical pillar, and the communications are carried out through the bus and the neurons.
Referring to fig. 2, a cortical pillar component RTL obtained by an anomaly detection apparatus based on a new cortical layer mechanism of a brain includes a main bus, where the main bus transmits addresses of various data, such as a synapse data address (syncaddr) and a Winner Addr; the main bus output links the second input terminal and the third input terminal of the first data selector, the fourth input terminal of the first data selector is linked with the synapse permanent value register, one output terminal of the first data selector is linked with the terminal of the bit data input of the partition1 part of the 64-byte memory and is output to the neuron, the data output of the partition2 part of the 64-byte memory is linked with a third data selector, the first output terminal of the third data selector is linked with the synapse permanent value register, the second output terminal of the third data selector is linked with the synapse address register, the synapse address register stores the dendrite address, the third and fourth output terminals of the third data selector are linked with the active address 8-bit register in common, the active address 8-bit register stores the active cortical pillar address, the synapse address register is linked with the active address 8-bit register through a first data distributor, the 8-bit register of the activation address is linked to the overlap count register through a logic operation, the synapse permanent value register stores cortical pillar permanent value information, the synapse permanent value register is linked with a second data distributor, and the data distributor (1-way input terminal and 2-way output terminal) is used for distributing data to the bit overlap array storage component and the winner storage component; the first output terminal of the second data distributor is linked to the overlapping count register through sequencing operation, the second output terminal of the second data distributor is linked to the first input terminal of the first data selector linked with the partition1 part of the 64-byte memory through inversion operation, the overlapping count register and the neuron information are both linked to the pipeline register through the first data selector, the pipeline register is used for storing processing step information, the overlapping count register stores overlapping count, and the output of the pipeline register is linked to the multi-core controller.
Furthermore, the 64-byte memory further comprises a partition3 part, a partition3 part is linked with a count register, and the count register is respectively linked with four input terminals of the address count register, the synapse permanent value count register, the bit register and the synapse address register through a first data selector. It should be noted that, 3 parts of the 64-byte memory respectively store the permanent value of synapse, the address of synapse in the input space, and the address of winner (Active Bits/Winners Addr).
Referring to fig. 3, a neuron element RTL representation obtained by an abnormality detection device based on a new cortical layer mechanism of a brain includes multi-phase information of a plurality of cortical pillars, the multi-phase information of the plurality of cortical pillars is linked to a neuron time series storage through a logical operation output, the neuron time series storage is interactively linked with a controller, each unit of the controller inputs the neuron time series storage linked to the previous time from a decoding register, the neuron element further includes an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition, and the information of the cortical pillars is further linked to the controller through a cortical pillar state register.
Specifically, the last time refers to that the discrete timing sequence t corresponds to the time t-1, the time t-1 corresponds to the time t-2, and so on.
Further, the amplification processing module comprises a synapse permanent value register and a neuron register, wherein the synapse permanent value register is linked to a counting register through ordering operation of a limited threshold, the output of the counting register is linked to a learning channel, the neuron register is also output to the learning channel, and the learning channel is output to a cortical pillar; the learning processing module comprises a segment register, a segment updating register and a synapse permanent value register, and the segment register and the segment updating register are output to the controller and the synapse comparison vector register through sequencing operation; the prediction processing module comprises a current value register and a segment register, the previous value register and the segment register are output through logic operation and are linked with a counter register, the counter register is linked to each cell of the neuron state register through sorting operation of a limited threshold value, and the identification of each cell of the neuron state register comprises a learning state mark and a neuron state.
It is further explained that the neuron Status register is used to store the Status of the neuron, and the Learning Status Flag (Learning Flag) and the neuron Status (Cells Status) are used to identify whether the neuron is in an activated, inactivated, or predicted state.
Further, a neuron component RTL expression obtained by the anomaly detection device based on a new cortex mechanism of a brain is characterized in that a segment storage partition is divided into a segment updating storage partition, a previous content storage partition and a permanent value storage partition, wherein the previous content storage partition is respectively linked with a segment permanent value address register, a segment updating address register and a previous segment address register through a first data selector;
the segment storage partition is connected with a terminal of a data input of the segment storage partition through an output terminal sub-link of a first data selector, a first input terminal sub-link of the first data selector is connected with an initial synapse permanent value register, a second input terminal sub-link of the first data selector is connected with information of a cortex column, the information of the cortex column is further connected with an output link controller through logic transportation, a third input terminal sub-link of the first data selector is connected with a sorting transportation result of a touch comparison vector register and a synapse permanent value register in a learning processing module, and a fourth input terminal sub-link of the first data selector is connected with a memory buffer register;
the permanent value storage partition respectively outputs a linked memory buffer register, a synapse permanent value register in the amplification processing module, a segment register in the prediction processing module, a neuron register in the amplification processing module, a synapse permanent value register in the learning processing module, a segment register in the learning processing module, a current value register in the prediction processing module and a segment update register in the learning processing module through a fourth data selector through data output of the permanent value storage partition.
Further, the neuron element mainly processes activation of neurons, transition of learning state, and neuron excitation and inhibition processes. The system is initialized by the value of the initial synapse permanent value register, the neuron is in idle state after initialization, when the neuron in the cortical pillar receives the notification, the neuron in the cortical pillar in the prediction state is selected as the input representation, if no neuron in the cortical pillar is in an activated state, all neurons are activated, amplification processing (bursting) is carried out, a specific comparison method is to compare whether the neuron is in a predicted state or not according to previous information stored in a neuron time sequence, activating neurons if there are neurons in the cortical pillar that are in a predicted state, activating neurons if neurons in the cortical pillar are in a learning state, the neurons are updated to a learning state and all neurons are updated to an active state if there are no neurons in a predicted state. The most matched neuron is then selected as the input to the amplification processing module (Burst _ Block), and the address of the activated neuron is then transferred from the previous content storage partition (priormpivot) to the segment update storage partition (segment _ partition) via the memory buffer register (m.buffer). The number of activated neurons in the cortical column will then be transmitted to the multinuclear Master Controller (MCU) through the pipeline register (pipeline register) of the cortical column assembly. The master controller will update the distribution of activated neurons. A new segment store is created if the selected neuron is the winner. If it is a non-winner, the Prediction processing module (Prediction _ Block) is triggered if the neuron is in an inactive state and there is an active segment. The prediction processing module compares the segment register and the current register, and if the matching image is more than 50%, the neuron is updated to a prediction state. Otherwise, checking whether the current state is a prediction state, if the current state is the prediction state and is in an activation state, enhancing the permanent synapse value, and otherwise weakening the synapse value for inhibition processing. This phase triggers a Learning processing module (Learning _ Block) that compares the contents of the Segment register (Segment) and Segment update register (Segment. up.) and enhances the linkage of synapses if there is an address matching the synapse comparison vector register (SynpMatchVec), otherwise it is forwarded as a Segment storage Partition (Segment Partition).
The sorting operation means that the input values are rearranged according to a certain sorting rule and then output into a new input value sequence to enter another operation area; the sorting operation of the limited threshold value refers to that the sorting operation is carried out on input values within the value of the threshold value, and then the input values are output according to a sequence; the logical operation refers to an operation on an input value by a logical manner such as nand inversion.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and the preferred embodiments of the present invention are described in the above embodiments and the description, and are not intended to limit the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. The utility model provides an unusual detection device based on new cortex mechanism of brain which characterized in that: the abnormality detection device comprises a multi-core controller, a cortical post assembly and a neuron assembly, and is connected with a PC mainboard through a PCIe interface.
2. The apparatus for detecting abnormality based on mechanism of cortex neoformae cerebri according to claim 1, characterized in that: the multi-core controller comprises an instruction register, a counter register and a decoding register,
the output terminals of the counter register and the register are both linked to the second input terminal of the first data selector,
the output terminal of the instruction register is linked to the first input terminal of the first data selector,
the output terminal of the decoding register is linked to the input terminal of the second data selector,
two output terminals of the second data selector are respectively linked with a data input terminal of the bit overlap array and a bit data input terminal of the winning neuron storage component,
the data output terminal of the bit overlap array is linked to the input terminal of the ordering element,
the output terminal of the ordering component is linked out of the bit data input terminal of the cortical pillar storage component,
the data output terminal of the winning cortical pillar storage component is connected to the fourth input terminal of the first data selector,
the data output terminal of the winning neuron storage component is linked to the third input terminal of the first data selector,
the bit data input terminals of the winning neuron storage component and the bit overlap array are respectively linked with two output terminals of the second data selector,
the output terminal of the second data selector is linked to the input terminal of cortical pillar data.
3. The apparatus for detecting abnormality based on mechanism of cortex neoformae cerebri according to claim 1, characterized in that: the cortical pillar assembly includes a primary bus that,
the main bus output terminal is connected with the second path input terminal and the third path input terminal of the first data selector,
a fourth way input terminal of the first data selector is linked to an input terminal of a first synapse persistence value register,
the output terminal of the first data selector is linked to the bit data input terminal of the partition1 portion of the 64-byte memory, the output terminal of the first data selector is also output to a neuron,
the data output terminal of the partition2 portion of the 64byte memory is linked to the input terminal of a third data selector,
a first output terminal of the third data selector is linked to an input terminal of a second synapse persistence value register,
a second output terminal of the third data selector is linked to an input terminal of a synapse address register,
the third and fourth output terminals of the third data selector are commonly linked with the input terminal of an activated address 8-bit register,
the output terminal of the synaptic address register is linked through a first data distributor to the input terminal of an active address 8-bit register,
the active address 8-bit register is linked to an overlap count register by a logical operation,
the second synaptic permanent value register is linked to a second data distributor,
the first output terminal of the second data distributor is linked to the input terminal of the overlap count register by a sort operation,
the second way output terminal of the second data distributor outputs data through an inversion operation, the inversion operation output data is linked to the first way input terminal of the first data selector linked with the partition1 part of the 64-byte memory,
the information carried by the overlapping counting register and the neuron is linked with a pipeline register through a first data selector, and an output end chain of the pipeline register is linked to the multi-core controller.
4. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 3, wherein: the 64-byte memory further comprises a partition3 part, wherein the partition3 part is linked with a count register, and the count register is respectively linked with four input terminals of an address count register, a synapse permanent value count register, a bit register and a synapse address register through a first data selector.
5. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 1, wherein: the neuron component includes multi-phase information of a plurality of cortical pillars,
the multi-phase information of the plurality of cortical pillars is linked to a neuron time series store by a logical operation,
the neuron time series stores an interlink controller,
each unit of the controller is linked to a time series store of neurons at the last time from the input of the decoding register.
6. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 1, wherein: the neuron components further respectively comprise an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition, and the multiphase information of the plurality of cortical columns is further linked to the controller through a cortical column state register.
7. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 6, wherein: the amplification processing module comprises a synapse persistence value register and a neuron register, the synapse persistence value register being linked to a count register by a threshold-defining ordering operation,
the output end of the counting register is linked to the learning channel, the output end of the neuron register is linked to the learning channel,
the output end of the learning channel is linked to a cortical post.
8. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 6, wherein: the learning processing module comprises a segment register, a segment update register and a synapse permanent value register,
and the segment register and the segment updating register are output to the controller and the synapse comparison vector register through sequencing operation.
9. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 6, wherein: the prediction processing module includes a current value register and a segment register,
the previous value register and the segment register are linked with the counter register through the logical operation output,
the counter register is linked to the individual cells of the neuron state register by a sorting operation that defines a threshold value,
the identification of each cell of the neuron state register comprises a learning state flag and a neuron state.
10. The apparatus for detecting abnormality based on mechanism of neocortex of brain according to claim 6, wherein: the segment storage partition is divided into a segment update storage partition, a previous content storage partition and a permanent value storage partition,
the previous content memory partition is respectively linked with a segment permanent value address register, a segment update address register and a previous segment address register through a first data selector;
the output terminal of the first data selector links bit data input terminals of segment storage partitions,
a first input terminal of the first data selector is linked to an initial synapse persistence value register,
the second input terminal of the first data selector is linked with the multiphase information of a plurality of cortical columns and the multiphase information of the plurality of cortical columns is also linked with the controller through a logical operation output,
a third input terminal of the first data selector is linked to a synapse comparison vector register and a synapse persistence value register in a learning processing module,
a fourth input end of the first data selector is connected with a memory buffer register in a sub-link mode;
and the permanent value storage partition is respectively output through a fourth data selector and a data output and linked memory buffer register, a synapse permanent value register in the amplification processing module, a segment register in the prediction processing module, a neuron register in the amplification processing module, a synapse permanent value register in the learning processing module, a segment register in the learning processing module, a current value register in the prediction processing module and a segment update register in the learning processing module.
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