CN115033420A

CN115033420A - NAND flash memory dynamic voltage writing method and device

Info

Publication number: CN115033420A
Application number: CN202210790252.3A
Authority: CN
Inventors: 方毅; 蔡润彬; 史志芳; 韩国军; 刘畅
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2022-07-06
Filing date: 2022-07-06
Publication date: 2022-09-09

Abstract

The invention relates to the technical field of data storage, in particular to a dynamic voltage writing method and a dynamic voltage writing device for an NAND flash memory, and discloses the dynamic voltage writing method and the dynamic voltage writing device for the NAND flash memory, wherein the method comprises the following steps: constructing a cost function according to the high-order channel error rate, the low-order channel error rate and the minimum Hamming distance estimated by the LDPC code; the method comprises the steps of taking the minimum function value of the cost function as an optimization target, taking the first programming voltage and the second programming voltage as independent variables, carrying out convex optimization calculation on the cost function, and outputting the optimal first programming voltage and the optimal second programming voltage.

Description

NAND flash memory dynamic voltage writing method and device

Technical Field

The invention relates to the technical field of data storage, in particular to a dynamic voltage writing method and device for a NAND flash memory.

Background

With the advent of the intelligent age, the storage of large volumes of data has become a new challenge. The solid state disk based on the flash memory has the advantages of large capacity and low power consumption, gradually replaces the traditional storage medium, and becomes one of the mainstream storage devices, especially the NAND flash memory.

NAND flash memory is a non-volatile memory device that is made up of many blocks, each containing many pages. A block is composed of word lines (word-lines) and bit lines (bit-lines), and a memory cell (cell) is located at the intersection of the word lines and the bit lines. Each word line contains one or more pages of user data, and all bit lines in a block are connected to a source line (source line) so that when an erase operation is performed, all memory cells in the block are erased. When writing data, only a high voltage needs to be applied to the corresponding word line, and then the bit line voltage at the corresponding position needs to be adjusted.

After the NAND flash memory writes data, the voltage distribution in the flash memory is approximately Gaussian distribution. The voltage exhibited by the flash cell after the injection of electrons is called the threshold voltage. Taking MLC type NAND flash as an example, under Gray mapping, a flash memory cell can be configured with four different levels, respectively V _min 、V ₁ 、V ₂ 、V _max They may represent data symbols "11", "10", "00", "01", respectively. Generally, the bits on the left side of the symbol are called high order bits (MSB) and the bits on the right side are called low order bits (LSB), and we regard all the high order bits on a page of flash memory as a high order bit page and all the low order bits as a low order bit page.

Before writing data into MLC type NAND flash memory unit, the whole block of data is erased to change the voltage in the flash memory unit to the lowest voltage V _min And then writing the respective data into the flash memory cells. Thus, V _min Called erase level or minimum write voltage, V _max Is the maximum write level, V ₁ 、V ₂ Is the programming level. In practical application, the minimum write voltage and the maximum write voltage are fixed, and the optimal programming level V is obtained by solving the minimum channel error rate ₁ 、V ₂ Data writing is performed.

However, in the above data writing scheme, when the codeword is stored only in the upper bit page or the lower bit page, the total error rate performance is deteriorated by continuing to use the above method of writing data because the channel error rates of the upper and lower bits are not equal.

Disclosure of Invention

The invention provides a dynamic voltage writing method and a dynamic voltage writing device for a NAND flash memory, which are used for improving the total error rate performance of the NAND flash memory.

The invention provides a dynamic voltage writing method for a NAND flash memory, wherein the writing voltage comprises a first programming voltage and a second programming voltage, and the method comprises the following steps:

constructing a cost function according to the high-order channel error rate, the low-order channel error rate and the minimum Hamming distance estimated by the LDPC code;

and performing convex optimization calculation on the cost function by taking the minimum function value of the cost function as an optimization target and the first programming voltage and the second programming voltage as independent variables, and outputting the optimal first programming voltage and the optimal second programming voltage.

Optionally, the performing convex optimization calculation on the cost function by using the minimum function value of the cost function as an optimization target and the first programming voltage and the second programming voltage as arguments to output the optimal first programming voltage and the optimal second programming voltage includes:

s0: acquiring flash memory channel parameters, wherein the flash memory channel parameters comprise a first numerical range of a first programming voltage and a second numerical range of a second programming voltage;

s1: selecting one second programming voltage value from the second value range as an initial value of a second programming voltage;

s2: uniformly selecting M first programming voltage values from the first value range, and combining the M first programming voltage values with the initial value of the second programming voltage to form M groups of first writing voltages, wherein M is a constant;

s3: calculating M groups of cost function values corresponding to the first writing voltage, and determining the optimal first programming voltage corresponding to the minimum cost function value;

s4: uniformly selecting M second programming voltage values from the second value range, and forming M groups of second writing voltages by the M second programming voltage values and the optimal first programming voltage respectively;

s5: calculating cost function values corresponding to the M groups of second writing voltages, and determining an optimal second programming voltage corresponding to the minimum cost function value;

s6: replacing the initial value of the second programming voltage with an optimal second programming voltage;

s7: and iterating S2-S6 until an iteration termination condition is met, and outputting the optimal first programming voltage and the optimal second programming voltage.

Optionally, the flash channel parameters further include a maximum write voltage and a minimum write voltage, and the S3 specifically includes:

respectively generating M groups of first threshold voltage distribution graphs according to the M groups of first write voltages, the maximum write voltage and the minimum write voltage;

determining M sets of first curve intersections from the M sets of first threshold voltage distribution plots;

respectively substituting the M groups of first curve intersections into a high-low channel error rate calculation formula to obtain high-low channel error rates, and substituting the high-low channel error rates into the cost function to obtain M groups of cost function values;

determining a first curve intersection point corresponding to the minimum cost function value from M sets of cost function values;

and determining the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

Optionally, the S5 specifically includes:

respectively generating M groups of second threshold voltage distribution graphs according to the M groups of second writing voltages, the maximum writing voltage and the minimum writing voltage;

determining M groups of second curve intersections from the M groups of second threshold voltage distribution plots;

respectively substituting the M groups of second curve intersections into a high-low channel error rate calculation formula to obtain high-low channel error rates, and substituting the high-low channel error rates into the cost function to obtain M groups of cost function values;

determining a second curve intersection point corresponding to the minimum cost function value from M sets of cost function values;

and determining the corresponding optimal second programming voltage according to the second curve intersection point corresponding to the minimum cost function value.

Optionally, the S7 specifically includes:

and iterating S2-S6 until the iteration number reaches an iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage are unchanged compared with the optimal first programming voltage and the optimal second programming voltage obtained in the previous iteration, and outputting the optimal first programming voltage and the optimal second programming voltage.

The present invention also provides a NAND flash dynamic write voltage apparatus, the write voltage including a first programming voltage and a second programming voltage, the apparatus comprising:

the construction module is used for constructing a cost function according to the high-order channel error rate, the low-order channel error rate and the minimum Hamming distance estimated by the LDPC code;

and the optimization module is used for carrying out convex optimization calculation on the cost function by taking the minimum function value of the cost function as an optimization target and the first programming voltage and the second programming voltage as independent variables, and outputting the optimal first programming voltage and the optimal second programming voltage.

Optionally, the optimization module comprises

The flash memory device comprises an acquisition module, a processing module and a control module, wherein the acquisition module is used for acquiring flash memory channel parameters, and the flash memory channel parameters comprise a first numerical value range of a first programming voltage and a second numerical value range of a second programming voltage;

the first selecting module is used for selecting one second programming voltage value from the second value range as an initial value of the second programming voltage;

the second selection module is used for uniformly selecting M first programming voltage values from the first value range, and forming M groups of first writing voltages by the M first programming voltage values and the initial value of the second programming voltage respectively, wherein M is a constant;

the first calculation module is used for calculating cost function values corresponding to the M groups of first write voltages and determining an optimal first programming voltage corresponding to the minimum cost function value;

the third selecting module is used for uniformly selecting M second programming voltage values from the second value range and forming M groups of second writing voltages by the M second programming voltage values and the optimal first programming voltage respectively;

the second calculation module is used for calculating cost function values corresponding to the M groups of second writing voltages and determining an optimal second programming voltage corresponding to the minimum cost function value;

a replacement module for replacing an initial value of the second programming voltage with an optimal second programming voltage;

and the circulating module is used for triggering the second selecting module, the first calculating module and the third selecting module, the second calculating module and the replacing module in sequence until a triggering termination condition is met, and outputting an optimal first programming voltage and an optimal second programming voltage.

Optionally, the flash channel parameters further include a maximum write voltage and a minimum write voltage, and the first calculation module specifically includes:

the first generation module is used for respectively generating M groups of first threshold voltage distribution graphs according to the M groups of first write voltages, the maximum write voltage and the minimum write voltage;

a first determining module for determining M groups of first curve intersections from the M groups of first threshold voltage distribution plots;

a first substituting module, configured to substitute M groups of the first curve intersections into a high-low channel error rate calculation formula, respectively, to obtain a high-low channel error rate, and substitute the high-low channel error rate into the cost function, to obtain M groups of the cost function values;

a second determining module, configured to determine, from M sets of cost function values, a first curve intersection corresponding to the minimum cost function value;

and the third determining module is used for determining the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

Optionally, the second calculating module specifically includes:

the second generating module is used for respectively generating M groups of second threshold voltage distribution graphs according to the M groups of second writing voltages, the maximum writing voltage and the minimum writing voltage;

a fourth determining module, configured to determine M groups of second curve intersections according to the M groups of second threshold voltage distribution graphs;

a second substituting module, configured to substitute the M groups of second curve intersections into a high-low channel error rate calculation formula, respectively, to obtain high-low channel error rates, and substitute the high-low channel error rates into the cost function, to obtain M groups of cost function values;

a fifth determining module, configured to determine, from M sets of cost function values, a second curve intersection corresponding to the minimum cost function value;

and the sixth determining module is used for determining the corresponding optimal second programming voltage according to the second curve intersection point corresponding to the minimum cost function value.

Optionally, the loop module is specifically configured to sequentially trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module until the iteration number reaches an iteration number threshold, or until the current optimal first programming voltage and the current optimal second programming voltage are both kept unchanged compared with the optimal first programming voltage and the optimal second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

According to the technical scheme, the invention has the following advantages:

the embodiment provides a NAND flash memory dynamic voltage writing method, a cost function is constructed according to a high-bit channel error rate, a low-bit channel error rate and a minimum Hamming distance estimated by an LDPC code, the effect of the LDPC code in data error correction is considered, different influences of the high-bit channel error rate and the low-bit channel error rate on an error rate are considered, the cost function is used for evaluating the high-bit channel error rate and the low-bit channel error rate corresponding to different first programming voltage and second programming voltage, so that the error rate is affected, the cost is large, the first programming voltage and the second programming voltage corresponding to the minimum cost are found, the minimum function value of the cost function is taken as an optimization target, the first programming voltage and the second programming voltage are arguments, convex optimization calculation is performed on the cost function, and the constructed cost function is a concave function, so that the optimal first programming voltage and the optimal second programming voltage can be obtained more quickly, the technical problem that when the code words are only stored in a high-order bit page or a low-order bit page, the total error rate performance is poor due to the fact that the channel error rates of the high-order bit page and the low-order bit page are unequal by the aid of an existing voltage writing method is solved, and the total error rate performance is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a flowchart of a dynamic voltage writing method for a NAND flash memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a conventional NAND flash memory;

FIG. 3 is a basic structure diagram of a conventional flash memory cell;

FIG. 4 is a schematic diagram of a threshold voltage distribution curve;

FIG. 5 is a schematic diagram of interference between adjacent cells in a parity bit line structure;

FIG. 6 is a diagram of a prior art NAND flash memory channel model;

FIG. 7 is a schematic diagram of a threshold voltage distribution curve;

FIG. 8 is a diagram of a threshold voltage distribution curve and a reference level;

FIG. 9 is a flowchart illustrating a dynamic voltage writing method for a NAND flash according to a second embodiment of the present invention;

FIG. 10 is a graph of simulation results provided by the present invention;

FIG. 11 is a schematic diagram of a NAND flash dynamic write voltage apparatus according to a third embodiment of the present invention.

Detailed Description

Referring to fig. 2, fig. 2 is a schematic structural diagram of a conventional NAND flash memory. NAND flash memory is made up of blocks, each block containing pages. As shown in fig. 2, a block in a NAND flash memory is composed of a plurality of word-lines (word-lines) and bit-lines (bit-lines), and a memory cell (cell) is located at an intersection of the word-lines and the bit-lines. Each wordline contains one or more pages of user data, which in current flash memory designs vary in length from 512 bytes to 8 kbytes. Typically 16 to 64 memory cells are included on each bit line. All bit lines in a block are connected to a source line (source line), which causes all memory cells in the block to be erased when an erase operation is performed. When writing data, only a high voltage needs to be applied to the corresponding word line, and then the bit line voltage at the corresponding position needs to be adjusted, so that the unit of operation for programming is a page. Each block is also provided with a page buffer area (page buffer) for facilitating data writing and reading.

The NAND flash memory can be classified into an odd/odd bit-line (even/odd bit-line) structure and an all-bit line (all-bit-line) structure according to the structure of a bit line. When the flash memory is in an odd-even bit line structure, the data written into the flash memory is written into the odd-even bit line structure after the data in the even unit. While all bit lines are written simultaneously. Even bit lines constitute an even page and odd bit lines constitute an odd page, and there is no such distinction in a full bit line architecture. Since the even and odd pages share the page buffer and peripheral circuitry, the parity bit line architecture requires less hardware than the full bit line architecture, which causes less inter-cell interference than the parity bit line architecture.

Referring to fig. 3, fig. 3 is a basic structure diagram of a conventional flash memory cell, in which a Floating Gate (FG) is added to an original triode transistor, mainly to retain electrons therein. The flash memory cell also includes several other parts: a Control Gate (CG), a Source (S) and a Drain (Drain, D). The number of bits that can be represented according to the voltage in the flash memory cell can be mainly classified into: Single-Level-Cell (SLC) type, Multi-Level-Cell (MLC) type, and Triple-Level-Cell (TLC) type. In SLC type NAND flash memory, each cell can store 1 bit of data, while in MLC type NAND flash memory, each cell can store 2 bits of data.

Before data is written into the NAND flash memory, the whole data needs to be erased, and the erasing operation only needs to apply high voltage on the substrate layer so that electrons in the floating gate flow into the substrate layer. When writing data, a high voltage is applied to the control gate to transfer electrons from the substrate layer to the floating gate. After the NAND flash memory unit writes data, the voltage distribution in the unit is approximately Gaussian distribution. The voltage exhibited by the flash cell after the injection of electrons is called the threshold voltage. Taking MLC type NAND flash as an example, under Gray mapping, a flash memory cell can be configured with four different levels, respectively V _min 、V ₁ 、V ₂ 、V _max They may represent data symbols "11", "10", "00", "01", respectively. Generally, bits on the left side of a symbol are called high order bits (MSB), and bits on the right side are called low order bits (LSB).

Before writing data into MLC flash memory unit, erasing operation is performed on the whole data to make the voltage in unit become the lowest voltage V _min Then by adjusting V ₁ 、V ₂ 、V _max The voltage value of (2) is used to write respective data into the flash memory cell. Thus, V _min Also called erase level (or minimum write voltage), V ₁ 、V ₂ 、V _max Called programming level (V) _max Also called maximum write voltage). Suppose setting V _min ＝1.4、V _max V obtained by MLC type NAND flash memory cell, 3.93 _min 、V ₁ 、V ₂ 、V _max The distribution curve of the threshold voltage can be shown in fig. 4, and there are four probability density curves in fig. 4, which are p in sequence from left to right _s11 (curve on which the first peak is located), p _s10 (curve on which the second peak is located), p _s00 (curve on which the third peak is located), p _s01 (the curve on which the fourth peak is located) corresponds to V _min 、V ₁ 、V ₂ 、V _max 。

The flash memory unit may generate various types of noise due to the threshold voltage fluctuation caused by the data erasure frequency, erasure time, and the change of the number of electrons in the flash memory unit, and the like, and the noise may affect the error code performance of the flash memory unit. The noise types include programming noise, random telegraph noise, data retention noise, and intercell interference. The detailed description is as follows:

(1) programming noise

The erase level and the program level are different in noise during programming, mainly in that the variance of the program noise is different. The distribution of the programming noise can be represented by a gaussian distribution:

where i ∈ {11,10,00,01}, respectively represent the erased state and 3 programmed states in the MLC flash memory, i ∈ 11 represents the erased state, and the rest represent other programming levels. In actual data writing, the idea of reaching the programming voltage in the flash memory cell is achieved by using an incremental step pulse program, which is based on the principle of adding a certain number of electrons to the cell each time, and then determining whether the voltage in the cell has reached the desired threshold voltage, and then repeating this process until the voltage value in the cell is greater than or equal to the threshold voltage. However, this will prevent the threshold voltage from reaching the correct voltage value and will generate a uniformly distributed noise, which is expressed as:

where vpp is the magnitude of the voltage that increases each time a step pulse is used. The erase state noise is not affected by this disturbance, while the program noise distribution of the program state needs to be convolved with the uniform distribution and the gaussian distribution. Thus, the programming noise expression for a programmed state is as follows:

wherein

Respectively corresponding to the programming voltages V ₁ 、V ₂ 、V _max 。

(2) Random telegraph noise

Random telegraph noise is a non-stationary noise component that is related to the number of erasures of the flash memory. The increase in erase times results in fluctuations in the threshold voltage within the cell, which is known as random telegraphic noise. The probability density distribution of random telegraph noise can be represented by a gaussian function:

wherein sigma _t Is a variance that is approximately proportional to the number of erasures.

(3) Data retention noise

The data retention noise is also a non-fixed noise component, and is related to the erase time of the flash memory, and is related to the data retention time. The probability density distribution of the data retention noise can be represented by a gaussian distribution:

wherein,

and

the mean and variance of the gaussian distribution, respectively, are both power-law related to the number of erasures and logarithmic to the data retention time. Can be expressed as:

wherein, PE (program and erase) is the number of times of erasing and writing data in the flash memory block, T is the data retention time of the flash memory, x ₀ 1.4 is the write voltage in the erased state, V _s Is the voltage value written into the flash memory cell. A. the _t 、B _t 、α ₁ 、α ₀ Is a constant.

(4) Inter-unit interference

In flash memory, a change in the threshold voltage of one cell has an effect on the threshold voltage of an adjacent cell, which is intercell interference. With the development of the manufacturing process, the size of the chip is smaller and smaller, the inter-cell interference is more and more serious, and the reliability of the data of the NAND flash memory is most affected. The intercell interference may be expressed as:

wherein, is Δ V _t ^(k) Refers to the threshold induced after the disturb cell is programmed to the kth stateThe value voltage changes by a value, γ refers to a coupling coefficient. The inter-cell interference is also related to the structure of the bit line of the NAND flash memory, and as can be seen from the above, the word line structure can be divided into a parity bit line structure and an all bit line structure. In the odd-even bit line structure, for the same word line, the cells on the even bit line are programmed first, and the cells on the odd bit line are programmed later, so that the flash memory cells on the even bit line are interfered by 5 adjacent flash memory cells, and the cells on the odd bit line are interfered by 3 adjacent flash memory cells, as shown in fig. 5. In the all-bit line structure, all flash memory cells on the same word line are programmed simultaneously, so that one cell of the all-bit line structure is affected by 3 adjacent cells, and thus it can be seen that the all-bit line structure has less inter-cell interference than the odd-even bit line structure.

According to the analysis, the threshold voltage obtained inside the flash memory unit is influenced by various noises after the flash memory unit writes data, so that the error code performance of the flash memory unit is influenced. In practical applications, data is encoded into codewords and then written into flash memory cells. Later, when one wants to read out these data, one needs to recover them from the code words using decoding. And obtaining the error rate according to the data error rate after decoding to determine the error performance of the flash memory unit. In order to reduce the error rate as much as possible, in the prior art, the write voltage is designed by establishing a minimum channel error rate. The channel error rate refers to the error rate of a code word before decoding, and the bit error rate refers to the bit error rate obtained after decoding the code word.

As shown in fig. 6, in the existing NAND flash memory channel model, after being erased and programmed, a flash memory cell is affected by random telegraph noise, inter-cell interference, and data retention noise, and after being affected by the inter-cell interference, the influence caused by the inter-cell interference is cancelled by a post-compensation technique, so as to output a final threshold voltage distribution condition. In practical applications, when there is no noise at all, the threshold voltage distribution is an equipotent distribution with only four values because there are only four voltages (minimum write voltage, maximum write voltage, program voltage) written (the even distribution caused by the incremental step pulse program is also considered as an equipotent distributionOne of the noises) and then subjected to various noises, i.e., by convolving the above-mentioned pre-constructed equi-probability distribution with various noises, a final threshold voltage distribution is obtained, which is represented by four probability density function curves, the function variables of which are expressed as

Respectively corresponding to the write voltages V _min 、V ₁ 、V ₂ 、V _max Then, the intersection R of the adjacent curves is calculated by the formula (1.8) ₁ 、R ₂ And R ₃ In particular R ₁ Is the minimum write voltage V _min The probability density curve and the first programming voltage V ₁ Of the probability density curve of (1), R ₂ Is a first programming voltage V ₁ The probability density curve and the second programming voltage V ₂ Of the probability density curve of (1), R ₃ Is the probability density curve of the second programming voltage and the maximum writing voltage V _max The intersection of the probability density curves.

Then, based on the obtained R ₁ 、R ₂ And R ₃ Making hard decision, and calculating the total channel error rate P at this time by formula (1.9) _e 。

Setting a parameter σ of threshold voltage distribution in an erase state _e And σ _p 0.35 and 0.05, respectively, an incremental programming step voltage vpp of 0.3, a decision voltage of 2.38, 3.0, 3.93, respectively, a number of PE cycles of 6000, and a retention time T of 40000 hours. For random telegraph noise, let σ _t Equal to 0.00025(PE) ^0.62 . For intercell interference, set γ _xy 、γ _y 0.006s and 0.08s, respectively, where s denotes the coupling strength factor between the units, set to 0.75, anAn all bit line structure is adopted. For data retention noise, parameter A is set _t ＝0.000055、B _t ＝0.000235、α ₁ ＝0.62、α ₀ The threshold voltage distribution obtained at 0.32 is shown in fig. 7, in which the distribution of the threshold voltage level and the reference voltage level according to the slave and flash memories is shown in fig. 8. In FIG. 7, there are four probability density curves, in left-to-right order, that are

Respectively correspond to V _min 、V ₁ 、V ₂ 、V _max 。

In practical application, the minimum write voltage V of the flash memory _min And a maximum write voltage V _max Is fixed, therefore, the prior art is to look for V ₁ And V ₂ Minimizing the current channel error rate can be expressed as:

the prior art is to use a gradient descent method to find the V to be found ₁ ^* And V ₂ ^* . When the parameter variation is relatively large, for example, when PE changes from 5000 to 10000, V can be calculated again to minimize the channel error rate at this time ₁ ^* And V ₂ ^* And dynamically designing the write voltage.

The current data storage basically uses an error correction code technology to obtain further data protection capability, the main flow is to add some redundancies to an information sequence, the information sequence and the redundancies form a code word, and when the information sequence is to be recovered, the code word can be obtained by decoding the code word. However, for the existing write voltage design scheme with the minimum channel error rate, when the code words are stored on the flash memory units in sequence of high-order bits, low-order bits and high-order bits, a better storage effect can be achieved. However, when the codeword is stored only in the upper bit page or the lower bit page, since the channel error rates of the upper and lower bits are not equal, the continued use of the scheme may cause the barrel effect, and the overall error rate performance may be degraded.

In view of the above, embodiments of the present invention provide a method and apparatus for dynamic write voltage of a NAND flash memory, which are used to improve the overall bit error rate performance of the NAND flash memory.

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for writing voltages to a NAND flash memory according to an embodiment of the invention, where the writing voltages include a first programming voltage V ₁ And a second programming voltage V ₂ The specific method comprises the following steps:

step 101, constructing a cost function according to the error rate of a high-order channel, the error rate of a low-order channel and the minimum Hamming distance estimated by the LDPC code;

it should be noted that, on the MLC-type NAND flash memory, the channel error rates of the high-order bits and the low-order bits have different effects on the total error rate of the flash memory cell, and when data storage is performed, error correction is performed by using an error correction code to reduce the error rate, and because of the participation of the error correction code, the error rate is always lower than the channel error rate, so that the effect of the error correction code is considered, and a cost function is constructed on the basis of combining the error correction code in this embodiment. The channel error rate of high and low bits corresponding to different first programming voltages and second programming voltages is evaluated through the cost function, and the caused error rate influence is evaluated. The first and second programming voltages that minimize (i.e., have minimal impact on) the cost function value are then found as the optimal write voltages. The error correction code according to the present embodiment is an LDPC code.

The calculation formula of the high bit channel error rate and the low bit channel error rate is shown as formula (2.1).

Wherein, ω is _msb At high bit channel error rates, omega _lsb A low bit channel error rate. R is ₁ Is the minimum write voltage V _min The probability density curve and the first programming voltage V ₁ Of the probability density curve of (1), R ₂ Is a first programming voltage V ₁ The probability density curve and the second programming voltage V ₂ Of the probability density curve of (1), R ₃ Is the probability density curve of the second programming voltage and the maximum writing voltage V _max The intersection of the probability density curves of (a).

Respectively, is the minimum write voltage V _min Probability density curve, first programming voltage V ₁ Probability density curve, second programming voltage V ₂ Probability density curve of (1), maximum write voltage V _max Probability density curve of (1).

It can be understood that the probability density curve

The construction method of (2) can be referred to in the prior art, and the rest parameters required in the curve construction process can be set by referring to the related contents in the prior art. The cost function provided by the embodiment is suitable for probability density curves constructed by various different parameters.

The cost function constructed from the high bit channel error rate, the low bit channel error rate and the minimum hamming distance estimated by the LDPC code is as follows:

where d is the minimum hamming distance estimated by the LDPC code.

And 102, performing convex optimization calculation on the cost function by taking the minimum function value of the cost function as an optimization target and the first programming voltage and the second programming voltage as independent variables, and outputting the optimal first programming voltage and the optimal second programming voltage.

It should be noted that, through multiple experimental verifications, it is known that the cost function constructed in this embodiment is a concave function, and convex optimization calculation can be performed according to parameters of the first programming voltage and the second programming voltage, so as to quickly find the optimal first programming voltage and the optimal second programming voltage, where a convex optimization formula is as follows:

wherein, V ₁ ^* ,V ₂ ^* Respectively, an optimal first programming voltage and an optimal second programming voltage.

Referring to fig. 9, fig. 9 is a schematic flow chart of a NAND flash dynamic voltage writing method according to a second embodiment of the present invention, the method includes:

201. and constructing a cost function according to the high-order channel error rate, the low-order channel error rate and the minimum Hamming distance estimated by the LDPC code.

It should be noted that step 201 may refer to step 101, and is not described herein again.

202. And acquiring flash memory channel parameters, wherein the flash memory channel parameters comprise a first numerical range of the first programming voltage, a second numerical range of the second programming voltage, a maximum writing voltage and a minimum writing voltage.

It should be noted that the flash channel parameters refer to parameters required for constructing the threshold voltage distribution. The threshold distribution parameter sigma in the erase state is included in addition to the first value range of the first programming voltage, the second value range of the second programming voltage, the maximum write voltage and the minimum write voltage _e And σ _p Incremental programming step voltage vpp, cycle number PE, retention time T, parameter σ for random wave noise use _t Parameter gamma used for intercell interference _xy 、γ _y Coupling strength factor s, parameter A used for data retention noise _t 、B _t 、α ₁ 、α ₀ And so on. The specific values of these parameters can be set in advance according to different types of flash memory cells. The maximum write voltage and the minimum write voltage are both preset fixed values.

As an example, let us say the parameter σ of the threshold voltage distribution in the erased state _e And σ _p 0.35 and 0.05, respectively, and an incremental programming step voltage vpp of 0.3; minimum write voltage V _min And a maximum write voltage V _max 1.4 and 3.93, respectively, V of the first programming voltage ₁ Has a first numerical value range of [2,2.6]]Second programming voltage V ₂ Is set to (2.6, 3.3)]The experiment is simulated under different PE cycle times, the retention time T is 0, and sigma is set for random telegraph noise _t Is equal to0.00025(PE) ^0.62 . For intercell interference, γ is set _xy 、γ _y 0.006s and 0.08s, respectively, where s refers to the coupling strength factor between cells and is set to 0.75, and the flash memory cells adopt an all bit line architecture. For data retention noise, parameter A is set _t ＝0.000055、B _t ＝0.000235、α ₁ ＝0.62、α ₀ ＝0.32。

203. A second programming voltage value is selected from the second range of values as an initial value of the second programming voltage.

It should be noted that, a value is arbitrarily selected from the second value range as the initial value of the second programming voltage, and as an example, the initial value of the second programming voltage is 3.3.

204. And uniformly selecting M first programming voltage values from the first value range, and combining the M first programming voltage values and the initial value of the second programming voltage into M groups of first writing voltages respectively, wherein M is a constant.

It should be noted that, as an example, M first programming voltage values may be uniformly selected from the first range of values [2,2.6], where M may be determined according to actual needs.

The M first programming voltage values and the second programming voltage initial value are respectively combined into M groups of first writing voltages, namely the first writing voltages comprise the first programming voltages and the second programming voltage initial value, and the M groups of first writing voltages can be combined because of the M first programming voltages.

205. And calculating cost function values corresponding to the M groups of first writing voltages, and determining the optimal first programming voltage corresponding to the minimum cost function value.

It should be noted that step 205 specifically includes the following sub-steps:

s21: and respectively generating M groups of first threshold voltage distribution graphs according to the M groups of first write voltages, the maximum write voltage and the minimum write voltage.

In addition, since the minimum value of the cost function is calculated by using the probability density curve of each voltage, after the M groups of first write voltages are obtained, the first threshold voltage distribution graph is generated according to each group of the first write voltages, the maximum write voltage, and the minimum write voltage.

After determining the values of the first programming voltage, the second programming voltage, the maximum writing voltage and the minimum writing voltage, a corresponding threshold voltage distribution graph similar to that shown in fig. 8 can be generated, and the generation method can refer to the prior art.

S22: determining M groups of first curve intersection points according to M groups of first threshold voltage distribution graphs;

it should be noted that, in each threshold voltage distribution graph, a minimum write voltage curve, a first program voltage curve, a second program voltage curve, and a maximum write voltage curve are distributed, and based on this, curve intersections of adjacent curves, that is, R, can be determined in the threshold voltage distribution graph ₁ 、R ₂ And R ₃ 。

With M sets of threshold voltage distribution graphs, M sets of first curve intersections can be correspondingly identified.

S23: and substituting the M groups of first curve cross points into a high-low channel error rate calculation formula respectively to obtain high-low channel error rates, and substituting the high-low channel error rates into a cost function to obtain M groups of cost function values.

S24: and determining a first curve intersection point corresponding to the minimum cost function value from the M sets of cost function values.

S25: and determining the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

In addition, M groups R will be obtained ₁ 、R ₂ And R ₃ The values are respectively substituted into a high-order channel error rate calculation formula (2.1) and a low-order channel error rate are obtained, and the obtained high-order channel error rate and the obtained low-order channel error rate are substituted into a cost function formula (2.2) to obtain M groups of cost function values. Finding out the cross point corresponding to the minimum cost function value from the M sets of cost function values, determining the corresponding first writing voltage based on the set of cross points, and obtaining the first writing voltage at the timeThe initial values of the optimal first and second programming voltages are set, and thus, the optimal first programming voltage can be determined.

206. And uniformly selecting M second programming voltage values from the second value range, and combining the M second programming voltage values with the optimal first programming voltage to form M groups of second writing voltages respectively.

It should be noted that the second write voltages include the second programming voltage and the optimal first programming voltage, and since there are M second programming voltages, there are M groups of corresponding second write voltages.

207. And calculating cost function values corresponding to the M groups of second writing voltages, and determining the optimal second programming voltage corresponding to the minimum cost function value.

It should be noted that the principle of determining the optimal second programming voltage is similar to that of determining the optimal first programming voltage, and refer to step 205. Step 207 specifically comprises the following substeps:

s31: respectively generating M groups of second threshold voltage distribution graphs according to the M groups of second write voltages, the maximum write voltage and the minimum write voltage;

according to the second write voltage, the maximum write voltage and the minimum write voltage, corresponding second threshold voltage distribution graphs can be generated, and due to the fact that M groups of second write voltages exist, M groups of second threshold voltage distribution graphs can be correspondingly generated.

S32: determining M groups of second curve intersections according to the M groups of second threshold voltage distribution graphs;

each threshold voltage distribution graph is distributed with a minimum write voltage curve, a first programming voltage curve, a second programming voltage curve and a maximum write voltage curve, and based on the minimum write voltage curve, a curve intersection point of adjacent curves, namely R, can be determined in the threshold voltage distribution graphs ₁ 、R ₂ And R ₃ 。

S33: respectively substituting the M groups of second curve cross points into a high-low channel error rate calculation formula to obtain high-low channel error rates, and substituting the high-low channel error rates into a cost function to obtain M groups of cost function values;

s34: determining a second curve intersection point corresponding to the minimum cost function value from the M sets of cost function values;

s35: and determining the corresponding optimal second programming voltage according to the second curve intersection point corresponding to the minimum cost function value.

In addition, M groups R will be obtained ₁ 、R ₂ And R ₃ The values are respectively substituted into a high-order channel error rate calculation formula (2.1) and a low-order channel error rate are obtained, and the obtained high-order channel error rate and the obtained low-order channel error rate are substituted into a cost function formula (2.2) to obtain M groups of cost function values. And finding out the intersection point corresponding to the minimum cost function value from the M sets of cost function values, and determining the corresponding second writing voltage based on the set of intersection points, wherein the obtained second writing voltage is the optimal first programming voltage and the optimal second programming voltage, so that the optimal second programming voltage can be determined.

208. The optimum second programming voltage is substituted for the initial value of the second programming voltage.

It should be noted that, in the next iteration, the initial value of the second programming voltage is replaced by the optimal second programming voltage, the optimal second programming voltage and M first programming voltage values are used to form M groups in step 203, and the obtained first writing voltage in S25 of step 205 is the optimal first programming voltage and the optimal second programming voltage.

209. And iterating step 203-.

It should be noted that, the step 203-.

To further illustrate the technical effects achieved by the present embodiment, the following analysis will be performed based on the data obtained by the simulation test.

Referring to fig. 10, fig. 10 shows bit error rate performance simulation results provided by the embodiment of the invention.

The experimental simulation is carried out under a Window10 operating system, matlab software is utilized to carry out a bit error rate simulation experiment, an original pattern LDPC code with a code rate of 0.89 is selected in the experiment, a simulation result graph can refer to FIG. 10, and the specific parameter settings of the simulation are as follows:

setting a parameter σ of threshold voltage distribution in an erase state _e And σ _p 0.35 and 0.05, respectively, and an incremental programming step voltage vpp of 0.3; minimum write voltage V _min And a maximum write voltage V _max 1.4 and 3.93, respectively, V of the first programming voltage ₁ Is [2,2.6]]Second programming voltage V ₂ Is set to (2.6, 3.3)]The experiment is simulated under different PE cycle times, the retention time T is 0, and sigma is set for random telegraph noise _t Equal to 0.00025(PE) ^0.62 . For intercell interference, γ is set _xy 、γ _y 0.006s and 0.08s, respectively, where s refers to the coupling strength factor between the cells, is set to 0.75, and adopts an all bit line architecture. For data retention noise, parameter A is set _t ＝0.000055、B _t ＝0.000235、α ₁ ＝0.62、α ₀ ＝0.32。

As can be seen from fig. 10, the bit error rate performance of the NAND flash dynamic write voltage method provided by the embodiment of the present invention is better than that of the fixed write voltage scheme and the write voltage scheme constructed by the existing minimum channel error rate under the same program/erase times. Therefore, the technical scheme provided by the embodiment of the invention considers the problem of imbalance of high and low bit channel error rates, and remarkably improves the total error rate performance by combining the action of the LDPC code in data error correction.

Referring to fig. 11, fig. 11 is a block diagram illustrating a NAND flash dynamic write voltage apparatus according to a third embodiment of the present invention, wherein the apparatus includes:

a constructing module 301, configured to construct a cost function according to the high-order channel error rate, the low-order channel error rate, and the minimum hamming distance estimated by the LDPC code;

the optimization module 302 performs convex optimization calculation on the cost function by taking the minimum function value of the cost function as an optimization target and the first programming voltage and the second programming voltage as arguments, and outputs the optimal first programming voltage and the optimal second programming voltage.

Further, the optimization module 302 includes:

the flash memory device comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring flash memory channel parameters, and the flash memory channel parameters comprise a first numerical value range of a first programming voltage and a second numerical value range of a second programming voltage;

the first selection module is used for selecting a second programming voltage value from a second value range as an initial value of the second programming voltage;

the first calculation module is used for calculating cost function values corresponding to the M groups of first writing voltages and determining the optimal first programming voltage corresponding to the minimum cost function value;

the second calculation module is used for calculating cost function values corresponding to the M groups of second write voltages and determining an optimal second programming voltage corresponding to the minimum cost function value;

a replacing module for replacing the initial value of the second programming voltage with the optimal second programming voltage;

and the circulating module is used for sequentially triggering the second selecting module, the first calculating module, the third selecting module, the second calculating module and the replacing module until a triggering termination condition is met and outputting the optimal first programming voltage and the optimal second programming voltage.

Further, the flash memory channel parameters further include a maximum write voltage and a minimum write voltage, and the first calculation module specifically includes:

a first determining module for determining M groups of first curve intersections from the M groups of first threshold voltage distribution graphs;

the first substituting module is used for substituting the M groups of first curve cross points into a high-low channel error rate calculation formula respectively to obtain high-low channel error rates, and substituting the high-low channel error rates into a cost function to obtain M groups of cost function values;

the second determining module is used for determining a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

Further, the second calculation module specifically includes:

the second generation module is used for respectively generating M groups of second threshold voltage distribution graphs according to the M groups of second write voltages, the maximum write voltage and the minimum write voltage;

a fourth determining module, configured to determine M groups of second curve intersection points according to the M groups of second threshold voltage distribution graphs;

the second substituting module is used for substituting the M groups of second curve cross points into a high-low channel error rate calculation formula respectively to obtain high-low channel error rates, and substituting the high-low channel error rates into the cost function to obtain M groups of cost function values;

a fifth determining module, configured to determine, from the M sets of cost function values, a second curve intersection corresponding to a minimum cost function value;

Further, the loop module is specifically configured to sequentially trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module until the iteration number reaches an iteration number threshold, or until the current optimal first programming voltage and the current optimal second programming voltage are both kept unchanged compared with the optimal first programming voltage and the optimal second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A NAND flash dynamic write voltage method, wherein a write voltage comprises a first programming voltage and a second programming voltage, the method comprising:

2. The method of claim 1, wherein the optimizing target is a minimum function value of a cost function, the first programming voltage and the second programming voltage are independent variables, and performing a convex optimization calculation on the cost function to output an optimal first programming voltage and an optimal second programming voltage comprises:

3. The method according to claim 2, wherein the flash channel parameters further include a maximum write voltage and a minimum write voltage, and the S3 specifically includes:

determining a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

4. The method according to claim 3, wherein the S5 specifically comprises:

respectively substituting the M groups of second curve cross points into a high-low channel error rate calculation formula to obtain high-low channel error rates, and substituting the high-low channel error rates into the cost function to obtain M groups of cost function values;

5. The method according to claim 2, wherein the S7 specifically includes:

6. A NAND flash dynamic write voltage apparatus, wherein a write voltage comprises a first programming voltage and a second programming voltage, the apparatus comprising:

7. The apparatus of claim 6, wherein the optimization module comprises

8. The apparatus of claim 7, wherein the flash channel parameters further include a maximum write voltage and a minimum write voltage, and the first computing module specifically includes:

9. The apparatus of claim 8, wherein the second computing module specifically comprises:

10. The apparatus according to claim 7, wherein the loop module is specifically configured to sequentially trigger the second selection module, the first calculation module, the third selection module, the second calculation module, and the replacement module until an iteration count reaches an iteration count threshold, or until the current optimal first programming voltage and the current optimal second programming voltage are unchanged from the optimal first programming voltage and the optimal second programming voltage obtained in a previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.