CN115033090A

CN115033090A - Power supply management method, equipment and storage medium

Info

Publication number: CN115033090A
Application number: CN202210469974.9A
Authority: CN
Inventors: 钱凯
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2022-04-30
Filing date: 2022-04-30
Publication date: 2022-09-09

Abstract

The present specification provides a method, an apparatus, and a storage medium for managing power, the method including: and determining a corresponding power-on section according to a power module in the equipment, sequentially powering on the power module in each power-on section according to a power-on sequence, and determining that the equipment is powered on successfully after receiving a power-on success signal fed back by each power-on section. By the method, the device power-on \ power-off management can be realized.

Description

Power supply management method, equipment and storage medium

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a method, a device, and a storage medium for managing a power supply.

Background

The core router hardware system has more single boards, most of the power supply time sequence management of the onboard chip is more complex, for example, the INTEL X86 series CPU is taken as an example, the types of power supply sources are dozens, and the power-on and power-off sequence and time interval of each power supply are strictly quantized. A single-board hardware designer must strictly manage and control the power timing requirements of a chip, otherwise, a hardware system may cause catastrophic consequences due to improper power timing management, such as system probabilistic non-startup, kernel probabilistic hang-up, and the like.

Disclosure of Invention

The present disclosure provides a power management method, device, and storage medium, by which sequential power-up and power-down of power modules in a device can be achieved.

The embodiment of the disclosure provides a power supply management method, which includes:

determining a corresponding power-on section according to a power module in the equipment;

sequentially electrifying the power modules in each electrifying section according to the electrifying sequence;

and after receiving the power-on success signals fed back by each power-on section, determining that the equipment is powered on successfully.

Wherein, said power module in every power up section is electrified in order according to the time sequence of electrifying, including:

and setting a timer, and sequentially electrifying the power supply modules in each electrifying section according to electrifying signals sent by the timer at each electrifying preset time point.

Wherein, the setting of the timer, and the powering up of the power modules in each powering up section in sequence according to the powering up signal sent by the timer at each powering up preset time point, includes:

setting a timer through a microcontroller, and setting each power-on preset time point for the timer;

and when the time of the timer reaches a preset power-on time point, indicating the microcontroller to send a power-on signal to the power module in the corresponding power-on section.

The embodiment also provides the following method:

acquiring a device power-off signal;

powering down the powered-up sections in sequence according to the power-down time sequence;

and after receiving the power-off success signals fed back by each power-on section, determining that the power-off of the equipment is successful.

The embodiment also provides the following method:

monitoring the power state of each power-on section;

when monitoring that the power state of the power-on section is abnormal, powering down the powered-on section according to the power-down sequence;

Wherein, said powering down the powered up sections in sequence according to the powering down sequence comprises:

setting a timer through a microcontroller, and setting each power-off preset time point for the timer;

and when the time of the timer reaches a power-off preset time point, indicating the microcontroller to send a power-off signal to the power supply module in the corresponding power-off section.

An embodiment of the present disclosure further provides an apparatus, including: a memory, a processor and a program stored on the memory and executable on the processor, the program implementing any of the above method steps when executed by the processor.

Embodiments of the present disclosure also provide a computer-readable storage medium, on which a program is stored, where the program, when executed by a processor, implements any of the above-mentioned method steps.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a schematic flow chart of a power management method according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the claims that follow.

The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if," as used herein, may be interpreted as "at … …" or "when … …" or "in response to a determination," depending on the context.

The current power management system (exemplified by my X86 router) can implement power management based on CPLD, and can include two aspects as follows, (1) power-on management of X86 router: the POWER supply which is powered on firstly outputs a POWER GOOD signal to indicate that the POWER supply is powered on and OK at present, meanwhile, the POWER GOOD signal can be used as an enabling POWER EN signal for powering on the next POWER supply, the POWER EN signal enables the next POWER supply to be powered on, the time interval from the POWER GOOD of the previous POWER supply to the POWER EN for powering on the next POWER supply is set based on the POWER-on time interval required by a chip manual, and the chip is ensured to be powered on sequentially according to the manual requirement (2) the recording of the POWER supply state: the POWER GOOD signal is used as an indication of the POWER supply state and is transmitted to a pin of the CPLD in a transparent mode, the CPLD senses the jumping of the POWER GOOD signal of each POWER supply to record whether each POWER supply is normal or not, once the POWER GOOD signal jumps, the value of an internal register of the CPLD changes accordingly, and the upper computer senses the state of each POWER supply through polling the CPLD register.

In practical application, the input voltage-54V of the whole board primary direct-current power supply of the X86 router is converted into 12V direct-current stabilized voltage through a DC-DC isolation type power supply brick, the 12V is used as the input voltage of an on-board secondary power supply (BUCK/LDO), and power is supplied to each chip in the board after conversion.

Meanwhile, a POWER _ CPLD and ADM1166 are used as the core of POWER management of the whole board in the board, a main control board MPU is used as the POWER management main equipment of the line card service board, and the PTX/PRX universal serial bus and the POWER _ CPLD are used for communication to manage the POWER on and off of the line card service board and obtain the POWER state in the line card board: (1) and (3) power on and power off management: the MPU sends a POWER ON POWER-ON command to the POWER _ CPLD through the PTX/PRX bus, the POWER _ CPLD outputs a high level of 12V _ POWER to the ADM1166 in the BOARD after receiving the command, the ADM1166 starts a state machine for POWER management in the BOARD, sequentially enables POWER-ON actions of secondary POWER supplies (BUCK/LDO) in the BOARD according to the specifications of a POWER receiving chip, and when the ADM1166 monitors that all key POWER supplies in the BOARD are powered ON OK, the ADM1166 sends a BOARD _ PWR _ GOOD signal to the POWER _ CPLD to inform the MPU of a main control BOARD line card service BOARD of the POWER-ON OK.

The number of power sources related to the INTEL _ X86 serial CPUs is as large as tens of power sources, the requirement on power-on time sequence is complex, the number of power-on enable signals output by the ADM1166 is limited, the flexibility is not high, and the power-on enable signals are not suitable for outputting single-path power-on enable EN signals of the X86 router to control the power-on of the X86_ CPU. The power supply of the X86 router is typically managed through a single SYS _ CPLD.

When the MPU main control board sends a POWER-ON command to the line card service board, the ADM1166 in the board simultaneously sends an X86_ PWR _ EN high level to the SYS _ CPLD as a starting signal for powering ON the CPU, the CPLD sequentially controls the powering ON of the CPU _ PWR _0 to the CPU _ PWR _ n according to the POWER-ON sequence requirement of the CPU, and a PG (Power GOOD POWER-ON OK) signal of a POWER supply which is powered ON first (after delay time is carried out according to the CPU specification requirement) is used as an EN POWER-ON enabling signal of a POWER supply which is powered ON later until the POWER-ON of all the POWER supplies of the CPU is completed. Wherein, X86_ BIOS _ PWR _ EN is an enable signal in a special application scenario (for example, the CPU needs to be powered off and powered on again in the process of switching between the main and standby BIOS of the CPU), and is usually at a high level, the CPU issues the signal through the parallel Local _ bus management of the SYS _ CPLD, and the signal and X86_ PWR _ EN trigger the power on or power off of the CPU together. When the CPU has a power-down requirement, X86_ PWR _ EN or X86_ BIOS _ PWR _ EN is pulled down, and then CPU _ PWR _ EN _0 to n are sequentially pulled down to realize the power-down of the CPU.

When the CPU is powered on and OK, and the X86_ POWER _ GOOD is in high level, monitoring of the POWER supply on the X86 by the other one or more ADMs 1166 in the board is enabled, and once abnormal POWER failure or overvoltage occurs, an internal black box is recorded, and POWER supply abnormal record of the X86_ CPU is recorded.

In the scheme, the X86_ CPU can be sequentially powered on and normally started according to the specification requirements, but the power-off management of the CPU is under-specified by the method, and the power-off management sequence of the CPU is not usually met.

Moreover, the CPU power-off and power-on situations caused by abnormal situations such as single board pulling-out or power grid fluctuation tripping, or independent power-off and power-on situations of the CPU in other special application scenarios (for example, the CPU needs to be powered off and powered on again in the active and standby BIOS switching process of the CPU): under these scenes, the CPU can not be orderly powered off according to the sequence required by the specification, and the power-off state management has defects.

In order to solve the above technical problem, an embodiment of the present disclosure provides a method for managing a power supply, as shown in fig. 1, the method includes:

s101, determining a corresponding power-on section according to a power module in the equipment;

s102, sequentially electrifying the power modules in each electrifying section according to the electrifying time sequence;

s103, after receiving the power-on success signal fed back by each power-on section, determining that the equipment is powered on successfully.

In this embodiment, the device may be a device with multiple power supply modules, such as a router, a switch, an optical/point transmission device, a wireless base station, and the like.

In step S101, the administrator may determine a corresponding power-on section according to a power module in the device, for example, the motherboard, the hard disk, the memory, and the external interface may be divided into 4 power-on sections (it should be noted that the determination of the power-on section may be set according to the requirement of the user).

Generally, the process of powering on the device may be divided into the following typical stages, where each stage has a part of power supply powered on, and when the power on is completed in each stage, the power on of the CPU is OK:

(1) g3 state: the system is shut down and the mainboard is not powered

(2) State S5: system shutdown, mainboard power supply

(3) State S4: the system is shut down, the hard disk is suspended and electrified (intermediate standby state)

(4) State S3: suspend to memory (middle standby state)

(5) State S0: boot state

In each state, different power supplies of the CPU are sequentially powered on based on specification requirements (for example, a mainboard- > a hard disk- > a memory).

In step S102, in order to control the sequential power-on of the power modules in each power-on section, in this solution, a microcontroller, such as a CPLD (Complex Programmable logic device), or an MCU FPGA, having a control output may be used to set a timer, and a plurality of (one or more) power-on preset time points are set for the timer, where each preset power-on time point may correspond to a power module in one power-on region.

When receiving a POWER-on signal of the device, the CPLD starts to start the timer, and when the timer runs to a first POWER-on preset time point, the CPLD sends a POWER-on signal (POWER EN signal) to a corresponding POWER-on area.

Therefore, in the embodiment, the CPLD can be triggered by the timer to send the power-on signal to each power module without sending the power-on signal from the last powered power module to the next unpowered power module, so that the power-on efficiency of the device can be effectively improved.

In this embodiment, the CPLD may respectively represent different stages of the device power-on or power-off process by binary codes "001", "010" and "100", for example, each state and jump of the state are described as follows:

g3- > G3: unfinished power-on of CPU related power supply in G3 state

G3- > S5: the power supply related to the CPU in the G3 state is completely powered on, and the power supply related to the second stage of the CPU is powered on when the power supply related to the CPU in the G3 state is switched to the S5 state

S5- > S0: the power-on of the related power supply of the second stage of the CPU in the S5 state is completed, the power-on of the related power supply of the CPU in the S0 state in the third stage is jumped to until all the power supplies of the CPU are powered on OK and finally are stabilized in the S0 state

Thus X86_ jump flow of power on state machine on CPU: g3- > S5- > S0.

For convenience of description of the present embodiment, the number of states includes three states G3, S5, and S0, and when power is actually managed, other numbers of states and nodes may be arranged according to user requirements.

In combination with the above-described scheme, in practical practice, a POWER _ Timer is arranged inside the CPLD and is used for calibrating the POWER-on preset time point of each stage of the CPU, the POWER-on PWR _ EN enable signal of the corresponding POWER supply is pulled up at the corresponding POWER-on preset time point, the POWER supplies are sequentially powered on according to the CPU specification requirements, after the POWER supply at the S5 stage is powered on OK, the CPU sends SLP _ S4_ N and SLP _ S3_ N high level signals to the CPLD, the POWER supply of each path of POWER supply at the S0 stage is started, after the CPU is completely powered on OK, the CPU sends a CPU _ PWR _ GOOD signal to the CPLD, and the calibration of the POWER supply of the CPU is completed.

The CPU POWER-off control is opposite to the POWER-on process, when a POWER-off event is triggered, the CPLD sends a PROCPWRGD _ PCH low level signal to the CPU, the CPU returns SLP _ S4_ N and SLP _ S3_ N signal levels of the CPLD to be pulled down, the CPLD pulls down POWER-on PWR _ EN enabling signals of a corresponding POWER supply at a corresponding POWER-off preset time point based on POWER _ Timer control, and the POWER is sequentially powered off according to the CPU specification requirements until the POWER-off of the CPU is finished.

According to the embodiments, the power-on/power-off of the equipment can be effectively managed, the CPLD + timer can be used for indicating the equipment to complete the power-on/power-off by a management role, and the power-on/power-off efficiency of the equipment is effectively improved.

In the embodiment of the present disclosure, the power down of the device may be divided into normal power down and abnormal power down, and in the prior art, there is no corresponding control over the power down process of the device, for example, a CPU power down caused by abnormal situations such as single board pulling out or power grid ripple tripping, or independent power down and power up situations of a CPU in other special application scenarios (for example, a CPU needs to actively power down and power up again in a CPU main and standby BIOS switching process): under the conditions, the CPU can not be orderly powered down according to the sequence required by the specification, and the power-down state management has defects.

Based on the scheme provided by the disclosure, when the CPLD obtains the power-off signal of the device, the timer is started, wherein the timer is provided with a power-off preset time point, the power-off preset time point is the same as the power-on preset time point, each power-off preset time point corresponds to a different power-on zone, when the timer runs to one power-off preset time point, the power-off signal is sent to the corresponding power-on zone, and when the CPLD receives the power-off success signal fed back by each power-on zone, the power-off success of the device is determined.

Meanwhile, in the embodiment, power supply monitoring can be performed on the powered-on section, when the power supply state of the powered-on section is monitored to be abnormal, the timer can be triggered actively, and the powered-on section is powered off orderly according to the power-off signal sent by the timer at the power-off preset time point, so that the condition that data is lost or damaged due to abnormal power-off of the equipment is prevented.

An embodiment of the present disclosure also provides a computer-readable storage medium, on which a program is stored, which when executed by a processor implements any of the above method steps.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.

It will be understood that the present description is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for managing power, the method comprising:

2. The method of claim 1, wherein said sequentially powering up power modules in respective power-up sections according to a power-up sequence comprises:

3. The method according to claim 2, wherein the setting a timer, and sequentially powering up the power modules in each power-up section according to the power-up signal sent by the timer at each power-up preset time point comprises:

4. The method of claim 1, further comprising:

acquiring a device power-off signal;

5. The method of claim 1, further comprising:

monitoring the power state of each power-on section;

6. The method of claim 4 or 5, wherein said sequentially powering down powered up sections according to a power down timing comprises:

and when the time of the timer reaches a power-off preset time point, indicating the microcontroller to send a power-off signal to the power module in the corresponding power-off section.

7. An apparatus, characterized in that the apparatus comprises: memory, processor and program stored on the memory and executable on the processor, which when executed by the processor implements the method steps of any of claims 1 to 5.

8. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a program which, when being executed by a processor, carries out the method steps of any one of claims 1 to 5.