CN115021827B - Phase angle locking method and system of coherent receiver - Google Patents
Phase angle locking method and system of coherent receiver Download PDFInfo
- Publication number
- CN115021827B CN115021827B CN202210533779.8A CN202210533779A CN115021827B CN 115021827 B CN115021827 B CN 115021827B CN 202210533779 A CN202210533779 A CN 202210533779A CN 115021827 B CN115021827 B CN 115021827B
- Authority
- CN
- China
- Prior art keywords
- driving voltage
- phase angle
- voltage
- calibration value
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6165—Estimation of the phase of the received optical signal, phase error estimation or phase error correction
Abstract
The invention discloses a phase angle locking method and a system of a coherent receiver, which relate to the field of high-speed optical communication systems, and the method comprises the following steps: acquiring an initial value of a driving voltage when phase angles are orthogonal; fine tuning the initial value of the driving voltage, and determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate; and adjusting the driving voltage in real time according to the calibration parameters and the driving voltage calibration value, so that the current phase angle acquired in real time is kept at the phase angle calibration value. The invention can be compatible with DSP chips and silicon optical devices of different manufacturers, and can accurately control the IQ phase angle of the coherent receiver at an orthogonal position.
Description
Technical Field
The invention relates to the field of high-speed optical communication systems, in particular to a phase angle locking method and a phase angle locking system of a coherent receiver.
Background
With the driving of services such as mobile internet, internet of things, cloud computing and big data, an optical transmission network serving as a loading infrastructure of various services needs to adapt to the new requirements. The coherent optical communication system can support optical signal transmission up to thousands of kilometers based on advanced modulation formats such as QPSK (Quadrature Phase Shift Keying ) or QAM (Quadrature Amplitude Modulation, quadrature amplitude modulation) and the like, is widely used for OTN (optical transport network )/PTN (Packet Transport Network, packet transport network) optical communication systems in backbone networks and metropolitan area networks, and can also be used for optical interconnection between data centers above 80 km.
The coherent receiver is an important component in a coherent optical communication system, and adopts a coherent detection mode, and the beat frequency of signal light and local oscillation light is detected by a detector. The performance of the coherent receiver directly affects transmission indexes such as transmission distance, error rate and the like of the system. On the one hand, the mixer IQ phase angle of a coherent receiver is not perfectly 90 ° due to device process errors. On the other hand, when a coherent receiver operates for a long time, some internal and external factors such as ambient temperature may drift the IQ phase angle of the mixer. Thus, the coherent optical module requires real-time detection and adjustment of the mixer IQ phase angle.
Silicon photofabrication is an abbreviation for silicon-based optoelectronic integration technology, i.e., the integration of photonic and optoelectronic components on top of a silicon substrate material. Other optoelectronic functions besides lasers, such as a coherent modulator, a coherent receiver and a polarization multiplexer, inside the coherent optical module can be realized by silicon optical monolithic integration. The mixer of the silicon optical coherent receiver generally adopts a thermo-optical effect, and the refractive index is changed by heating the silicon-based waveguide through a resistor, so that the phase difference of the mixer is changed. The relationship between the phase angle of the mixer IQ and the driving voltage is non-periodic, and the period becomes smaller as the driving voltage increases. This characteristic of the coherent receiver results in a control accuracy that is inferior as the driving voltage is larger with the same driving voltage stepping accuracy.
Currently, a high-speed ADC (Analog to Digital Converter, analog-to-digital converter) inside a DSP (Digital Signal Process, digital signal processing) chip is generally used in the industry to collect a radio frequency signal, and then a digital signal processing algorithm is used to obtain an IQ phase angle. The digital processing algorithms of all DSP factories are different, and an external reading interface is not provided generally, so that the condition that the optical module internally uses DSP chips and silicon optical devices of different factories in actual application cannot be satisfied.
Disclosure of Invention
Aiming at the defects in the prior art, the first aspect of the invention is to provide a phase angle locking method of a coherent receiver, which can be compatible with DSP chips and silicon optical devices of different factories and can accurately control the IQ phase angle of the coherent receiver at an orthogonal position.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a phase angle locking method of a coherent receiver, the method comprising the steps of:
acquiring an initial value of a driving voltage when phase angles are orthogonal;
fine tuning the initial value of the driving voltage, and determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate;
and adjusting the driving voltage in real time according to the calibration parameters and the driving voltage calibration value, so that the current phase angle acquired in real time is kept at the phase angle calibration value.
In some embodiments, the trimming the initial value of the driving voltage, determining the calibration parameter, the driving voltage calibration value and the phase angle calibration value for adjusting the driving voltage according to the fed-back error rate, includes:
fine-tuning the initial value of the driving voltage, and determining a stepping voltage which can minimize the average value of error rate change when the driving voltage is regulated;
and determining the calibration parameter according to the step voltage, and adjusting the driving voltage according to the step voltage to obtain a driving voltage calibration value and a phase angle calibration value in a minimum bit error rate state.
In some embodiments, the trimming the initial value of the driving voltage to determine the step voltage that can minimize the average value of the error rate variation when adjusting the driving voltage includes:
setting stepping voltages with different step sizes and a preset number of driving voltage points, and calculating an average value of error rate change when each stepping voltage is regulated to the driving voltage point;
and determining the stepping voltage corresponding to the minimum average value of the error rate variation.
In some embodiments, the determining the calibration parameter according to the step voltage, and adjusting the driving voltage according to the step voltage, to obtain a driving voltage calibration value and a phase angle calibration value in a minimum bit error rate state, including;
according to the formula:
determination ofCalibration parameters->
Wherein V is n And V n+1 Step for the n-th and n+1-th driving voltage points at a step voltage with the smallest average value of error rate variation phase K is the slope of a phase characteristic curve of the coherent receiver, which is a parameter for minimizing error rate jump in the driving voltage adjustment process;
adjusting the driving voltage to each set driving voltage point according to the step voltage, and recording the bit error rate under each driving voltage point;
and taking the driving voltage point corresponding to the minimum error rate as a driving voltage calibration value, and taking the phase angle under the driving voltage calibration value as a phase angle calibration value.
In some embodiments, the adjusting the driving voltage in real time according to the calibration parameter and the driving voltage calibration value to keep the current phase angle acquired in real time at the phase angle calibration value includes:
determining a direction bit flag for adjusting the driving voltage according to the driving voltage calibration value;
tracking and monitoring the current phase angle according to the formula:
and adjusting the driving voltage in real time to enable the current phase angle to be kept at the phase angle calibration value, wherein the flag is equal to 1 or-1.
In some embodiments, the determining the direction flag for adjusting the driving voltage according to the driving voltage calibration value includes:
setting a plurality of driving voltage points left and right by taking the driving voltage calibration value as a center according to the stepping voltage;
when the driving voltage increases or decreases, if the phase angle change trend is the same, flag is equal to 1;
when the driving voltage increases or decreases, if the phase angle change trend is opposite, flag is equal to-1.
In some embodiments, the obtaining the initial value of the driving voltage when the phase angles are orthogonal includes:
determining the output voltage of the phase detector with the orthogonal phase angles according to the characteristic curve of the hardware circuit of the phase detector;
and according to the output voltage of the phase detector when the phase angles are in quadrature, roughly scanning a phase angle-driving voltage curve to obtain an initial value of the driving voltage.
The second aspect of the present invention is to provide a phase angle locking system of a coherent receiver, which is compatible with DSP chips and silicon optical devices of different manufacturers and is capable of precisely controlling the IQ phase angle of the coherent receiver to be in a quadrature position.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a phase angle locking system of a coherent receiver, comprising:
a phase detector for coupling to the mixer to obtain a current phase angle of the mixer;
digital signal processing dsp for obtaining bit error rates at respective driving voltages;
the controller is used for fine tuning the initial value of the driving voltage, determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate, and adjusting the driving voltage in real time according to the calibration parameter and the driving voltage calibration value so as to keep the current phase angle at the phase angle calibration value;
a compensation unit for squaring the driving voltage outputted from the controller;
and the current source is used for outputting the driving voltage processed by the compensation unit to the mixer.
In some embodiments, the phase detector comprises:
an X-polarization phase detector for receiving the mixer-recovered rf differential signals XI and XQ;
and the Y polarization phase detector is used for receiving the radio frequency differential signals YI and YQ recovered by the mixer.
In some embodiments, further comprising:
an analog-to-digital converter connected between the phase detector and the controller;
a digital-to-analog converter connected between the compensation unit and the current source.
Compared with the prior art, the invention has the advantages that:
the phase angle locking method of the coherent receiver directly obtains the phase difference of the homodromous component and the orthogonal component of the radio frequency differential signal recovered by the mixer by adopting a hardware method, does not need each DSP manufacturer to externally provide a reading interface, and can be compatible with DSP chips and silicon optical devices of different manufacturers. Further, by compensating the adjustment value of the driving voltage and then linearly responding to the driving voltage, the IQ phase angle of the coherent receiver can be precisely controlled to the quadrature position.
Drawings
Fig. 1 is a flowchart of a phase angle locking method of a coherent receiver according to an embodiment of the present invention;
FIG. 2 is a graph showing the relationship between the phase angle of an input signal and the output voltage of a phase detector according to an embodiment of the present invention;
FIG. 3 is a graph of phase angle versus driving voltage and square of driving voltage in an embodiment of the present invention;
fig. 4 is a block diagram of a phase angle locking system of a coherent receiver according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, an embodiment of the present invention provides a phase angle locking method of a coherent receiver, which is characterized in that the method includes the following steps:
s1, acquiring an initial value of the driving voltage when the phase angles are orthogonal.
Specifically, step S1 includes:
s11, determining the output voltage of the phase detector with the orthogonal phase angles according to the characteristic curve of the hardware circuit of the phase detector.
The characteristic curve of the hardware circuit of the phase detector can be seen in fig. 2, wherein the abscissa in fig. 2 represents the phase angle, and the ordinate represents the output voltage of the phase detector.
S12, rough scanning of a phase angle-driving voltage curve is carried out according to the output voltage of the phase detector when the phase angles are in quadrature, and an initial value of the driving voltage is obtained.
According to the basic characteristic curve of the phase detector hardware circuit, the basic value (output voltage of the phase sampling system) of the detector output voltage can be obtained when the phase angle is 90 degrees, and the initial value of the driving voltage can be deduced by rough scanning of the phase angle-driving voltage curve.
S2, fine tuning is carried out on the initial value of the driving voltage, and the calibration parameter, the driving voltage calibration value and the phase angle calibration value for adjusting the driving voltage are determined according to the fed-back error rate.
In this embodiment, step S2 mainly includes trimming the driving voltage around the initial value of the obtained driving voltage, finding a state corresponding to the minimum bit error rate, and recording the phase angle size and calibration parameters in the state, where the phase angle size is the phase angle calibration value.
Specifically, in the specific implementation, step S2 includes:
s21, fine tuning is carried out on the initial value of the driving voltage, and step voltage which can enable the average value of error rate change to be minimum when the driving voltage is regulated is determined.
Specifically, first, a plurality of stepping voltages with different step sizes and a preset number of driving voltage points are set, and an average value of error rate changes when the stepping voltages are adjusted to the driving voltage points is calculated.
For example, the setting sizes are respectively DeltaV 1 、ΔV 2 、ΔV 3 It can be understood that the voltage difference between two adjacent driving voltage points is a stepping voltage value, and the number of the driving voltage points can be reasonably set according to the requirement, which is not limited in this embodiment.
After the step voltage and the driving voltage point are set, the average value of the error rate change under each step voltage can be calculated, and then the step voltage corresponding to the minimum average value of the error rate change can be determined.
S22, determining the calibration parameters according to the step voltage, and adjusting the driving voltage according to the step voltage to obtain a driving voltage calibration value and a phase angle calibration value in a minimum bit error rate state.
After the desired step voltage is obtained, the formula is followed:
determining calibration parameters
Wherein V is n And V n+1 Step for the n-th and n+1-th driving voltage points at a step voltage with the smallest average value of error rate variation phase And K is the slope of a phase characteristic curve of the coherent receiver, which is a parameter for minimizing error rate jump in the driving voltage adjustment process.
And regulating the driving voltage to each set driving voltage point according to the stepping voltage, and recording the bit error rate under each driving voltage point.
And taking the driving voltage point corresponding to the minimum error rate as a driving voltage calibration value, and taking the phase angle under the driving voltage calibration value as a phase angle calibration value.
In a specific implementation, 20 driving voltage points can be respectively set around the initial value of the driving voltage, then the driving voltage is adjusted, and meanwhile, the error rate under each driving voltage point is recorded. The required drive voltage calibration and phase angle calibration can then be obtained.
It is worth noting that the thermo-optic effect of silicon-based waveguides changes the refractive index by heating the waveguide through electrical resistance, thereby changing the phase. The phase change of the silicon-based waveguide is linear with heat. The heat of the silicon-based waveguide is determined by the power of the resistor, which is square with the driving voltage, and thus the IQ phase angle is square with the driving voltage. The phase angle of the coherent receiver is given in fig. 3 below as a function of the driving voltage and the square of the driving voltage.
After square processing is performed on the driving voltage, the phase angle and the square of the driving voltage can be known to show periodicityAnd exhibits a linear relationship in each interval. Thus, after the curve is folded, the relationship between phase angle phase and driving voltage V can be qualitatively expressed as: phase=kv 2 +phase0。
From the above qualitative relation, a processing mode can be obtained, and the detected phase is directly proportional to the loaded driving voltage after the squaring process. But this approach requires determining the offset phase0 of the device. Because the bias phases of different devices are different, this approach is not easily implemented in mass production.
Therefore, in this embodiment, the rough target driving voltage is obtained by the rough phase angle mode, and then the influence of the offset phase0 can be eliminated by subtracting according to the following two formulas.
phase n ＝KV n 2 +phase0
phase n+1 ＝KV n+1 2 +phase0
And performing subtraction operation according to the two formulas to obtain the following equation:
step phase ＝K(V n+1 2 -V n 2 )
the conversion can be carried out to obtain:
the simplified formula can be obtained:
wherein->
From this formula it can be seen that the effect of the offset phase0 has been eliminated.
S3, driving voltage is regulated in real time according to the calibration parameters and the driving voltage calibration value, so that the current phase angle acquired in real time is kept at the phase angle calibration value.
After determining the calibration value of the phase angle, the present embodiment then obtains the current phase angle of the mixer through the phase detector.
The rf differential signals recovered by the mixer are input to the phase detector, specifically, the rf differential signals XI and XQ are input to the X-polarization phase detector, and the rf differential signals YI and YQ are input to the Y-polarization phase detector.
The voltage output by the phase detector is related to the phase angle between I and Q, so the current phase angle of the mixer can be determined from the voltage output by the phase detector.
It can be understood that in this embodiment, since the hardware method is adopted to directly obtain the phase difference between the homodromous component and the quadrature component of the radio frequency differential signal recovered by the mixer, each DSP manufacturer is not required to provide a read interface externally, and the method can be compatible with DSP chips and silicon optical devices of different manufacturers.
In a specific implementation, step S3 includes:
s31, determining a direction bit flag for adjusting the driving voltage according to the driving voltage calibration value.
It should be noted that, after the phase angle calibration value is determined as the adjustment target, the adjustment direction of the driving voltage needs to be determined.
Specifically, a plurality of driving voltage points are set left and right centering on the driving voltage calibration value according to the step voltage; when the driving voltage increases or decreases, if the phase angle change trend is the same, flag is equal to 1; when the driving voltage increases or decreases, if the phase angle change trend is opposite, flag is equal to-1.
After such setting, it is ensured that the drive voltage is not offset when adjusted, resulting in a phase angle that is far from the phase angle calibration value.
S32, tracking and monitoring the current phase angle, and according to the formula:
and adjusting the driving voltage in real time to enable the current phase angle to be kept at the phase angle calibration value, wherein the flag is equal to 1 or-1.
It should be noted that, referring to fig. 3, fig. 3 shows a relationship between a phase angle and a driving voltage of the coherent receiver and a square of the driving voltage. In the figure, the vertical axis represents the phase angle, and the horizontal axis represents the square of the driving voltage and the driving voltage, respectively. Because the IQ phase angle represents the I-path and Q-path relative phase shift, the range is 0-180 degrees. The phase shift first increases from 0 degrees to 180 degrees and then from 180 degrees to 360 degrees, which is equivalent to a decrease from 180 degrees to 0 degrees in view of the relative phase shift. As can be seen from the figure, the phase angle is linear with the square of the drive voltage during each cycle.
Therefore, the driving voltage is firstly subjected to squaring operation and then is loaded on the silicon-based waveguide, so that the generated phase and the driving voltage can be ensured to form linear response.
It will be appreciated that, since the phase detector outputs an analog voltage signal, in this embodiment, the analog voltage signal is first converted into a sampling value by the analog-to-digital converter, then the controller determines the required configuration value of the driving voltage to be issued, and then the configuration value of the driving voltage to be issued needs to be linearly converted into the driving voltage before the driving voltage acts on the mixer, where voltage=configuration value/2-bit reference voltage. Wherein the reference voltage is a hardware reference voltage of a DAC (Digital to analog converter, digital-to-analog converter) chip. And the adjustment value is compensated for by processing the driving voltage configuration value.
In summary, according to the phase angle locking method of the coherent receiver, the phase difference between the homodromous component and the orthogonal component of the radio frequency differential signal recovered by the mixer is directly obtained by adopting a hardware method, so that each DSP manufacturer is not required to provide a reading interface externally, and the phase angle locking method can be compatible with DSP chips and silicon optical devices of different manufacturers. Further, by compensating the adjustment value of the driving voltage and then linearly responding to the driving voltage, the IQ phase angle of the coherent receiver can be precisely controlled to the quadrature position.
Referring to fig. 4, an embodiment of the present invention provides a phase angle locking system of a coherent receiver, which includes a phase detector, a digital signal processing dsp, a controller, a compensation unit, and a current source.
The phase detector is used for being connected with the mixer to obtain the current phase angle of the mixer; the digital signal processing dsp is used for obtaining the error rate under each driving voltage; the controller is used for fine tuning the initial value of the driving voltage, determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate, and adjusting the driving voltage in real time according to the calibration parameter and the driving voltage calibration value so as to keep the current phase angle at the phase angle calibration value; the compensation unit is used for performing squaring processing on the driving voltage output by the controller; the current source is used for outputting the driving voltage processed by the compensation unit to the mixer.
In this embodiment, the phase detector includes an X-polarization phase detector and a Y-polarization phase detector, and in actual use, the radio frequency differential signals XI and XQ are input to the X-polarization phase detector, and the radio frequency differential signals YI and YQ are input to the Y-polarization phase detector, so as to obtain the current phase angle of the mixer.
At the same time, the voltage output by the phase detector is also transmitted to the controller, and because the phase detector outputs an analog voltage signal, the system in the embodiment further comprises an analog-to-digital converter, which is used for being connected between the phase detector and the controller, for the convenience of processing by the controller. The analog-to-digital converter converts the analog voltage signal into a digital signal and then transmits the digital signal to the controller for processing.
It should be noted that the compensation unit in this embodiment is connected between the controller and the current source and is configured to compensate the adjustment value so that the phase angle is linearly responsive to the driving voltage. Specifically, since the IQ phase angle is square with the driving voltage, the compensation unit in the embodiment is configured to perform the squaring process on the adjustment value to compensate for the convenience of operation, so that the phase angle is linearly responsive to the driving voltage.
It can be understood that the driving voltage configuration value issued by the controller is processed by the compensation unit, and then digital-to-analog conversion is needed to facilitate the driving voltage to act on the mixer, so that the system in this embodiment further includes a digital-to-analog converter connected between the compensation unit and the current source, and after the compensation unit processes the driving voltage configuration value issued by the controller, the driving voltage configuration value is converted into a linear voltage by the digital-to-analog converter, and then the driving voltage is acted on the mixer by the current source.
In summary, in the phase angle locking system of the coherent receiver, the phase difference between the homodromous component and the quadrature component of the radio frequency differential signal recovered by the mixer is directly obtained by adopting hardware, so that each DSP manufacturer is not required to provide a reading interface externally, and the phase angle locking system can be compatible with DSP chips and silicon optical devices of different manufacturers. Further, by compensating the adjustment value of the driving voltage and then linearly responding to the driving voltage, the IQ phase angle of the coherent receiver can be precisely controlled to the quadrature position.
The invention is not limited to the embodiments described above, but a number of modifications and adaptations can be made by a person skilled in the art without departing from the principle of the invention, which modifications and adaptations are also considered to be within the scope of the invention. What is not described in detail in this specification is prior art known to those skilled in the art.
Claims (10)
1. A phase angle locking method for a coherent receiver, the method comprising the steps of:
acquiring an initial value of a driving voltage when phase angles are orthogonal;
fine tuning the initial value of the driving voltage, and determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate;
and adjusting the driving voltage in real time according to the calibration parameters and the driving voltage calibration value, so that the current phase angle acquired in real time is kept at the phase angle calibration value.
2. The phase angle locking method of claim 1, wherein the fine tuning of the initial value of the driving voltage, determining the calibration parameter, the driving voltage calibration value, and the phase angle calibration value for adjusting the driving voltage according to the fed-back bit error rate, comprises:
fine-tuning the initial value of the driving voltage, and determining a stepping voltage which can minimize the average value of error rate change when the driving voltage is regulated;
and determining the calibration parameter according to the step voltage, and adjusting the driving voltage according to the step voltage to obtain a driving voltage calibration value and a phase angle calibration value in a minimum bit error rate state.
3. The phase angle locking method of a coherent receiver according to claim 2, wherein said fine-tuning an initial value of said driving voltage to determine a step voltage that minimizes an average value of a change in bit error rate when adjusting the driving voltage, comprises:
setting stepping voltages with different step sizes and a preset number of driving voltage points, and calculating an average value of error rate change when each stepping voltage is regulated to the driving voltage point;
and determining the stepping voltage corresponding to the minimum average value of the error rate variation.
4. The phase angle locking method of a coherent receiver according to claim 2, wherein said determining said calibration parameter according to said step voltage and adjusting a driving voltage according to said step voltage, obtaining a driving voltage calibration value and a phase angle calibration value in a minimum bit error rate state, comprises;
according to the formula:
determining calibration parameters->
Wherein V is n And V n+1 Step for the n-th and n+1-th driving voltage points at a step voltage with the smallest average value of error rate variation phase K is the slope of a phase characteristic curve of the coherent receiver, which is a parameter for minimizing error rate jump in the driving voltage adjustment process;
adjusting the driving voltage to each set driving voltage point according to the step voltage, and recording the bit error rate under each driving voltage point;
and taking the driving voltage point corresponding to the minimum error rate as a driving voltage calibration value, and taking the phase angle under the driving voltage calibration value as a phase angle calibration value.
5. The phase angle locking method of claim 4, wherein said adjusting the driving voltage in real time based on said calibration parameter and a driving voltage calibration value to maintain the current phase angle acquired in real time at said phase angle calibration value comprises:
determining a direction bit flag for adjusting the driving voltage according to the driving voltage calibration value;
tracking and monitoring the current phase angle according to the formula:
and adjusting the driving voltage in real time to enable the current phase angle to be kept at the phase angle calibration value, wherein the flag is equal to 1 or-1.
6. The phase angle locking method of a coherent receiver according to claim 5, wherein said determining a direction bit flag for adjusting a driving voltage based on said driving voltage calibration value comprises:
setting a plurality of driving voltage points left and right by taking the driving voltage calibration value as a center according to the stepping voltage;
when the driving voltage increases or decreases, if the phase angle change trend is the same, flag is equal to 1;
when the driving voltage increases or decreases, if the phase angle change trend is opposite, flag is equal to-1.
7. The phase angle locking method of a coherent receiver according to claim 1, wherein said obtaining an initial value of a driving voltage when phase angles are orthogonal comprises:
determining the output voltage of the phase detector with the orthogonal phase angles according to the characteristic curve of the hardware circuit of the phase detector;
and according to the output voltage of the phase detector when the phase angles are in quadrature, roughly scanning a phase angle-driving voltage curve to obtain an initial value of the driving voltage.
8. A phase angle locking system for a coherent receiver, comprising:
a phase detector for coupling to the mixer to obtain a current phase angle of the mixer;
digital signal processing dsp for obtaining bit error rates at respective driving voltages;
the controller is used for fine tuning the initial value of the driving voltage, determining a calibration parameter, a driving voltage calibration value and a phase angle calibration value for adjusting the driving voltage according to the fed-back error rate, and adjusting the driving voltage in real time according to the calibration parameter and the driving voltage calibration value so as to keep the current phase angle at the phase angle calibration value;
a compensation unit for squaring the driving voltage outputted from the controller;
and the current source is used for outputting the driving voltage processed by the compensation unit to the mixer.
9. The phase angle locking system of claim 8, wherein said phase detector comprises:
an X-polarization phase detector for receiving the mixer-recovered rf differential signals XI and XQ;
and the Y polarization phase detector is used for receiving the radio frequency differential signals YI and YQ recovered by the mixer.
10. The phase angle locking system of a coherent receiver of claim 8, further comprising:
an analog-to-digital converter connected between the phase detector and the controller;
a digital-to-analog converter connected between the compensation unit and the current source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210533779.8A CN115021827B (en) | 2022-05-16 | 2022-05-16 | Phase angle locking method and system of coherent receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210533779.8A CN115021827B (en) | 2022-05-16 | 2022-05-16 | Phase angle locking method and system of coherent receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115021827A CN115021827A (en) | 2022-09-06 |
| CN115021827B true CN115021827B (en) | 2023-05-09 |
Family
ID=83069330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210533779.8A Active CN115021827B (en) | 2022-05-16 | 2022-05-16 | Phase angle locking method and system of coherent receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115021827B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6917031B1 (en) * | 2004-02-17 | 2005-07-12 | Nortel Networks Limited | Method for quadrature phase angle correction in a coherent receiver of a dual-polarization optical transport system |
| JP2012044626A (en) * | 2010-08-23 | 2012-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Digital coherent light receiver |
| JP2013162182A (en) * | 2012-02-01 | 2013-08-19 | Nippon Telegr & Teleph Corp <Ntt> | Optical signal quality measurement method, optical signal quality measurement circuit, optical receiver and optical transmission system |
| CN103457616A (en) * | 2013-09-03 | 2013-12-18 | 广州润芯信息技术有限公司 | Orthogonal mismatch calibration method and device of direct frequency conversion transmitter |
| JP2014123905A (en) * | 2012-12-21 | 2014-07-03 | Mitsubishi Electric Corp | Coherent optical receiver |
| CN106549714A (en) * | 2016-10-31 | 2017-03-29 | 武汉光迅科技股份有限公司 | A kind of control method and control device based on IQ electrooptic modulator quadrature voltages |
| CN108809434A (en) * | 2017-05-01 | 2018-11-13 | 谷歌有限责任公司 | Mitigate the defect of the optical modulator of coherent optical communication system |
| CN110190907A (en) * | 2019-07-29 | 2019-08-30 | 烽火通信科技股份有限公司 | A kind of I/Q signal phase error control method and system |
| CN112789814A (en) * | 2019-05-24 | 2021-05-11 | 谷歌有限责任公司 | Low power coherent receiver for short range optical communications |
| CN113346956A (en) * | 2021-05-08 | 2021-09-03 | 华中科技大学 | Pilot-based bias control device and method for IQ modulator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6281387B2 (en) * | 2014-04-07 | 2018-02-21 | 富士通株式会社 | Digital coherent receiver and receiving method |
| JP2019074612A (en) * | 2017-10-13 | 2019-05-16 | 富士通株式会社 | Optical transmitter, optical transmission device, and control method of optical transmitter |
-
2022
- 2022-05-16 CN CN202210533779.8A patent/CN115021827B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6917031B1 (en) * | 2004-02-17 | 2005-07-12 | Nortel Networks Limited | Method for quadrature phase angle correction in a coherent receiver of a dual-polarization optical transport system |
| JP2012044626A (en) * | 2010-08-23 | 2012-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Digital coherent light receiver |
| JP2013162182A (en) * | 2012-02-01 | 2013-08-19 | Nippon Telegr & Teleph Corp <Ntt> | Optical signal quality measurement method, optical signal quality measurement circuit, optical receiver and optical transmission system |
| JP2014123905A (en) * | 2012-12-21 | 2014-07-03 | Mitsubishi Electric Corp | Coherent optical receiver |
| CN103457616A (en) * | 2013-09-03 | 2013-12-18 | 广州润芯信息技术有限公司 | Orthogonal mismatch calibration method and device of direct frequency conversion transmitter |
| CN106549714A (en) * | 2016-10-31 | 2017-03-29 | 武汉光迅科技股份有限公司 | A kind of control method and control device based on IQ electrooptic modulator quadrature voltages |
| CN108809434A (en) * | 2017-05-01 | 2018-11-13 | 谷歌有限责任公司 | Mitigate the defect of the optical modulator of coherent optical communication system |
| CN112789814A (en) * | 2019-05-24 | 2021-05-11 | 谷歌有限责任公司 | Low power coherent receiver for short range optical communications |
| CN110190907A (en) * | 2019-07-29 | 2019-08-30 | 烽火通信科技股份有限公司 | A kind of I/Q signal phase error control method and system |
| CN113346956A (en) * | 2021-05-08 | 2021-09-03 | 华中科技大学 | Pilot-based bias control device and method for IQ modulator |
Non-Patent Citations (3)
| Title |
|---|
| Calibration of in-phase/quadrature amplitude and phase response imbalance for coherent receiver;Cheng Ju.etc;2017 Optical Fiber Communications Conference and Exhibition (OFC);全文 * |
| 星地激光通信中光学数字相干接收机的研究;董光焰;徐圣奇;;激光与红外(第11期);全文 * |
| 正交调制器的校准设计;周建烨;;电子质量(第03期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115021827A (en) | 2022-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11086187B2 (en) | Bias control of optical modulators | |
| US11870407B2 (en) | Method and apparatus for bias control with a large dynamic range for Mach-Zehnder modulators | |
| US9686017B2 (en) | Bias control circuit for optical modulator, and optical transmitter comprising the same | |
| EP2432139B1 (en) | Method, device and system for feedback control of a coherent receiver | |
| US9124364B1 (en) | Quadrature power balance control in optical transmitters | |
| US9989785B2 (en) | In-situ ring-resonator-modulator calibration | |
| US10042190B2 (en) | Second order detection of two orthogonal dithers for I/Q modulator bias control | |
| JP5038219B2 (en) | Optical receiver | |
| JP2013511059A (en) | Modulator control system and method in optical network | |
| US10826621B2 (en) | Rx delay line inteferometer tracking in closed-loop module control for communication | |
| US20160204569A1 (en) | Wavelength tunable optical transmitter | |
| JPWO2017056350A1 (en) | Pluggable optical module and optical communication system | |
| US20220140899A1 (en) | Closed loop module control for communication based on signal quality | |
| US10862589B2 (en) | Histogram based optimization for optical modulation | |
| US9819412B1 (en) | Transmitter gain imbalance and skew optimization for coherent transmitters | |
| US10890822B2 (en) | Mach-zehnder optical modulator | |
| CN115021827B (en) | Phase angle locking method and system of coherent receiver | |
| US20230254043A1 (en) | Optical modulator control system for interconnect transceivers | |
| CN108964758B (en) | Method and system for measuring chirp parameters of double-parallel Mach-Zehnder modulator | |
| CN111682904B (en) | Device and method for stabilizing amplitude of radio frequency signal of coherent optical module modulation driver | |
| CN111711487A (en) | Automatic bias working point control system based on temperature drift compensation | |
| CN111984048B (en) | Bias voltage control method and system of optical IQ modulator | |
| US20240120996A1 (en) | Optical transmitter and bias control method | |
| US20230388016A1 (en) | Optimization of rf driver and/or optical device | |
| WO2022137517A1 (en) | Optical transmitter and method of transmitting an optical signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |