CN115021695A

CN115021695A - Operational amplifier input circuit and method for dynamically adjusting substrate voltage of operational amplifier input circuit

Info

Publication number: CN115021695A
Application number: CN202210698806.7A
Authority: CN
Inventors: 龚启善; 石传波
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2022-06-20
Filing date: 2022-06-20
Publication date: 2022-09-06

Abstract

The invention discloses an operational amplifier input circuit and a method for dynamically adjusting the substrate voltage of the operational amplifier input circuit, wherein the operational amplifier input circuit comprises: the circuit comprises an input stage unit, a substrate biasing unit and a substrate voltage regulating unit. The input stage unit comprises a first differential transistor pair; the substrate bias unit comprises a second differential transistor pair and a resistance unit, wherein the resistance unit is used for outputting a substrate voltage provided for the first differential transistor pair; the substrate voltage adjusting unit adjusts the substrate voltage according to a change of the input common mode voltage. According to the operational amplifier input circuit, the substrate voltage of the first differential transistor pair of the input stage unit is set through the substrate biasing unit, and the substrate voltage is adjusted through the substrate voltage adjusting unit when the input common-mode voltage changes in a large range, so that a better working point is provided for the input stage unit, and index performances of the circuit at low common-mode voltage and high common-mode voltage, such as common-mode rejection ratio, are improved.

Description

Operational amplifier input circuit and method for dynamically adjusting substrate voltage of operational amplifier input circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to an operational amplifier input circuit and a method for dynamically adjusting a substrate voltage of the operational amplifier input circuit.

Background

The high-voltage input common-mode voltage range of the operational amplifier is generally 0V to Vdd-1.5V or Vdd, and belongs to a larger range. Under a common operational amplifier structure, there is a Trade-off (Trade off) between a differential transistor pair and a tail current tube of an input stage unit, and when the situation is extreme, there may be only a relatively small margin between the two. The prior art uses the channel modulation effect to increase the turn-on voltage Vth of the differential transistor pair by providing the substrate with a level between the power supply voltage Vdd and the source terminal voltage, so as to optimize the performance of the 0V common mode, but the input common mode voltage range is large, and the operating state of the input stage unit is still not ideal under the change of the full-temperature and full-process corner.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide an operational amplifier input circuit and a method for dynamically adjusting the substrate voltage of the operational amplifier input circuit, which can still provide a better working point for an input stage unit under the condition of large input common mode voltage change range.

To achieve the above object, an embodiment of the present invention provides an operational amplifier input circuit, including: the circuit comprises an input stage unit, a substrate biasing unit and a substrate voltage regulating unit.

The input stage cell includes a first differential transistor pair for receiving a differential input signal.

The substrate bias unit comprises a second differential transistor pair and a resistance unit, wherein a first end of the resistance unit is used for outputting a substrate voltage provided for the first differential transistor pair of the input stage unit, a second end of the resistance unit is connected with the second differential transistor pair, and the second differential transistor pair is used for receiving differential input signals.

The substrate voltage adjusting unit is used for adaptively adjusting the voltage difference between the first end and the second end of the resistor unit according to the input common-mode voltage so as to adjust the substrate voltage.

In one or more embodiments of the present invention, the substrate voltage adjusting unit is configured to dynamically adjust a current flowing through the resistor unit and/or adjust a resistance value of the resistor unit according to a magnitude of the input common mode voltage to change the substrate voltage.

In one or more embodiments of the present invention, the substrate voltage adjusting unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a current mirror unit;

the first ends of the fourth transistor and the fifth transistor are connected with a power supply voltage, the control ends of the fourth transistor and the fifth transistor are connected with a first control voltage, the second end of the fifth transistor is connected with the second end of the first transistor, the first ends of the sixth transistor, the seventh transistor and the eighth transistor are connected with the second end of the fourth transistor, the control ends of the sixth transistor and the seventh transistor are used for receiving the differential input signal, the second ends of the sixth transistor and the seventh transistor are grounded, the control end of the eighth transistor is connected with a reference voltage, the current mirror unit is connected with the second end of the eighth transistor and the first end of the resistance unit, and substrates of the sixth transistor, the seventh transistor and the eighth transistor are connected with the first end of the resistance unit.

In one or more embodiments of the present invention, the substrate bias unit includes:

the first end of the first transistor is connected with a power supply voltage, the second end of the first transistor is connected with the substrate voltage regulating unit, and the control end of the first transistor is connected with a first control voltage;

the first end of the resistance unit is connected with the second end of the first transistor and the substrate voltage adjusting unit and forms a middle node for providing substrate voltage for the differential transistor pair of the input stage unit, and the resistance value of the resistance unit is a fixed resistance value or an adjustable resistance value; and

the second transistor and the third transistor form a second differential transistor pair, control ends of the second transistor and the third transistor are used for receiving the differential input signal, first ends of the second transistor and the third transistor are connected with a second end of the first resistor, second ends of the second transistor and the third transistor are grounded, and substrates of the second transistor and the third transistor are connected with a first end of the resistor unit.

In one or more embodiments of the present invention, the input stage unit includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, a first terminal of the eleventh transistor is connected to the power supply voltage, a control terminal of the eleventh transistor is connected to the first control voltage, the twelfth transistor and the thirteenth transistor form a first differential transistor pair, control terminals of the twelfth transistor and the thirteenth transistor are configured to receive the differential input signal, first terminals of the twelfth transistor and the thirteenth transistor are connected to a second terminal of the eleventh transistor, second terminals of the twelfth transistor and the thirteenth transistor are configured to output a differential current signal, and substrates of the twelfth transistor and the thirteenth transistor are connected to the first terminal of the resistance unit.

In one or more embodiments of the present invention, the input stage unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

a first terminal of the eleventh transistor is connected with a power supply voltage, a control terminal of the eleventh transistor is connected with a first control voltage, the twelfth transistor and the thirteenth transistor form a first differential transistor pair, the control terminals of the twelfth transistor and the thirteenth transistor are used for receiving the differential input signal, the first terminals of the twelfth transistor and the thirteenth transistor are connected with a second terminal of the eleventh transistor, the second terminals of the twelfth transistor and the thirteenth transistor are used for outputting a differential current signal, and substrates of the twelfth transistor and the thirteenth transistor are connected with the first terminal of the resistance unit;

the substrate bias unit includes:

the first end of the resistance unit is connected with the second end of the first transistor and the substrate voltage regulating unit and forms a middle node for providing substrate voltage for the differential transistor pair of the input stage unit, and the resistance value of the resistance unit is a fixed resistance value or an adjustable resistance value; and

the second transistor and the third transistor form a second differential transistor pair, control ends of the second transistor and the third transistor are used for receiving the differential input signal, first ends of the second transistor and the third transistor are connected with a second end of the first resistor, second ends of the second transistor and the third transistor are grounded, and substrates of the second transistor and the third transistor are connected with a first end of the resistor unit;

the substrate biasing unit further comprises a level shift circuit, and the input stage unit further comprises a seventeenth transistor and an eighteenth transistor;

the level shifter circuit is connected with the first ends of the second transistor and the third transistor, the second end of the first resistor and the control ends of the seventeenth transistor and the eighteenth transistor, the level shifter circuit controls the voltages of the control ends of the seventeenth transistor and the eighteenth transistor to follow the voltage change of the first ends of the second transistor and the third transistor, so that the voltage between the first end and the second end of the twelfth transistor and the voltage between the first end and the second end of the thirteenth transistor are clamped, the first end of the seventeenth transistor is connected with the second end of the twelfth transistor, the first end of the eighteenth transistor is connected with the second end of the thirteenth transistor, and the second ends of the seventeenth transistor and the eighteenth transistor are used for outputting differential current signals.

In one or more embodiments of the present invention, the level shifter circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

the first end of the fourteenth transistor is connected with the second end of the first resistor, the control end of the fourteenth transistor is in short circuit with the second end, the first end of the fifteenth transistor is connected with the second end of the fourteenth transistor, the second end of the fifteenth transistor is in short circuit with the control end, the second end of the sixteenth transistor is connected with the second end of the fifteenth transistor, the control end of the sixteenth transistor is connected with the second control voltage, the first end of the sixteenth transistor is grounded, and the second end of the fifteenth transistor is connected with the control ends of the seventeenth transistor and the eighteenth transistor.

In one or more embodiments of the present invention, the substrate bias unit further includes a twentieth transistor; the first end of the twentieth transistor is connected with the second ends of the second transistor and the third transistor, and the control end of the twentieth transistor is connected with the second end of the fifteenth transistor.

first ends of the fourth transistor and the fifth transistor are connected with a power supply voltage, control ends of the fourth transistor and the fifth transistor are connected with a first control voltage, a second end of the fifth transistor is connected with a second end of the first transistor, first ends of the sixth transistor, the seventh transistor and the eighth transistor are connected with a second end of the fourth transistor, the control ends of the sixth transistor and the seventh transistor are used for receiving the differential input signal, second ends of the sixth transistor and the seventh transistor are grounded, a control end of the eighth transistor is connected with a reference voltage, the current mirror unit is connected with a second end of the eighth transistor and a first end of the resistance unit, and substrates of the sixth transistor, the seventh transistor and the eighth transistor are connected with a first end of the resistance unit;

the substrate voltage adjusting unit further comprises a twenty-fifth transistor and a twenty-sixth transistor;

a first end of the twenty-fifth transistor is connected with second ends of the sixth transistor and the seventh transistor, and a control end of the twenty-fifth transistor is connected with a second end of the fifteenth transistor;

the first end of the twenty-sixth transistor is connected with the second end of the eighth transistor, the second end of the twenty-sixth transistor is connected with the current mirror unit, and the control end of the twenty-sixth transistor is connected with the second end of the fifteenth transistor.

In one or more embodiments of the present invention, the operational amplifier input circuit further includes a protection circuit, the protection circuit including a twenty-ninth transistor, a thirtieth transistor, and a first clamp circuit;

the second end of the twenty-ninth transistor is coupled to the first input end, the second end of the thirtieth transistor is coupled to the second input end, the control ends of the twenty-ninth transistor and the thirtieth transistor are connected with the first end of the resistance unit, and the first ends of the twenty-ninth transistor and the thirtieth transistor are connected with the first clamping circuit and are simultaneously used for outputting differential input signals.

The invention also discloses a method for dynamically adjusting the substrate voltage of the operational amplifier input circuit, wherein the operational amplifier input circuit comprises a resistor unit, a first differential transistor pair and a second differential transistor pair for receiving differential input signals, the first end of the resistor unit is used for outputting the substrate voltage of the first differential transistor pair provided for the input stage unit, and the second end of the resistor unit is connected with the second differential transistor pair, and the method comprises the following steps:

setting a substrate voltage of a first differential transistor pair of the input stage unit through a second differential transistor pair and a resistance unit based on an input common mode voltage of the differential input signal;

and adaptively adjusting the voltage difference between the first end and the second end of the resistor unit according to the input common-mode voltage so as to adjust the substrate voltage.

In one or more embodiments of the invention, the method further includes dynamically adjusting a current flowing through the resistance unit and/or adjusting a resistance value of the resistance unit according to a magnitude of the input common mode voltage to change the substrate voltage.

Compared with the prior art, according to the operational amplifier input circuit and the method for dynamically adjusting the substrate voltage of the operational amplifier input circuit, the substrate voltage of the first differential transistor pair of the input stage unit is set through the substrate bias unit based on the input common-mode voltage of the differential input signal, and the substrate voltage is adjusted through the substrate voltage adjusting unit when the input common-mode voltage changes in a large range, so that a better working point is provided for the input stage unit, and index performances of the circuit at low common-mode voltage and high common-mode voltage, such as common-mode rejection ratio, are improved.

Drawings

Fig. 1 is a circuit schematic diagram of an operational amplifier input circuit according to an embodiment of the present invention.

Fig. 2 is a circuit schematic of an input stage cell according to an embodiment of the present invention.

Fig. 3 is a circuit schematic of a substrate biasing unit according to an embodiment of the present invention.

Fig. 4 is a circuit schematic of a substrate voltage regulating unit according to an embodiment of the present invention.

Fig. 5 is a circuit schematic of a protection circuit according to an embodiment of the invention.

Fig. 6 is a flow chart of a method for dynamically adjusting the substrate voltage of an op-amp input circuit according to an embodiment of the invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected" to another element or "coupled" to another element, or an element/circuit is referred to as being "connected" between two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

In this application, the transistor may be a MOS transistor or a triode, and the transistor includes a first terminal, a second terminal, and a control terminal. The first end, the second end and the control end of the P-type MOS tube and the N-type MOS tube are respectively a source electrode, a drain electrode and a grid electrode, under the conducting state of the P-type MOS tube, current flows from the first end to the second end, and under the conducting state of the N-type MOS tube, current flows from the second end to the first end. The first end, the second end and the control end of the NPN type triode and the PNP type triode are respectively an emitting electrode, a collector electrode and a base electrode, current flows from the second end to the first end in the conduction state of the NPN type triode, and current flows from the first end to the second end in the conduction state of the PNP type triode.

The invention is further illustrated by the following examples in conjunction with the drawings.

As shown in fig. 1, an operational amplifier input circuit includes: an input stage unit 10, a substrate bias unit 20, and a substrate voltage adjusting unit 30.

The input stage unit 10 includes a first differential transistor pair for receiving a differential input signal INN _ G, INP _ G and outputting a differential current signal.

As shown IN fig. 1 and 2, the input stage unit 10 specifically includes a transistor MP _ BIAS1, a transistor MP _ IN1, and a transistor MP _ IN 2.

In this embodiment, the first terminal of the transistor MP _ BIAS1 is connected to the power supply voltage Vdd, and the control terminal of the transistor MP _ BIAS1 is connected to the first control voltage Vpbias.

The transistor MP _ IN1 and the transistor MP _ IN2 form a first differential transistor pair, control terminals of the transistor MP _ IN1 and the transistor MP _ IN2 are configured to receive a differential input signal INN _ G, INP _ G, first terminals of the transistor MP _ IN1 and the transistor MP _ IN2 are connected to a second terminal of the transistor MP _ BIAS1, and second terminals of the transistor MP _ IN1 and the transistor MP _ IN2 are configured to output a differential current signal.

In addition, the input stage cell 10 further includes a transistor HV _ PCAS1, and the transistor HV _ PCAS1 is a high voltage isolation bias tube for high voltage protection. A first terminal of the transistor HV _ PCAS1 is coupled to the second terminal of the transistor MP _ BIAS1, a second terminal of the transistor HV _ PCAS1 is coupled to the first terminals of the transistor MP _ IN1 and the transistor MP _ IN2, and a control terminal of the transistor HV _ PCAS1 is coupled to the third control voltage Vp _ cas _ BIAS.

In other embodiments, the transistor HV _ PCAS1 may be eliminated.

As shown in fig. 1 and 3, the substrate bias unit 20 in the present embodiment includes a second differential transistor pair and a resistance unit. A first terminal of the resistance unit is arranged to output a substrate voltage VNW supplied to a first differential transistor pair of the input stage unit 10, and a second terminal of the resistance unit is connected to a second differential transistor pair arranged to receive a differential input signal INN _ G, INP _ G. The substrate bias unit 20 is configured to set the substrate voltage VNW of the first differential transistor pair of the input stage unit 10 through the second differential transistor pair and the resistance unit based on the input common mode voltage of the differential input signal INN _ G, INP _ G.

As shown in fig. 1, the substrate bias unit 20 includes: a transistor MP _ BIAS2, a resistance unit, a transistor MP _ IN3, and a transistor MP _ IN 4. The resistance value of the resistance unit is a fixed resistance value or an adjustable resistance value.

Specifically, a first terminal of the transistor MP _ BIAS2 is connected to the power supply voltage Vdd, a second terminal of the transistor MP _ BIAS2 is connected to the substrate voltage regulating unit 30, and a control terminal of the transistor MP _ BIAS2 is connected to the first control voltage Vpbias.

In the present embodiment, the first resistor R1 constitutes a resistance unit. The first and second terminals of the first resistor R1 are the first and second terminals of the resistor unit. A first terminal of the first resistor R1 is connected to the second terminal of the transistor MP _ BIAS2 and the substrate voltage regulating unit 30 and forms an intermediate node O for supplying the substrate voltage VNW to the differential transistor pair of the input stage unit 10. In other embodiments, the resistor unit may be composed of a plurality of first resistors R1 and a switch, and the series-parallel connection between the first resistors R1 is realized by opening and closing the switch, so as to change the resistance value of the resistor unit. Alternatively, the first resistor R1 may be changed in resistance, so that the substrate voltage VNW is changed by adjusting the resistance under the variation of the input common mode voltage.

The substrates of the transistor MP _ IN1 and the transistor MP _ IN2 of the present embodiment are connected to a first terminal of the first resistor R1 to receive the substrate voltage VNW.

The transistor MP _ IN3 and the transistor MP _ IN4 constitute a second differential transistor pair. Control terminals of the transistor MP _ IN3 and the transistor MP _ IN4 are configured to receive the differential input signal INN _ G, INP _ G, first terminals of the transistor MP _ IN3 and the transistor MP _ IN4 are connected to the second terminal of the first resistor R1, second terminals of the transistor MP _ IN3 and the transistor MP _ IN4 are grounded, and substrates of the transistor MP _ IN3 and the transistor MP _ IN4 are connected to the first terminal of the first resistor R1 to receive the substrate voltage VNW.

As shown in fig. 1, the substrate bias unit 20 further includes a level shifter 21, and the input stage unit 10 further includes a transistor HV _ P1 and a transistor HV _ P2. The transistors HV _ P1 and HV _ P2 are high voltage isolation bias transistors.

The level shifter circuit 21 is connected to first terminals of the transistors MP _ IN3 and MP _ IN4, a second terminal of the first resistor R1, and control terminals of the seventeenth and eighteenth transistors HV _ P1 and HV _ P2. The level shifter circuit 21 controls the voltage of the control terminals of the transistors HV _ P1 and HV _ P2 to follow the voltage variation of the first terminals of the transistors MP _ IN3 and MP _ IN4, thereby clamping the voltage between the first terminals and the second terminals of the transistors MP _ IN1 and MP _ IN2, preventing the voltage between the first terminal and the second terminal of the transistor MP _ IN1 and the voltage between the first terminal and the second terminal of the transistor MP _ IN2 from exceeding the withstand voltage value, and playing a role of protection.

The level shifter circuit 21 includes a transistor MP _ DIO1, a transistor MP _ DIO2, and a transistor MN _ BIAS 1.

Specifically, a first end of the transistor MP _ DIO1 is connected to the second end of the first resistor R1, a control end of the transistor MP _ DIO1 is shorted with the second end, a first end of the transistor MP _ DIO2 is connected to the second end of the transistor MP _ DIO1, and a second end of the transistor MP _ DIO2 is shorted with the control end. A second terminal of the transistor MN _ BIAS1 is coupled to the second terminal of the transistor MP _ DIO2, a control terminal of the transistor MN _ BIAS1 is coupled to the second control voltage, and a first terminal of the transistor MN _ BIAS1 is coupled to ground. The first terminal of the transistor HV _ P1 is connected to the second terminal of the transistor MP _ IN1, and the control terminal of the transistor HV _ P1 is connected to the second terminal of the transistor MP _ DIO 2. A first terminal of the transistor HV _ P2 is connected to the second terminal of the transistor MP _ IN2, and a control terminal of the transistor HV _ P2 is connected to the second terminal of the transistor MP _ DIO 2.

IN other embodiments, the transistor level shifter circuit 21, the transistor HV _ P1, and the transistor HV _ P2 may be eliminated if the input voltages of the transistor MP _ IN3 and the transistor MP _ IN4, the transistor MP _ IN1, and the transistor MP _ IN2 are low voltages. In other embodiments, the transistors HV _ P1 and HV _ P2 may be common transistors in a low voltage environment.

In addition, the substrate bias unit 20 further includes a transistor HV _ PCAS2, a transistor HV _ P3, and a transistor MN _ DIO 1. The transistor HV _ PCAS2 and the transistor HV _ P3 are high voltage isolation bias transistors.

Specifically, the first terminal of the transistor HV _ PCAS2 is connected to the second terminal of the transistor MP _ BIAS2 to form a Q junction, the second terminal of the transistor HV _ PCAS2 is connected to the first terminal of the first resistor R1 to form the intermediate node O, and the control terminal of the transistor HV _ PCAS2 is connected to the third control voltage Vp _ cas _ BIAS, due to the addition of the transistor HV _ PCAS 2.

A first terminal of the transistor HV _ P3 is connected to the second terminals of the transistors MP _ IN3 and MP _ IN4, and a control terminal of the transistor HV _ P3 is connected to the second terminal of the transistor MP _ DIO2 and forms a P connection point. The second terminal and the control terminal of the transistor MN _ DIO1 are shorted and connected to the second terminal of the transistor HV _ P3, and the first terminal of the transistor MN _ DIO1 is grounded.

The level shift circuit 21 further includes a transistor HV _ NCAS1, and the transistor HV _ NCAS1 is a high voltage isolation bias transistor. A second terminal of the transistor HV _ NCAS1 is coupled to the second terminal of the transistor MP _ DIO2, a first terminal of the transistor HV _ NCAS1 is coupled to the second terminal of the transistor MN _ BIAS1, and a control terminal of the transistor HV _ NCAS1 is coupled to the fourth control voltage Vn _ cas _ BIAS.

In other embodiments, the transistor HV _ PCAS2, the transistor HV _ P3, the transistor MN _ DIO1, and the transistor HV _ NCAS1 may be eliminated when high voltage protection is not required.

In the present embodiment, the substrate voltage adjusting unit 30 is configured to adaptively adjust a voltage difference between the first terminal and the second terminal of the resistance unit according to the input common mode voltage to adjust the substrate voltage VNW. The self-adaptive adjustment means that the voltage difference between the first end and the second end of the resistance unit dynamically changes in real time according to the input common-mode voltage, so that the purpose of self-adjustment is achieved.

Further, the substrate voltage adjusting unit 30 is configured to dynamically adjust the current flowing through the resistance unit according to the magnitude of the input common mode voltage to change the substrate voltage VNW. In other embodiments, the substrate voltage adjusting unit 30 may also dynamically adjust the resistance of the resistor unit according to the magnitude of the input common mode voltage, or adjust both the current flowing through the resistor unit and the resistance of the resistor unit.

As shown in fig. 1 and 4, the substrate voltage adjusting unit 30 includes a transistor MP _ BIAS4, a transistor MP _ BIAS3, a transistor MP3, a transistor MP2, a transistor MP1, and a current mirror unit.

First terminals of the transistors MP _ BIAS4 and MP _ BIAS3 are connected to the power supply voltage Vdd, control terminals of the transistors MP _ BIAS4 and MP _ BIAS3 are connected to the first control voltage Vpbias, and a second terminal of the transistor MP _ BIAS3 is connected to the second terminal of the transistor MP _ BIAS2 and the Q connection point. First terminals of the transistors MP3, MP2, and MP1 are connected to the second terminal of the transistor MP _ BIAS4, control terminals of the transistors MP3 and MP2 are used for receiving the differential input signal INN _ G, INP _ G, and second terminals of the transistors MP3 and MP2 are grounded. The control terminal of the transistor MP1 is connected to a reference voltage Vref, which is formed by a constant voltage source. The current mirror unit is connected to the second terminal of the transistor MP1, the first terminal of the first resistor R1, and the intermediate node O. The substrates of the transistor MP3, the transistor MP2, and the transistor MP1 are connected to a first terminal of a first resistor R1 to receive a substrate voltage VNW.

The current mirror cell in the present embodiment includes a transistor MN _ BIAS3 and a transistor MN _ BIAS 2. A second terminal of the transistor MN _ BIAS3 is shorted to the control terminal and is connected to the second terminal of the transistor MP1 and the control terminal of the transistor MN _ BIAS2, a second terminal of the transistor MN _ BIAS2 is connected to the first terminal of the first resistor R1 and the intermediate node O, and first terminals of the transistor MN _ BIAS3 and the transistor MN _ BIAS2 are grounded.

In addition, the substrate voltage adjusting unit 30 further includes a transistor HV _ PCAS3, a transistor HV _ P5, a transistor HV _ P4, a transistor MN _ DIO3, and a transistor HV _ NCAS 2. The transistors HV _ PCAS3, HV _ P5 and HV _ P4 are high voltage isolation bias transistors.

Specifically, a first terminal of the transistor HV _ PCAS3 is connected to the second terminal of the transistor MP _ BIAS4, a second terminal of the transistor HV _ PCAS3 is connected to first terminals of the transistors MP3, MP2, and MP1, and a control terminal of the transistor HV _ PCAS3 is connected to the third control voltage.

A first terminal of the transistor HV _ P5 is connected to the second terminals of the transistors MP3 and MP2, and control terminals of the transistors HV _ P5 and HV _ P4 are connected to the second terminal of the transistor MP _ DIO2 and the point P connection. A first terminal of the transistor HV _ P4 is connected to the second terminal of the transistor MP1, and a second terminal of the transistor HV _ P4 is connected to the second terminal of the transistor MN _ BIAS 3.

The second terminal of the transistor MN _ DIO3 is connected to the second terminal of the transistor HV _ P5, the first terminal of the transistor MN _ DIO3 is grounded, and the second terminal of the transistor MN _ DIO3 is shorted to the control terminal. A second terminal of the transistor HV _ NCAS2 is coupled to the first terminal of the first resistor R1 and the intermediate node O, a first terminal of the transistor HV _ NCAS2 is coupled to a second terminal of the transistor MN _ BIAS2, and a control terminal of the transistor HV _ NCAS2 is coupled to the fourth control voltage Vn _ cas _ BIAS.

In other embodiments, when high voltage protection is not required, the transistor HV _ PCAS3, the transistor HV _ P5, the transistor HV _ P4, and the transistor HV _ NCAS2 may be eliminated, and the transistor MN _ DIO3 may also be eliminated.

As shown in fig. 1 and 5, in the present embodiment, the operational amplifier input circuit further includes a protection circuit 40. The protection circuit 40 includes a second resistor R2, a third resistor R3, a transistor HV _ SP1, a transistor HV _ SP2, and a first clamp circuit. The transistors HV _ SP1 and HV _ SP2 are high voltage isolation bias transistors.

A first terminal of the second resistor R2 is connected to the first input terminal INP, and a second terminal of the second resistor R2 is connected to a second terminal of the transistor HV _ SP 1. A first terminal of the third resistor R3 is coupled to the second input terminal INN, a second terminal of the third resistor R3 is coupled to a second terminal of the transistor HV _ SP2, and control terminals of the transistor HV _ SP1 and the transistor HV _ SP2 are coupled to a first terminal of the first resistor R1 for receiving the substrate voltage VNW. First terminals of the transistor HV _ SP1 and the transistor HV _ SP2 are connected to the first clamp circuit and are simultaneously used to output the differential input signal INP _ G, INN _ G.

IN the present embodiment, the transistor MP _ BIAS2, the transistor MP _ IN3, the transistor MP _ IN4, the transistor MP _ BIAS4, the transistor MP _ BIAS3, the transistor MP3, the transistor MP2, the transistor MP1, the transistor MP _ BIAS1, the transistor MP _ IN1, the transistor MP _ IN2, the transistor MP _ DIO1, the transistor MP _ DIO2, the transistor HV _ P1, the transistor HV _ P2, the transistor HV _ PCAS2, the transistor HV _ P3, the transistor HV _ PCAS1, the transistor HV _ PCAS3, the transistor HV _ P5, the transistor HV _ P4, the transistor HV _ SP1, and the transistor HV _ SP2 are P-type MOS transistors.

The transistors MN _ BIAS3, MN _ BIAS2, MN _ BIAS1, MN _ DIO1, HV _ NCAS1, MN _ DIO3 and HV _ NCAS2 are N-type MOS transistors.

In other embodiments, the N-type MOS transistor and the P-type MOS transistor may be interchanged.

The operation principle of the present embodiment will be described in detail with reference to fig. 1 to 5.

The substrate bias unit 20 sets a substrate voltage VNW of the transistors MP _ IN1 and MP _ IN2 IN the input stage unit 10 according to an input common mode voltage of the differential input signal INN _ G, INP _ P, wherein the substrate voltage VNW is:

VNW＝VGS+I1*R1

VGS is the gate-source voltage of the transistor MP _ IN3 and the transistor MP _ IN4, I1 is the current flowing through the resistor R1, and R1 is the resistance of the first resistor R1.

When the input common mode voltage is a low common mode voltage, typically 0V, the current output from the transistor MP _ BIAS4 flows into both the transistor MP3 and the transistor MP2, and the reference voltage Vref is typically about 500mV due to the setting of the reference voltage Vref, so that the transistor MP1 is in an off state. No current flows through the current mirror unit, and at this time, the current I1 flowing through the first resistor R1 is the sum of the currents flowing through the transistor MP _ BIAS2 and the transistor MP _ BIAS3, and the substrate voltage VNW provided by the intermediate node O increases, so that the turn-on voltage VTH of the transistor MP _ IN1 and the transistor MP _ IN2 is increased, so that the transistor MP _ IN1 and the transistor MP _ IN2 operate IN a saturation region, and the operational amplifier can operate normally.

When the input common mode voltage is a high common mode voltage, typically Vdd-1.5V, the transistor MP1 is in an on state, the transistors MP3 and MP2 are in an off state, and the current output from the transistor MP _ BIAS4 flows into the transistor MP 1. A current is also generated in the current mirror cell, and at this time, the current I1 flowing through the first resistor R1 is the sum of the currents flowing through the transistor MP _ BIAS2 and the transistor MP _ BIAS3 minus the current flowing through the transistor MN _ BIAS2, and the substrate voltage VNW provided by the intermediate node O becomes smaller, so that the source-drain voltage of the transistor MP _ BIAS1 has a larger margin.

As shown in fig. 6 and fig. 1, this embodiment further discloses a method for dynamically adjusting a substrate voltage of an operational amplifier input circuit, where the method includes:

s1, the substrate voltage VNW of the first differential transistor pair of the input stage unit 10 is set based on the input common mode voltage of the differential input signal INN _ G, INP _ G and through the second differential transistor pair and the resistance unit.

And S2, adaptively adjusting the voltage difference between the first end and the second end of the resistance unit according to the input common-mode voltage so as to adjust the substrate voltage VNW.

In addition, the method further comprises: the substrate voltage VNW is changed by dynamically adjusting the current flowing through the resistor unit and/or adjusting the resistance of the resistor unit according to the magnitude of the input common mode voltage.

In summary, the dynamic substrate voltage VNW can provide a better operating point for the input stage unit 10, so as to improve the performance of the circuit at low common mode voltage and high common mode voltage, such as the common mode rejection ratio.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. An operational amplifier input circuit, comprising:

an input stage cell comprising a first differential transistor pair for receiving a differential input signal;

the substrate bias unit comprises a second differential transistor pair and a resistance unit, wherein the first end of the resistance unit is used for outputting a substrate voltage provided for the first differential transistor pair of the input stage unit, the second end of the resistance unit is connected with the second differential transistor pair, and the second differential transistor pair is used for receiving differential input signals; and

and the substrate voltage adjusting unit is used for adaptively adjusting the voltage difference between the first end and the second end of the resistor unit according to the input common-mode voltage so as to adjust the substrate voltage.

2. The operational amplifier input circuit as claimed in claim 1, wherein the substrate voltage adjusting unit is configured to dynamically adjust a current flowing through the resistor unit and/or adjust a resistance of the resistor unit according to a magnitude of the input common mode voltage to change the substrate voltage.

3. The operational amplifier input circuit according to claim 1 or 2, wherein the substrate voltage adjusting unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a current mirror unit;

4. The op-amp input circuit of claim 1, wherein the substrate bias unit comprises:

the second transistor and the third transistor form a second differential transistor pair, the control ends of the second transistor and the third transistor are used for receiving the differential input signal, the first ends of the second transistor and the third transistor are connected with the second end of the first resistor, the second ends of the second transistor and the third transistor are grounded, and the substrates of the second transistor and the third transistor are connected with the first end of the resistor unit.

5. The operational amplifier input circuit as claimed in claim 1, wherein the input stage unit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor, a first terminal of the eleventh transistor is connected to the power voltage, a control terminal of the eleventh transistor is connected to the first control voltage, the twelfth transistor and the thirteenth transistor form a first differential transistor pair, the control terminals of the twelfth transistor and the thirteenth transistor are configured to receive the differential input signal, first terminals of the twelfth transistor and the thirteenth transistor are connected to a second terminal of the eleventh transistor, second terminals of the twelfth transistor and the thirteenth transistor are configured to output a differential current signal, and substrates of the twelfth transistor and the thirteenth transistor are connected to the first terminal of the resistance unit.

6. The operational amplifier input circuit according to claim 1 or 2, wherein the input stage unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

the substrate bias unit includes:

the second transistor and the third transistor form a second differential transistor pair, the control ends of the second transistor and the third transistor are used for receiving the differential input signal, the first ends of the second transistor and the third transistor are connected with the second end of the first resistor, the second ends of the second transistor and the third transistor are grounded, and the substrates of the second transistor and the third transistor are connected with the first end of the resistor unit;

the level shift circuit is connected with the first ends of the second transistor and the third transistor, the second end of the first resistor and the control ends of the seventeenth transistor and the eighteenth transistor, the level shift circuit controls the voltages of the control ends of the seventeenth transistor and the eighteenth transistor to follow the voltage variation of the first ends of the second transistor and the third transistor so as to clamp the voltage between the first end and the second end of the twelfth transistor and the voltage between the first end and the second end of the thirteenth transistor, the first end of the seventeenth transistor is connected with the second end of the twelfth transistor, the first end of the eighteenth transistor is connected with the second end of the thirteenth transistor, and the second ends of the seventeenth transistor and the eighteenth transistor are used for outputting differential current signals.

7. The operational amplifier input circuit as claimed in claim 6, wherein the level shifter circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

8. The op-amp input circuit of claim 7, wherein the substrate bias cell further comprises a twentieth transistor; the first end of the twentieth transistor is connected with the second ends of the second transistor and the third transistor, and the control end of the twentieth transistor is connected with the second end of the fifteenth transistor.

9. The operational amplifier input circuit of claim 7, wherein the substrate voltage regulating unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a current mirror unit;

10. The operational amplifier input circuit of claim 1, further comprising a protection circuit comprising a twenty-ninth transistor, a thirtieth transistor, and a first clamp circuit;

the second end of the twenty ninth transistor is coupled to the first input end, the second end of the thirty th transistor is coupled to the second input end, the control ends of the twenty ninth transistor and the thirty th transistor are connected with the first end of the resistance unit, and the first ends of the twenty ninth transistor and the thirty th transistor are connected with the first clamping circuit and are simultaneously used for outputting differential input signals.

11. A method of dynamically adjusting a substrate voltage of an operational amplifier input circuit, the operational amplifier input circuit comprising a resistor unit, and a first differential transistor pair and a second differential transistor pair receiving differential input signals, a first terminal of the resistor unit being for outputting the substrate voltage provided to the first differential transistor pair of the input stage unit, a second terminal of the resistor unit being connected to the second differential transistor pair, the method comprising:

12. The method of dynamically adjusting a substrate voltage of an op-amp input circuit of claim 11, further comprising dynamically adjusting a current through a resistive element and/or adjusting a resistance of the resistive element based on a magnitude of an input common mode voltage to change the substrate voltage.